Finalize S100 FPGA Z80 Onboard VGA/PS2 Support

- RomWBW will now "follow" the S100 monitors console selection for all 3 possibilities (USB Serial, Propeller Console, and Onboard VGA/PS2).
Update Doc
2026-02-07 23:13:13 -06:00 · 2024-09-04 17:15:23 -07:00 · 2024-09-04 12:22:58 -07:00 · 2024-09-04 11:40:36 -07:00 · 2024-09-04 11:25:41 -07:00 · 2024-09-04 10:46:25 -07:00
703 changed files with 8973 additions and 2034 deletions
--- a/Doc/ChangeLog.txt
+++ b/Doc/ChangeLog.txt
@@ -14,7 +14,7 @@ Version 3.5
 - DDW: Added support for Duodyne Media board
 - WBW: Auto restore TMS video on user reset (CP/M warm boot)
 - L?B: Added support for NABU w/ RomWBW Option Board
- M?P: Reorganization of Doc directory introducing subfolders
+- MAP: Reorganization of Doc directory introducing subfolders
 - WBW: Upgraded BBCBASIC to v5.00
 - W?S: Updated FLASH utility to v1.3.9
 - WBW: Support RCBus PS/2 Keyboard (EP/Sally)
@@ -27,6 +27,13 @@ Version 3.5
 - WBW: Added support for DS1305 RTC on S100 FPGA Z80
 - WBW: Added support for Les Bird's RCBus Graphics/Sound/Joystick module
 - WBW: Added support for Les Bird's Dual 16C550 UART module
+- WBW: Refactor UART driver for more flexible configuration
+- M?R: Added hour/minute/second display to timer app
+- WBW: Substantial customization of NZ-COM disk image
+- WBW: Refactor build post-processing (ZRC, ZZRCC, etc.)
+- MAP: Improved section Real Time Clock in User Guide document
+- WBW: Support for Hitachi HD44780-based LCD display
+- DRJ: Added support for Genesis STD Bus Z180 platform

 Version 3.4
 -----------
@@ -695,4 +702,4 @@ interrupts disabled the BIOS will now start OK even if some vagrant
 hardware is asserting an interrupt (DISKIO).  Seems like this is better
 anyway -- general idea is that we only enable interupts precisely
 when desired for very specific controled purposes since there is no
-concept of interrupt dispatching available.
+concept of interrupt dispatching available.
--- a/Doc/Contrib/ZSystem.txt
+++ b/Doc/Contrib/ZSystem.txt
@@ -20,7 +20,7 @@ Beyond the construction and integration of the actual DOS itself, the majority o

 The remainder of this document details the changes I made as I went along.  In all cases, my goal was to keep the result as close to the original distribution as possible.  I started by copying all of the files from the distribution (contained in zsdos2.zip) into Support\ZSDOS.  From there I tested, modified, updated, and customized as documented below.  Finally, I cherry picked files that made sense to include on the ZSystem ROM disks.

-1. CLOCKS.DAT has been updated to include the RomWBW clock driver, HBCLK.  I have also added the SIMHCLOK clock driver.
+1. CLOCKS.DAT has been updated to include the RomWBW clock driver, WBWCLK.  I have also added the SIMHCLOK clock driver.

 2. STAMPS.DAT has been replaced with an updated version.  The update was called STAMPS11.DAT and was found on the Walnut Creek CP/M CDROM.  The original version has a bug that prevents RSX (resident system extension) mode to load properly.

--- a/Anatomy.pdf
+++ b/Anatomy.pdf
--- a/Applications.pdf
+++ b/Applications.pdf
--- a/Catalog.pdf
+++ b/Catalog.pdf
--- a/Errata.pdf
+++ b/Errata.pdf
--- a/Applications.pdf
+++ b/Applications.pdf
--- a/Doc/RomWBW
+++ b/Doc/RomWBW
--- a/Doc/RomWBW
+++ b/Doc/RomWBW
--- a/Doc/Testing
+++ b/Doc/Testing
@@ -1,144 +0,0 @@
-SIMH (X)
----
- Test UART driver
- Test HDSK driver
-
-Zeta 1 (X)
------
- Test UART driver
- Test PPP detection (startup w/ and w/o PPP)
- Test boot to CRT
- Test PPPSD driver
- Test PPPCON driver (video & kbd)
- Test FD driver
- Test FDU app
-
-Zeta 2 (X)
------
- Test UART driver
- Test PPP detection (startup w/ and w/o PPP)
- Test boot to CRT
- Test PPPSD driver
- Test PPPCON driver (video & kbd)
- Test FD driver
- Test FDU app
-
-RCBus (X)
------
- Test SIO driver (Serial Module)
- Test ACIA driver (Dual Serial Module)
- Test IDE driver (Compact Flash Module)
- Test PPIDE driver (IDE Module)
- Test FD driver (SMC and WDC)
- Test FDU app (SMC and WDC)
-
-N8-2312 (X)
-------
- Test ASCI driver
- Test SD driver (CSIO mode)
- Test FD driver
- Test FDU app
- Test TMS driver (video & kbd)
-
-N8-2511 (X)
-------
- Test ASCI driver
- Test SD driver (Juha mode)
- Test FD driver
- Test FDU app
- Test TMS driver (video & kbd)
-
-SBC (X)
---
- Test UART driver
- Test PPIDE driver
- Test PPISD driver
- Test PRP detection
- Test boot to CRT console
-
-MK4 (X)
---
- Test ASCI driver
- Test IDE driver
- Test SD driver
- Test PRP detection
-
-RAMF (X)
----
- Test RAMF driver
-
-PRP (X)
---
- Test PRPSD driver
- Test PRPCON driver (video & kbd)
-
-SCG (X)
---
- Test TMS driver (video)
-
-VDU (X)
---
- Test CVDU driver (video & kbd)
-
-CVDU (X)
----
- Test CVDU driver (video & kbd)
-
-VGA (X)
---
- Test VGA driver (video & kbd)
-
-DIO (X)
---
- Test FD driver
- Test FDU app
- Test IDE driver
-
-DIO3 (X)
----
- Test FD driver
- Test FDU app
- Test PPIDE driver
-
-DIDE (X)
----
- Test FD driver
- Test FDU app
- Test IDE driver
-
-DSD (X)
---
- Test SD driver
-
-4UART (X)
-----
- Test UART driver
-
-
-UNA (X)
---
- General Startup
- Boot from disk functionality
- Image loading
- Monitor
- XM app
- ASSIGN app
- MODE app
- SYSCOPY app
- OSLDR app
- FDU app
- FDISK80 app
-
-GENERAL (X)
-------
- Boot to ROM
- Boot to Disk
- Boot to Monitor
- XM app
- XM port auto-detect
- ASSIGN app
- MODE app
- SYSCOPY app
- FDU app
- FDISK80 app
- TUNE app
--- a/ReadMe.md
+++ b/ReadMe.md
@@ -3,7 +3,7 @@
 **RomWBW ReadMe** \
 Version 3.5 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-15 Jul 2024
+04 Sep 2024

 # Overview

--- a/ReadMe.txt
+++ b/ReadMe.txt
@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-15 Jul 2024
+04 Sep 2024



--- a/Source/Apps/rtc.asm
+++ b/Source/Apps/rtc.asm
@@ -33,6 +33,8 @@
 ;
 ;[2023/07/07] v1.9 Support DUODYNE
 ;
+;[2024/09/02] v1.10  Support Genesis STD Z180
+;
 ; Constants
 ;
 mask_data	.EQU	%10000000	; RTC data line
@@ -52,6 +54,7 @@ PORT_RCZ280	.EQU	$C0		; RTC port for RCZ280
 PORT_MBC	.EQU	$70		; RTC port for MBC
 PORT_RPH	.EQU	$84		; RTC port for RHYOPHYRE
 PORT_DUO	.EQU	$94		; RTC port for DUODYNE
+PORT_STDZ180 .EQU $84         ; RTC Port for STD Bus Z180 board


 BDOS		.EQU	5		; BDOS invocation vector
@@ -1143,7 +1146,13 @@ HINIT:
 	CP	17		; DUODYNE
 	JP	Z,RTC_INIT2
 ;
-	; Unknown platform
+	LD	C,PORT_STDZ180
+	LD	DE,PLT_STDZ180
+	CP	21		; STD Z180
+	JP	Z,RTC_INIT2
+;
+
+; Unknown platform
 	LD	DE,PLTERR	; BIOS error message
 	LD	C,9		; BDOS string display function
 	CALL	BDOS		; Do it
@@ -1769,6 +1778,7 @@ PLT_RCZ280	.TEXT	", RCBus Z280 RTC Module Latch Port 0xC0\r\n$"
 PLT_MBC		.TEXT	", MBC RTC Latch Port 0x70\r\n$"
 PLT_RPH		.TEXT	", RHYOPHYRE RTC Latch Port 0x84\r\n$"
 PLT_DUO		.TEXT	", DUODYNE RTC Latch Port 0x70\r\n$"
+PLT_STDZ180 .TEXT ", STD Z180 RTC Module latch port 0x84\r\n$"

 ;
 ; Generic FOR-NEXT loop algorithm
--- a/Source/Apps/timer.asm
+++ b/Source/Apps/timer.asm
--- a/Source/Doc/Build.cmd
+++ b/Source/Doc/Build.cmd
@@ -11,12 +11,12 @@ set PATH=%TOOLS%\gpp;%PATH%

 if not "%1"=="" (call :GenDoc %1 & goto :eof)

-call :GenDoc ReadMe
-call :GenDoc UserGuide
-call :GenDoc SystemGuide
-call :GenDoc Applications
-call :GenDoc Catalog
-call :GenDoc Errata
+call :GenDoc ReadMe || exit /b
+call :GenDoc UserGuide || exit /b
+call :GenDoc SystemGuide || exit /b
+call :GenDoc Applications || exit /b
+call :GenDoc Catalog || exit /b
+call :GenDoc Errata || exit /b

 if exist ReadMe.gfm copy Readme.gfm ..\..\ReadMe.md || exit /b
 if exist ReadMe.txt copy ReadMe.txt ..\..\ReadMe.txt || exit /b
--- a/Source/Doc/Catalog.md
+++ b/Source/Doc/Catalog.md
@@ -217,9 +217,9 @@ on using the applications and files listed.
 | `INITDIR.COM`  | ZSDOS      | ZSDOS Prepare disks for P2DOS Stamps |
 | `KERMIT.COM`   |     --     | Generic CP/M 2.2 Kermit communication application |
 | `LBREXT.COM`   |     --     | Extract library files |
-| `LDDS.COM`     | ZSDOS      | Clock driver |
-| `LDNZT.COM`    | ZSDOS      | Clock driver |
-| `LDP2D.COM`    | ZSDOS      | Clock driver |
+| `LDDS.COM`     | ZSDOS      | Load DateStamper date/time stamping resident extension |
+| `LDNZT.COM`    | ZSDOS      | Load NZT date/time stamping resident extension |
+| `LDP2D.COM`    | ZSDOS      | Load P2DOS date/time stamping resident extension |
 | `LIB.COM`      |     --     | DRI Library manager |
 | `LINK.COM`     |     --     | DRI CPM relocatable linker |
 | `LOAD.COM`     |     --     | DRI hex file loader into memory |
@@ -229,7 +229,7 @@ on using the applications and files listed.
 | `PMARC.COM`    |     --     | LHA file compressor |
 | `PMEXT.COM`    |     --     | Extractor for PMARC archives |
 | `PUTBG.COM`    | ZSDOS      | ZSDOS Prepare disk for backgrounder |
-| `PUTDS.COM`    | ZSDOS      | ZSDOS Prepare disk for datestamper |
+| `PUTDS.COM`    | ZSDOS      | ZSDOS Prepare disk for datestamper date/time stamping|
 | `RELOG.COM`    | ZSDOS      | ZSDOS relog disks after program that bypasses BDOS |
 | `RMAC.COM`     |     --     | DRI Relocatable Macro Assembler |
 | `SETTERM.COM`  | ZSDOS      | ZSDOS Installs terminal control codes into DateSamper utilities |
--- a/Source/Doc/Graphics/BankSwitchedMemory.pdf
+++ b/Source/Doc/Graphics/BankSwitchedMemory.pdf
--- a/Source/Doc/Graphics/BankSwitchedMemory.png
+++ b/Source/Doc/Graphics/BankSwitchedMemory.png
--- a/Source/Doc/Graphics/BankSwitchedMemory.svg
+++ b/Source/Doc/Graphics/BankSwitchedMemory.svg
@@ -0,0 +1,366 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
+<!-- Generated by Microsoft Visio, SVG Export BankSwitchedMemory.svg Page-1 -->
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:ev="http://www.w3.org/2001/xml-events"
+		width="6.51042in" height="5.73361in" viewBox="0 0 468.75 412.82" xml:space="preserve" color-interpolation-filters="sRGB"
+		class="st22">
+	<style type="text/css">
+	<![CDATA[
+		.st1 {fill:#c0c0c0;stroke:#000000;stroke-linecap:round;stroke-linejoin:round;stroke-width:0.24}
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+		.st4 {fill:#ffffff;stroke:none;stroke-linecap:butt;stroke-width:7.2}
+		.st5 {fill:#000000;font-family:Calibri;font-size:0.75em}
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+		.st22 {fill:none;fill-rule:evenodd;font-size:12px;overflow:visible;stroke-linecap:square;stroke-miterlimit:3}
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+
+	<defs id="Markers">
+		<g id="lend4">
+			<path d="M 2 1 L 0 0 L 2 -1 L 2 1 " style="stroke:none"/>
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+			<path
+					d="M 0 0.75 C -0.414214 0.75 -0.75 0.414214 -0.75 0 -0.75 -0.414214 -0.414214 -0.75 0 -0.75 0.414214 -0.75 0.75 -0.414214 0.75 0 0.75 0.414214 0.414214 0.75 0 0.75 Z "
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+			<g id="shape15-4" transform="translate(0,-172.8)">
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+			<g id="shape16-6">
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+		</g>
+		<g id="group9-8" transform="translate(216.75,-282.72)">
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+			<g id="shape11-11" transform="translate(0,-57.6)">
+				<title>Sheet.11</title>
+				<path d="M0 412.82 L157.75 412.82 L169.15 401.41 L11.41 401.41 L0 412.82 Z" class="st1"/>
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+			<g id="shape12-13">
+				<title>Sheet.12</title>
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+			</g>
+		</g>
+		<g id="group5-15" transform="translate(216.75,-340.32)">
+			<title>Data block</title>
+			<g id="shape6-16" transform="translate(157.745,0)">
+				<title>Sheet.6</title>
+				<path d="M0 412.82 L11.41 401.41 L11.41 379.81 L0 391.22 L0 412.82 Z" class="st1"/>
+			</g>
+			<g id="shape7-18" transform="translate(0,-21.6)">
+				<title>Sheet.7</title>
+				<path d="M0 412.82 L157.75 412.82 L169.15 401.41 L11.41 401.41 L0 412.82 Z" class="st1"/>
+			</g>
+			<g id="shape8-20">
+				<title>Sheet.8</title>
+				<rect x="0" y="391.22" width="157.745" height="21.6" class="st2"/>
+			</g>
+		</g>
+		<g id="shape2-22" transform="translate(65.55,486.457) rotate(180)">
+			<title>Sheet.2</title>
+			<desc>$FE00</desc>
+			<path d="M0 412.82 L36 412.82" class="st3"/>
+			<rect x="-29.1072" y="-418.22" width="22.2144" height="10.7998" transform="rotate(180)" class="st4"/>
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+		<g id="shape3-27" transform="translate(65.55,542.541) rotate(180)">
+			<title>Sheet.3</title>
+			<desc>$D000</desc>
+			<path d="M0 412.82 L36 412.82" class="st3"/>
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+		<g id="shape17-32" transform="translate(433.37,106.7) rotate(90)">
+			<title>Sheet.17</title>
+			<desc>$8000</desc>
+			<path d="M0 412.82 L46.25 412.82" class="st3"/>
+			<rect x="-38.3323" y="-420.02" width="30.4102" height="14.4001" transform="rotate(180)" class="st6"/>
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+			<title>3D stack middle</title>
+			<g id="shape19-38" transform="translate(77.0909,0)">
+				<title>Sheet.19</title>
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+			</g>
+			<g id="shape20-40">
+				<title>Sheet.20</title>
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+			</g>
+		</g>
+		<g id="group21-42" transform="translate(297.405,-297.12)">
+			<title>3D stack middle.21</title>
+			<g id="shape22-43" transform="translate(77.0909,0)">
+				<title>Sheet.22</title>
+				<path d="M0 412.82 L7.2 405.62 L7.2 384.02 L0 391.22 L0 412.82 Z" class="st1"/>
+			</g>
+			<g id="shape23-45">
+				<title>Sheet.23</title>
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+			</g>
+		</g>
+		<g id="group24-47" transform="translate(297.405,-318.72)">
+			<title>3D stack middle.24</title>
+			<g id="shape25-48" transform="translate(77.0909,0)">
+				<title>Sheet.25</title>
+				<path d="M0 412.82 L7.2 405.62 L7.2 384.02 L0 391.22 L0 412.82 Z" class="st1"/>
+			</g>
+			<g id="shape26-50">
+				<title>Sheet.26</title>
+				<rect x="0" y="391.22" width="77.0909" height="21.6" class="st2"/>
+			</g>
+		</g>
+		<g id="shape27-52" transform="translate(220.314,-340.32)">
+			<title>Sheet.27</title>
+			<desc>HBIOS Proxy (RST 08)</desc>
+			<rect x="0" y="391.22" width="154.182" height="21.6" class="st8"/>
+			<text x="34.06" y="405.02" class="st9">HBIOS Proxy (RST 08)</text>		</g>
+		<g id="shape28-55" transform="translate(220.314,-109.92)">
+			<title>Sheet.28</title>
+			<desc>Application Area (TPA)</desc>
+			<rect x="0" y="237.402" width="154.836" height="175.418" class="st8"/>
+			<text x="22.5" y="328.71" class="st7">Application Area (TPA)</text>		</g>
+		<g id="shape29-58" transform="translate(220.314,-282.72)">
+			<title>Sheet.29</title>
+			<desc>Operating System CP/M or ZSYS</desc>
+			<rect x="0" y="355.22" width="77.0909" height="57.6" class="st8"/>
+			<text x="2.38" y="375.02" class="st9">Operating System  <tspan x="11.08" dy="2.4em" class="st10">CP/M or ZSYS</tspan></text>		</g>
+		<g id="shape30-62" transform="translate(297.405,-318.72)">
+			<title>Sheet.30</title>
+			<desc>CBIOS</desc>
+			<rect x="0" y="391.22" width="77.0909" height="21.6" class="st8"/>
+			<text x="26.29" y="405.02" class="st9">CBIOS</text>		</g>
+		<g id="shape31-65" transform="translate(297.405,-297.12)">
+			<title>Sheet.31</title>
+			<desc>BDOS</desc>
+			<rect x="0" y="391.22" width="77.0909" height="21.6" class="st8"/>
+			<text x="27.14" y="405.02" class="st9">BDOS</text>		</g>
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+			<desc>CCP</desc>
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+		<g id="group33-71" transform="translate(72.75,-109.92)">
+			<title>Data block.33</title>
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+				<title>Sheet.34</title>
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+		</g>
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+			<path d="M0 412.82 L360 412.82" class="st11"/>
+		</g>
+		<g id="shape38-81" transform="translate(72.75,-109.92)">
+			<title>Sheet.38</title>
+			<desc>HBIOS (Hardware Drivers)</desc>
+			<rect x="0" y="297.62" width="108" height="115.2" class="st8"/>
+			<text x="38.76" y="351.62" class="st7">HBIOS <tspan x="7.61" dy="1.2em" class="st10">(Hardware Drivers)</tspan></text>		</g>
+		<g id="shape39-85" transform="translate(22.35,-109.92)">
+			<title>Sheet.39</title>
+			<path d="M0 412.82 L338.4 412.82" class="st11"/>
+		</g>
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+			<title>Sheet.40</title>
+			<path d="M0 412.82 L360 412.82" class="st11"/>
+		</g>
+		<g id="shape43-91" transform="translate(-397.67,302.9) rotate(-90)">
+			<title>Sheet.43</title>
+			<desc>Z80 CPU Address Space</desc>
+			<rect x="0" y="398.42" width="252" height="14.4" class="st12"/>
+			<text x="69.04" y="409.22" class="st7">Z80 CPU Address Space</text>		</g>
+		<g id="shape41-94" transform="translate(-383.27,302.9) rotate(-90)">
+			<title>Sheet.41</title>
+			<desc>Banked Lower 32K</desc>
+			<rect x="0" y="398.42" width="115.2" height="14.4" class="st12"/>
+			<text x="12.48" y="409.22" class="st7">Banked Lower 32K</text>		</g>
+		<g id="shape42-97" transform="translate(-383.27,187.7) rotate(-90)">
+			<title>Sheet.42</title>
+			<desc>Fixed Upper 32K</desc>
+			<rect x="0" y="398.42" width="136.8" height="14.4" class="st12"/>
+			<text x="28.39" y="409.22" class="st7">Fixed Upper 32K</text>		</g>
+		<g id="shape1-100" transform="translate(65.55,463.72) rotate(180)">
+			<title>Sheet.1</title>
+			<desc>$10000</desc>
+			<path d="M0 412.82 L36 412.82" class="st3"/>
+			<rect x="-31.6846" y="-418.22" width="27.3691" height="10.7998" transform="rotate(180)" class="st6"/>
+			<text x="-31.68" y="-410.12" transform="rotate(180)" class="st5">$10000</text>		</g>
+		<g id="shape4-105" transform="translate(65.55,715.72) rotate(180)">
+			<title>Sheet.4</title>
+			<desc>$0000</desc>
+			<path d="M0 412.82 L36 412.82" class="st3"/>
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+		<g id="shape44-110" transform="translate(798.77,50.9) rotate(90)">
+			<title>Bracket</title>
+			<path d="M0 412.82 A6.11239 6.11239 0 0 1 5.4 407.42 L64.22 407.42 A6.11239 6.11239 -180 0 0 69.62 402.02 A6.11239 6.11239
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+		</g>
+		<g id="shape45-113" transform="translate(0.750002,-52.32)">
+			<title>Sheet.45</title>
+			<desc>Bank 0</desc>
+			<rect x="0" y="398.42" width="36" height="14.4" class="st12"/>
+			<text x="5.69" y="408.32" class="st5">Bank 0</text>		</g>
+		<g id="shape47-116" transform="translate(252.75,-52.32)">
+			<title>Sheet.47</title>
+			<desc>App/OS Banks</desc>
+			<rect x="0" y="398.42" width="108" height="14.4" class="st12"/>
+			<text x="28.09" y="408.32" class="st5">App/OS Banks</text>		</g>
+		<g id="shape48-119" transform="translate(360.75,-52.32)">
+			<title>Sheet.48</title>
+			<desc>Bank N-1</desc>
+			<rect x="0" y="398.42" width="36" height="14.4" class="st12"/>
+			<text x="1.41" y="408.32" class="st5">Bank N-1</text>		</g>
+		<g id="shape49-122" transform="translate(396.75,-52.32)">
+			<title>Sheet.49</title>
+			<desc>Bank N</desc>
+			<rect x="0" y="398.42" width="36" height="14.4" class="st12"/>
+			<text x="5.06" y="408.32" class="st5">Bank N</text>		</g>
+		<g id="shape50-125" transform="translate(36.75,-52.32)">
+			<title>Sheet.50</title>
+			<desc>• • •</desc>
+			<rect x="0" y="398.42" width="216" height="14.4" class="st12"/>
+			<text x="91.49" y="408.62" class="st9">•    •    •</text>		</g>
+		<g id="shape51-128" transform="translate(375.15,715.72) rotate(180)">
+			<title>Bracket.51</title>
+			<path d="M0 412.82 A8.14985 8.14985 0 0 1 7.2 405.62 L36 405.62 A8.14985 8.14985 -180 0 0 43.2 398.42 A8.14985 8.14985
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+		</g>
+		<g id="shape55-131" transform="translate(396.75,-66.72)">
+			<title>Sheet.55</title>
+			<path d="M0 187.31 L9 187.31 A9 9 0 0 1 18 196.31 L18 404.78" class="st14"/>
+		</g>
+		<g id="shape56-137" transform="translate(0.750002,-37.92)">
+			<title>Sheet.56</title>
+			<desc>Physical RAM (32K per bank)</desc>
+			<rect x="0" y="398.42" width="432" height="14.4" class="st12"/>
+			<text x="157.88" y="408.62" class="st9">Physical RAM (32K per bank)</text>		</g>
+		<g id="shape57-140" transform="translate(180.75,715.72) rotate(180)">
+			<title>Bracket.57</title>
+			<desc>`</desc>
+			<path d="M0 412.82 A8.14984 8.14984 0 0 1 7.2 405.62 L46.8 405.62 A8.14984 8.14984 -180 0 0 54 398.42 A8.14984 8.14984
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+		<g id="shape58-145" transform="translate(449.57,360.5) rotate(90)">
+			<title>Sheet.58</title>
+			<path d="M0 412.82 L34.16 412.82" class="st17"/>
+		</g>
+		<g id="group60-148" transform="translate(36.75,-0.12)">
+			<title>3D stack top</title>
+			<desc>RAM Disk</desc>
+			<g id="shape61-149" transform="translate(208.8,0)">
+				<title>Sheet.61</title>
+				<path d="M0 412.82 L7.09 405.73 L7.09 387.73 L0 394.82 L0 412.82 Z" class="st1"/>
+			</g>
+			<g id="shape62-151" transform="translate(0,-18)">
+				<title>Sheet.62</title>
+				<path d="M0 412.82 L208.8 412.82 L215.89 405.73 L7.09 405.73 L0 412.82 Z" class="st1"/>
+			</g>
+			<g id="shape63-153">
+				<title>Sheet.63</title>
+				<rect x="0" y="394.82" width="208.8" height="18" class="st2"/>
+			</g>
+			<g id="shape60-155">
+				<text x="88.83" y="406.22" class="st16">RAM Disk</text>			</g>
+		</g>
+		<g id="shape64-157" transform="translate(-59.27,84.02) rotate(-90)">
+			<title>Pointer (1-D)</title>
+			<path d="M1.71 412.82 L2.07 412.82 L16.08 412.82" class="st18"/>
+		</g>
+		<g id="shape65-166" transform="translate(-95.27,108.5) rotate(-90)">
+			<title>Pointer (1-D).65</title>
+			<path d="M1.71 412.82 L2.07 412.82 L18.96 412.82" class="st18"/>
+		</g>
+		<g id="shape66-173" transform="translate(-52.07,122.9) rotate(-90)">
+			<title>Pointer (1-D).66</title>
+			<path d="M1.71 412.82 L2.07 412.82 L11.76 412.82" class="st18"/>
+		</g>
+		<g id="shape67-180" transform="translate(-105.35,137.3) rotate(-90)">
+			<title>Pointer (1-D).67</title>
+			<path d="M1.71 412.82 L2.07 412.82 L26.16 412.82" class="st18"/>
+		</g>
+		<g id="shape70-187" transform="translate(228.935,-227.945) scale(-1,1)">
+			<title>Sheet.70</title>
+			<path d="M2.65 293.24 L3.01 293.24 L76.08 293.24 A22.5 22.5 0 0 1 98.58 315.74 L98.58 404.78" class="st20"/>
+		</g>
+		<g id="shape68-195" transform="translate(87.15,-289.92)">
+			<title>Sheet.68</title>
+			<desc>HBIOS Function Call w/ Bank Switch</desc>
+			<rect x="0" y="384.02" width="86.4" height="28.8" class="st2"/>
+			<text x="7.14" y="395.72" class="st5">HBIOS Function Call <tspan x="15.11" dy="1.2em" class="st10">w/ Bank Switch</tspan></text>		</g>
+		<g id="shape69-199" transform="translate(0.75,-390.72)">
+			<title>Sheet.69</title>
+			<desc>RomWBW Bank Switched Memory Layout</desc>
+			<rect x="0" y="391.22" width="432" height="21.6" class="st21"/>
+			<text x="113.82" y="405.62" class="st7">RomWBW Bank Switched Memory Layout</text>		</g>
+		<g id="shape59-202" transform="translate(665.566,362.226) rotate(90.2396)">
+			<title>Sheet.59</title>
+			<path d="M0 412.82 L27.11 412.82" class="st17"/>
+		</g>
+		<g id="shape52-205" transform="translate(16.33,324.5) rotate(-90)">
+			<title>Sheet.52</title>
+			<desc>Fixed Mapping of Upper 32K to Last Bank</desc>
+			<rect x="0" y="398.42" width="172.8" height="14.4" class="st8"/>
+			<text x="11.1" y="408.32" class="st5">Fixed Mapping of Upper 32K to Last Bank</text>		</g>
+		<g id="shape72-208" transform="translate(331.95,-66.72)">
+			<title>Sheet.72</title>
+			<path d="M0 384.02 L0 387.62 A3.59999 3.59999 -180 0 0 3.6 391.22 L45.4 391.22 A5 5 0 0 1 50.4 396.22 L50.4 404.78"
+					class="st14"/>
+		</g>
+		<g id="shape74-213" transform="translate(126.75,-66.72) scale(-1,1)">
+			<title>Sheet.74</title>
+			<path d="M0 384.02 L0 387.62 A3.59999 3.59999 -180 0 0 3.6 391.22 L103 391.22 A5 5 0 0 1 108 396.22 L108 404.78"
+					class="st14"/>
+		</g>
+	</g>
+</svg>
--- a/Source/Doc/Graphics/BankSwitchedMemory.vsd
+++ b/Source/Doc/Graphics/BankSwitchedMemory.vsd
--- a/Source/Doc/Graphics/CharacterEmulationVideoServices.pdf
+++ b/Source/Doc/Graphics/CharacterEmulationVideoServices.pdf
--- a/Source/Doc/Graphics/CharacterEmulationVideoServices.png
+++ b/Source/Doc/Graphics/CharacterEmulationVideoServices.png
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+++ b/Source/Doc/Graphics/CharacterEmulationVideoServices.svg
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+		.st3 {font-size:1em}
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+		.st7 {fill:#000000;font-family:Calibri;font-size:0.666664em;font-weight:bold}
+		.st8 {fill:#ffffff;stroke:#000000;stroke-linecap:round;stroke-linejoin:round;stroke-width:0.24}
+		.st9 {fill:#00ff00;stroke:none;stroke-linecap:round;stroke-linejoin:round;stroke-width:0.75}
+		.st10 {fill:#e6e6e6;stroke:none;stroke-linecap:round;stroke-linejoin:round;stroke-width:0.75}
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+		</g>
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+		</g>
+		<g id="shape1-5" transform="translate(108.539,-315.375)">
+			<title>Sheet.1</title>
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+		</g>
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+			<path d="M0 180.75 L27 180.75" class="st7"/>
+		</g>
+		<g id="shape71-160" transform="translate(162.375,-58.875)">
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+			<text x="7.12" y="178.65" class="st8">Floppy</text>		</g>
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+			<desc>Hard</desc>
+			<rect x="0" y="171.75" width="36" height="9.00001" class="st5"/>
+			<text x="10.1" y="178.65" class="st8">Hard</text>		</g>
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+			<path d="M0 180.75 L99 180.75" class="st7"/>
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+		<g id="shape74-169" transform="translate(198.375,-49.875)">
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+			<desc>4</desc>
+			<rect x="0" y="171.75" width="36" height="9.00001" class="st5"/>
+			<text x="15.97" y="178.65" class="st8">4</text>		</g>
+		<g id="shape75-172" transform="translate(234.375,-49.875)">
+			<title>Sheet.75</title>
+			<desc>2</desc>
+			<rect x="0" y="171.75" width="36" height="9.00001" class="st5"/>
+			<text x="15.97" y="178.65" class="st8">2</text>		</g>
+		<g id="shape76-175" transform="translate(270.375,-49.875)">
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+			<desc>1</desc>
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+			<text x="15.97" y="178.65" class="st8">1</text>		</g>
+		<g id="shape78-178" transform="translate(198.375,-58.875)">
+			<title>Sheet.78</title>
+			<desc>ROM App / Boot Slice</desc>
+			<rect x="0" y="171.75" width="108" height="9.00001" class="st5"/>
+			<text x="18.99" y="178.65" class="st8">ROM App / Boot Slice</text>		</g>
+		<g id="shape79-181" transform="translate(18.375,-0.375)">
+			<title>Sheet.79</title>
+			<desc>ROM Apps: 0=Monitor 1=BASIC 2=Forth 3=Game 4=CP/M 2.2 5=Z-Sys...</desc>
+			<rect x="0" y="171.75" width="288" height="9" class="st5"/>
+			<text x="19.9" y="178.05" class="st9">ROM Apps:   0=Monitor   1=BASIC   2=Forth   3=Game   4=CP/M 2.2   5=Z-System   6=Net Boot   7=User</text>		</g>
+		<g id="shape80-184" transform="translate(0.375,-0.375)">
+			<title>Sheet.80</title>
+			<rect x="0" y="0.750005" width="324" height="180" class="st10"/>
+		</g>
+		<g id="shape81-186" transform="translate(18.375,-72.375)">
+			<title>Sheet.81</title>
+			<path d="M0 180.75 L144 180.75" class="st4"/>
+		</g>
+		<g id="shape82-189" transform="translate(199.125,99.375) rotate(90)">
+			<title>Sheet.82</title>
+			<path d="M0 180.75 L18 180.75" class="st4"/>
+		</g>
+		<g id="shape84-192" transform="translate(18.375,-72.375)">
+			<title>Sheet.84</title>
+			<desc>Console</desc>
+			<rect x="0" y="162.75" width="72" height="18" class="st5"/>
+			<text x="16.61" y="175.35" class="st6">Console</text>		</g>
+		<g id="shape85-195" transform="translate(162.375,-72.375)">
+			<title>Sheet.85</title>
+			<path d="M0 180.75 L144 180.75" class="st4"/>
+		</g>
+		<g id="shape86-198" transform="translate(271.125,99.375) rotate(90)">
+			<title>Sheet.86</title>
+			<path d="M0 180.75 L18 180.75" class="st4"/>
+		</g>
+		<g id="shape87-201" transform="translate(487.125,99.375) rotate(90)">
+			<title>Sheet.87</title>
+			<path d="M0 180.75 L18 180.75" class="st4"/>
+		</g>
+		<g id="shape88-204" transform="translate(90.375,-72.375)">
+			<title>Sheet.88</title>
+			<desc>Boot</desc>
+			<rect x="0" y="162.75" width="216" height="18" class="st5"/>
+			<text x="96.4" y="175.35" class="st6">Boot</text>		</g>
+	</g>
+</svg>
--- a/Source/Doc/Graphics/hd1k.pdf
+++ b/Source/Doc/Graphics/hd1k.pdf
--- a/Source/Doc/Graphics/hd1k.png
+++ b/Source/Doc/Graphics/hd1k.png
--- a/Source/Doc/Graphics/hd1k.svg
+++ b/Source/Doc/Graphics/hd1k.svg
--- a/Source/Doc/Graphics/hd512.pdf
+++ b/Source/Doc/Graphics/hd512.pdf
--- a/Source/Doc/Graphics/hd512.png
+++ b/Source/Doc/Graphics/hd512.png
--- a/Source/Doc/Graphics/hd512.svg
+++ b/Source/Doc/Graphics/hd512.svg
@@ -0,0 +1,236 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
+<!-- Generated by Microsoft Visio, SVG Export hd512.svg Page-1 -->
+<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:ev="http://www.w3.org/2001/xml-events"
+		width="6.51389in" height="3.90694in" viewBox="0 0 469 281.3" xml:space="preserve" color-interpolation-filters="sRGB"
+		class="st16">
+	<style type="text/css">
+	<![CDATA[
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+		.st3 {fill:#ffffff;stroke:#000000;stroke-linecap:round;stroke-linejoin:round;stroke-width:0.24}
+		.st4 {fill:#000000;font-family:Calibri;font-size:0.666664em}
+		.st5 {fill:none;stroke:#000000;stroke-linecap:round;stroke-linejoin:round;stroke-width:1}
+		.st6 {fill:#d8d8d8;stroke:#000000;stroke-linecap:round;stroke-linejoin:round;stroke-width:1}
+		.st7 {fill:none;stroke:none;stroke-linecap:round;stroke-linejoin:round;stroke-width:0.75}
+		.st8 {marker-start:url(#mrkr4-40);stroke:#000000;stroke-linecap:round;stroke-linejoin:round;stroke-width:0.24}
+		.st9 {fill:#000000;fill-opacity:1;stroke:#000000;stroke-opacity:1;stroke-width:0.08695652173913}
+		.st10 {fill:#000000;font-family:Calibri;font-size:0.499992em}
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+		.st12 {stroke:#000000;stroke-linecap:round;stroke-linejoin:round;stroke-width:0.25}
+		.st13 {marker-end:url(#mrkr9-69);marker-start:url(#mrkr4-40);stroke:#000000;stroke-linecap:round;stroke-linejoin:round;stroke-width:0.24}
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+	</style>
+
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+		<g id="lend4">
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+		<marker id="mrkr4-40" class="st9" refX="21.5" orient="auto" markerUnits="strokeWidth" overflow="visible">
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+	</defs>
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+		<g id="shape69-1" transform="translate(0.5,-252)">
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+			<text x="61.63" y="272.3" class="st2">RomWBW Hard Disk Anatomy (Classic / hd512)</text>		</g>
+		<g id="shape259-4" transform="translate(50.9,-151.2)">
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+			<desc>0</desc>
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+			<text x="5.17" y="276.5" class="st4">1</text>		</g>
+		<g id="shape261-10" transform="translate(79.7,-151.2)">
+			<title>Sheet.261</title>
+			<desc>2</desc>
+			<rect x="0" y="266.9" width="14.4" height="14.4" class="st3"/>
+			<text x="5.17" y="276.5" class="st4">2</text>		</g>
+		<g id="shape262-13" transform="translate(94.1,-151.2)">
+			<title>Sheet.262</title>
+			<desc>3</desc>
+			<rect x="0" y="266.9" width="14.4" height="14.4" class="st3"/>
+			<text x="5.17" y="276.5" class="st4">3</text>		</g>
+		<g id="shape263-16" transform="translate(108.5,-151.2)">
+			<title>Sheet.263</title>
+			<desc>. . .</desc>
+			<rect x="0" y="266.9" width="72" height="14.4" class="st3"/>
+			<text x="27.54" y="276.5" class="st4">.   .   .</text>		</g>
+		<g id="shape264-19" transform="translate(180.5,-151.2)">
+			<title>Sheet.264</title>
+			<desc>N</desc>
+			<rect x="0" y="266.9" width="14.4" height="14.4" class="st3"/>
+			<text x="4.62" y="276.5" class="st4">N</text>		</g>
+		<g id="shape265-22" transform="translate(50.9,-151.2)">
+			<title>Sheet.265</title>
+			<rect x="0" y="266.9" width="144" height="14.4" class="st5"/>
+		</g>
+		<g id="shape266-24" transform="translate(50.9,-122.4)">
+			<title>Sheet.266</title>
+			<desc>RomWBW Hard Disk (IDE/ATA/ATAPI/CF/SD/USB)</desc>
+			<rect x="0" y="266.9" width="360" height="14.4" class="st6"/>
+			<text x="99.2" y="276.5" class="st4">RomWBW Hard Disk (IDE/ATA/ATAPI/CF/SD/USB)</text>		</g>
+		<g id="shape267-27" transform="translate(230.9,-136.8)">
+			<title>Sheet.267</title>
+			<desc>FAT Partition</desc>
+			<rect x="0" y="266.9" width="165.6" height="14.4" class="st1"/>
+			<text x="61.69" y="276.5" class="st4">FAT Partition</text>		</g>
+		<g id="shape268-30" transform="translate(101.3,-43.2)">
+			<title>Sheet.268</title>
+			<desc>Sector 0</desc>
+			<rect x="0" y="266.9" width="72" height="14.4" class="st7"/>
+			<text x="22.71" y="276.5" class="st4">Sector 0</text>		</g>
+		<g id="shape269-33" transform="translate(158.9,-57.6)">
+			<title>Sheet.269</title>
+			<rect x="0" y="266.9" width="14.4" height="14.4" class="st3"/>
+		</g>
+		<g id="shape270-35" transform="translate(50.9,-64.8)">
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+			<path d="M0 228.86 L0 229.22 L0 276.8 A4.5 4.5 -180 0 0 4.5 281.3 L46.08 281.3" class="st8"/>
+		</g>
+		<g id="shape271-41" transform="translate(209.3,-43.2)">
+			<title>Sheet.271</title>
+			<desc>Type 06</desc>
+			<rect x="0" y="274.1" width="43.2" height="7.2" class="st3"/>
+			<text x="11.99" y="279.5" class="st10">Type 06</text>		</g>
+		<g id="shape272-44" transform="translate(209.3,-36)">
+			<title>Sheet.272</title>
+			<rect x="0" y="274.1" width="43.2" height="7.2" class="st3"/>
+		</g>
+		<g id="shape273-46" transform="translate(209.3,-28.8)">
+			<title>Sheet.273</title>
+			<rect x="0" y="274.1" width="43.2" height="7.2" class="st3"/>
+		</g>
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+			<title>Sheet.274</title>
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+		</g>
+		<g id="shape275-50" transform="translate(202.1,-7.19997)">
+			<title>Sheet.275</title>
+			<desc>Partition Table</desc>
+			<rect x="0" y="266.9" width="57.6" height="14.4" class="st7"/>
+			<text x="4.92" y="276.5" class="st4">Partition Table</text>		</g>
+		<g id="shape276-53" transform="translate(339.4,65.2999) rotate(90)">
+			<title>Sheet.276</title>
+			<path d="M0 98.42 L0 258.8 A22.5 22.5 -180 0 0 22.5 281.3 L44.88 281.3" class="st11"/>
+		</g>
+		<g id="shape277-59" transform="translate(-71.9999,259.7) rotate(-90)">
+			<title>Bracket.132</title>
+			<path d="M0 281.3 A5.43323 5.43323 0 0 1 4.8 276.5 L9.6 276.5 A5.43323 5.43323 -180 0 0 14.4 271.7 A5.43323 5.43323 -180
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+		</g>
+		<g id="shape278-62" transform="translate(252.5,-180)">
+			<title>Sheet.278</title>
+			<path d="M0 272.06 L0 272.42 L0 274.1 A7.19998 7.19998 -180 0 0 7.2 281.3 L28.8 281.3" class="st13"/>
+		</g>
+		<g id="shape279-70" transform="translate(284.9,-172.8)">
+			<title>Sheet.279</title>
+			<desc>CP/M System Area (128 KB)</desc>
+			<rect x="0" y="266.9" width="111.6" height="14.4" class="st7"/>
+			<text x="1" y="276.5" class="st4">CP/M System Area (128 KB)</text>		</g>
+		<g id="shape280-73" transform="translate(353.8,65.2999) rotate(90)">
+			<title>Sheet.280</title>
+			<path d="M0 112.82 L0 258.8 A22.5 22.5 -180 0 0 22.5 281.3 L44.88 281.3" class="st11"/>
+		</g>
+		<g id="shape281-78" transform="translate(368.2,65.2999) rotate(90)">
+			<title>Sheet.281</title>
+			<path d="M0 127.22 L0 258.8 A22.5 22.5 -180 0 0 22.5 281.3 L44.88 281.3" class="st11"/>
+		</g>
+		<g id="shape282-83" transform="translate(382.6,65.2999) rotate(90)">
+			<title>Sheet.282</title>
+			<path d="M0 141.62 L0 258.8 A22.5 22.5 -180 0 0 22.5 281.3 L44.88 281.3" class="st11"/>
+		</g>
+		<g id="shape283-88" transform="translate(469,65.2999) rotate(90)">
+			<title>Sheet.283</title>
+			<path d="M0 228.02 L0 258.8 A22.5 22.5 -180 0 0 22.5 281.3 L44.88 281.3" class="st11"/>
+		</g>
+		<g id="shape284-93" transform="translate(158.9,-68.3999)">
+			<title>Sheet.284</title>
+			<rect x="0" y="277.7" width="14.4" height="3.6" class="st3"/>
+		</g>
+		<g id="shape285-95" transform="translate(158.9,-64.7999)">
+			<title>Sheet.285</title>
+			<rect x="0" y="277.7" width="14.4" height="3.6" class="st3"/>
+		</g>
+		<g id="shape286-97" transform="translate(158.9,-61.1999)">
+			<title>Sheet.286</title>
+			<rect x="0" y="277.7" width="14.4" height="3.6" class="st3"/>
+		</g>
+		<g id="shape287-99" transform="translate(158.9,-57.5999)">
+			<title>Sheet.287</title>
+			<rect x="0" y="277.7" width="14.4" height="3.6" class="st3"/>
+		</g>
+		<g id="shape288-101" transform="translate(166.1,-57.6)">
+			<title>Stack pointer.179</title>
+			<path d="M33.6 302.9 L5.4 302.9 A5.39999 5.39999 0 0 1 0 297.5 L0 292.1 L0 286.82" class="st11"/>
+		</g>
+		<g id="shape289-106" transform="translate(50.9,-136.8)">
+			<title>Sheet.289</title>
+			<desc>RomWBW Data (8,320 KB * N)</desc>
+			<rect x="0" y="266.9" width="144" height="14.4" class="st1"/>
+			<text x="22.71" y="276.5" class="st4">RomWBW Data (8,320 KB * N)</text>		</g>
+		<g id="shape293-109" transform="translate(252.5,-46.8)">
+			<title>Dynamic connector.207</title>
+			<path d="M0 281.3 L17.1 281.3 A4.5 4.5 -180 0 0 21.6 276.8 L21.6 231.8 A4.5 4.5 -180 0 0 17.1 227.3 L-17.1 227.3 A4.5
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+		</g>
+		<g id="shape294-115" transform="translate(101.3,-57.6)">
+			<title>Sheet.294</title>
+			<desc>MBR</desc>
+			<rect x="0" y="266.9" width="72" height="14.4" class="st5"/>
+			<text x="28.23" y="276.5" class="st4">MBR</text>		</g>
+		<g id="shape295-118" transform="translate(209.156,-21.5999)">
+			<title>Sheet.295</title>
+			<rect x="0" y="252.5" width="43.344" height="28.8" class="st5"/>
+		</g>
+		<g id="shape296-120" transform="translate(245.3,-208.8)">
+			<title>Sheet.296</title>
+			<desc>Slice (8,320 KB)</desc>
+			<rect x="0" y="266.9" width="151.2" height="14.4" class="st5"/>
+			<text x="50.65" y="276.5" class="st4">Slice (8,320 KB)</text>		</g>
+		<g id="shape298-123" transform="translate(245.3,-194.4)">
+			<title>Sheet.298</title>
+			<rect x="0" y="266.9" width="14.4" height="14.4" class="st3"/>
+		</g>
+		<g id="shape299-125" transform="translate(245.3,-194.4)">
+			<title>Sheet.299</title>
+			<desc>CP/M File System (8 MB)</desc>
+			<rect x="0" y="266.9" width="151.2" height="14.4" class="st7"/>
+			<text x="35.37" y="276.5" class="st4">CP/M File System (8 MB)</text>		</g>
+		<g id="shape300-128" transform="translate(245.3,-194.4)">
+			<title>Sheet.300</title>
+			<rect x="0" y="266.9" width="151.2" height="14.4" class="st5"/>
+		</g>
+		<g id="shape301-130" transform="translate(-180,223.7) rotate(-90)">
+			<title>Bracket.301</title>
+			<path d="M-0 281.3 A2.41217 2.41217 0 0 1 2.13 279.17 L5.07 279.17 A2.41217 2.41217 -180 0 0 7.2 277.04 A2.41217 2.41217
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+		</g>
+		<g id="shape302-133" transform="translate(-35.9999,72.5) rotate(-90)">
+			<title>Bracket.302</title>
+			<path d="M-0 281.3 A2.41217 2.41217 0 0 1 2.13 279.17 L5.07 279.17 A2.41217 2.41217 -180 0 0 7.2 277.04 A2.41217 2.41217
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+		</g>
+	</g>
+</svg>
--- a/Source/Doc/RomWBW
+++ b/Source/Doc/RomWBW
--- a/Source/Doc/SystemGuide.md
+++ b/Source/Doc/SystemGuide.md
@@ -126,6 +126,7 @@ execution.

 ![Bank Switched Memory Layout](Graphics/BankSwitchedMemory){ width=100% }

+
 ## Bank Id

 RomWBW utilizes a specific assignment of memory banks for dedicated
@@ -262,6 +263,106 @@ Common Bank:
 It is a fixed mapping that is never changed in normal RomWBW operation
 hence the name "Common".

+# Disk Layout
+
+RomWBW supports two hard disk layouts: the Classic layout used by 
+RomWBW with 512 directory entries per slice and a Modern layout with 
+1024 directory entries per slice.  These layouts are referred to as
+hd512 and hd1k respectively.
+
+WARNING: You **can not** mix the two hard disk layouts on one hard 
+disk device.  You can use different layouts on different hard disk 
+devices in a single system though.
+
+RomWBW determines which of the hard disk layouts to use for a given 
+hard disk device based on whether there is a RomWBW hard disk 
+partition on the disk containing the slices.   If there is no RomWBW 
+partition, then RomWBW will assume the 512 directory entry format for 
+all slices and will assume the slices start at the first sector of 
+the hard disk.  If there is a RomWBW partition on the hard disk 
+device, then RomWBW will assume the 1024 directory entry format for 
+all slices and will assume the slices are located in the defined 
+partition.
+
+RomWBW supports up to 256 CP/M slices (0-255).  Under hd512, the slices
+begin at the start of the hard disk.  Under hd1k, the slices reside
+within partition type 0x2E.
+
+RomWBW accesses all hard disks using Logical Block Addressing (pure
+sector offset).  When necessary, RomWBW simulates the following disk
+geometry for operating systems:
+
+- Sector = 512 Bytes
+- Track = 16 Sectors (8KB per Track)
+- Cylinder = 16 Tracks (256 Sectors per Cylinder, 128KB per Cylinder)
+
+If one is used, the FAT Partition must not overlap the CP/M slices.
+The FAT partition does not need to start immediately after the CP/M
+slices nor does it need to extend to the end of the hard disk.  Its
+location and size are entirely determined by its corresponding
+partition table entry.
+
+Drive letters in CP/M are ASSIGNed to the numbered slices as desired.  
+At boot, RomWBW automatically assigns up to  8 slices to drive letters 
+starting with the first available drive letter (typically C:).
+
+Microsoft Windows will assign a single drive letter to the FAT partition
+when the CF/SD Card is inserted.  The drive letter assigned has no 
+relationship to the CP/M drive letters assigned to CP/M slices.
+
+In general, Windows, MacOS, or Linux know nothing about the CP/M slices 
+and CP/M knows nothing about the FAT partition.  However, the FAT 
+application can be run under CP/M to access the FAT partition 
+programmatically.
+
+A CP/M slice is (re)initialized using the CP/M command CLRDIR.  A CP/M 
+slice can be made bootable by copying system image to the System Area 
+using SYSCOPY.
+
+The FAT partition can be created from CP/M using the FDISK80 application.
+
+The FAT partition can be initialized using the FAT application from CP/M
+using the command `FAT FORMAT n:` where n is the RomWBW disk unit 
+number containing the FAT partition to be formatted.
+
+## Modern Disk Layout (hd1k)
+
+![Modern Disk Layout](Graphics/hd1k)
+
+The CP/M filesystem on a Modern disk will accommodate 1,024 directory 
+entries.
+
+The CP/M slices reside entirely within a hard disk partition of type
+0x2E.  The number of slices is determined by the number of slices that
+fit within the partition spaces allocated up to the maximum of 256.
+
+## Classic Disk Layout (hd512)
+
+![Classic Disk Layout](Graphics/hd512)
+
+The CP/M filesystem on a Classic disk will accommodate 512 directory 
+entries.
+
+The CP/M slices reside on the hard disk starting at the first sector
+of the hard disk.  The number of CP/M slices is not explicitly recorded
+anywhere on the hard disk.  It is up to the system user to know how
+many slices are being used based on the size of the hard disk media
+and/or the start of a FAT partition.
+
+A partition table may exist within the first sector of the first
+slice.  For Classic disks, the partition table defines only the
+location and size of the FAT partition.  The Partition Table does
+not control the location or number of CP/M slices in any way.
+
+The Partition Table resides in a sector that is shared with the System 
+Area of CP/M Slice 0.  However, the RomWBW implementation of CP/M takes 
+steps to avoid changing or corrupting the Partition Table area.
+
+The FAT partition can be created from CP/M using the FDISK80 
+application.  The user is responsible for ensuring that the start of the
+FAT partition does not overlap with the area they intend to use for 
+CP/M slices.  FDISK80 has a Reserve option to assist with this.
+
 # System Boot Process

 A multi-phase boot strategy is employed. This is necessary because at
@@ -746,12 +847,19 @@ more of the defined media types.
 | MID_FD111     | 9      | 8" 1.11M Floppy                            |
 | MID_HD1K      | 10     | Hard Disk (LBA) w/ 1024 directory entries  |

+**NOTE**: HBIOS does not actually differentiate between MID_HD512 and
+MID_HD1K.  The use of these two formats is determined by the use of a
+partition table on the media and is implemented by the operating
+system itself.  HBIOS treats all hard disks as raw sectors. See
+[Function 0x18 -- Disk Media (DIOMEDIA)] for more information on the
+Media ID byte returned.
+
 HBIOS supports both Cylinder/Head/Sector (CHS) and Logical Block 
 Addresses (CHS) when locating a sector for I/O (see DIOSEEK function). 
 For devices that are natively CHS (e.g., floppy disk), the HBIOS driver 
 can convert LBA values to CHS values according to the geometry of the 
 current media.  For devices that are natively LBA (e.g., hard disk), the
- HBIOS driver simulates CHS using a fictitious geometry provided by the 
+HBIOS driver simulates CHS using a fictitious geometry provided by the 
 driver (typically 16 sectors per track and 16 heads per cylinder).

 ### Function 0x10 -- Disk Status (DIOSTATUS)
@@ -964,6 +1072,12 @@ Report the Media ID (E) for the for media in the specified Disk Unit
 will be performed.  The Status (A) is a standard HBIOS result code. If 
 there is no media in device, function will return an error status.

+**NOTE**: This function will always return MID_HD512 for hard disk
+devices.  MID_HD1K is provided for use internally by operating systems
+that provide different filsystem formats depending on the partition
+table.  This function cannot be used to determine if an HD1K formatted
+partition exists on the hard disk.
+
 ### Function 0x19 -- Disk Define Media (DIODEFMED)

 | **Entry Parameters**                   | **Returned Values**                    |
@@ -997,7 +1111,7 @@ DIOMEDIA function to force this if desired.
 | **Entry Parameters**                   | **Returned Values**                    |
 |----------------------------------------|----------------------------------------|
 | B: 0x1B                                | A: Status                              |
-| C: Disk Unit                           | D: Heads                               |
+| C: Disk Unit                           | D: Heads / LBA                         |
 |                                        | E: Sectors                             |
 |                                        | HL: Cylinder Count                     |
 |                                        | BC: Block Size                         |
@@ -1007,7 +1121,11 @@ device uses LBA mode addressing natively, then the drivers simulated
 geometry will be returned. The Status (A) is a standard HBIOS result 
 code.  If the media is unknown, an error will be returned.

-Heads (D) refers to the number of heads per cylinder.  Sectors (E)
+LBA capability is indicated by D:7.  When set, the device is capable
+of LBA addressing.  Refer to [Function 0x12 -- Disk Seek (DIOSEEK)]
+for more information on specifying LBA vs. CHS addresses.
+
+Heads (D:6-0) refers to the number of heads per cylinder.  Sectors (E)
 refers to the number of sectors per track.  Cylinder Count (HL) is the
 total number of cylinders addressable for the media.  Block Size (BC)
 is the number of bytes in one sector.
@@ -2409,6 +2527,9 @@ a double-word binary value.  The frequency of the system timer in Hertz
 is returned in Frequency (C). The returned Status (A) is a standard HBIOS
 result code.

+The tick count is a 32 bit binary value.  It will rollover to zero
+if the maximum value for a 32 bit number is reached.
+
 Note that not all hardware configuration have a system timer.  You
 can determine if a timer exists by calling this function repeatedly
 to see if it is incrementing.
--- a/Source/Doc/UserGuide.md
+++ b/Source/Doc/UserGuide.md
@@ -222,46 +222,47 @@ by RomWBW along with the standard pre-built ROM image(s).  RomWBW does
 allow for the creation of ROM images with custom configurations.  This
 is discussed in [Customizing RomWBW].

-| **Description**                                                | **Bus** | **ROM Image File**    | **Baud Rate** |
-|----------------------------------------------------------------|---------|-----------------------|--------------:|
-| [RetroBrew Z80 SBC]^1^                                         | ECB     | SBC_std.rom           | 38400         |
-| [RetroBrew Z80 SimH]^1^                                        | -       | SBC_simh.rom          | 38400         |
-| [RetroBrew N8 Z180 SBC]^1^ (date code >= 2312)                 | ECB     | N8_std.rom            | 38400         |
-| [Zeta Z80 SBC]^2^, ParPortProp                                 | -       | ZETA_std.rom          | 38400         |
-| [Zeta V2 Z80 SBC]^2^, ParPortProp                              | -       | ZETA2_std.rom         | 38400         |
-| [Mark IV Z180 SBC]^3^                                          | ECB     | MK4_std.rom           | 38400         |
-| [RCBus Z80 CPU Module]^4^, 512K RAM/ROM                        | RCBus   | RCZ80_std.rom         | 115200        |
-| [RCBus Z80 CPU Module]^4^, 512K RAM/ROM, KIO                   | RCBus   | RCZ80_kio.rom         | 115200        |
-| [RCBus Z180 CPU Module]^4^ w/ external banking                 | RCBus   | RCZ180_ext.rom        | 115200        |
-| [RCBus Z180 CPU Module]^4^ w/ native banking                   | RCBus   | RCZ180_nat.rom        | 115200        |
-| [RCBus Z280 CPU Module]^4^ w/ external banking                 | RCBus   | RCZ180_ext.rom        | 115200        |
-| [RCBus Z280 CPU Module]^4^ w/ native banking                   | RCBus   | RCZ180_nat.rom        | 115200        |
-| [Easy Z80 SBC]^2^                                              | RCBus   | RCZ80_easy.rom        | 115200        |
-| [Tiny Z80 SBC]^2^                                              | RCBus   | RCZ80_tiny.rom        | 115200        |
-| [Z80-512K CPU/RAM/ROM Module]^2^                               | RCBus   | RCZ80_skz.rom         | 115200        |
-| [Small Computer SC126 Z180 SBC]^5^                             | BP80    | SCZ180_sc126.rom      | 115200        |
-| [Small Computer SC130 Z180 SBC]^5^                             | RCBus   | SCZ180_sc130.rom      | 115200        |
-| [Small Computer SC131 Z180 Pocket Computer]^5^                 | -       | SCZ180_sc131.rom      | 115200        |
-| [Small Computer SC140 Z180 CPU Module]^5^                      | Z50     | SCZ180_sc140.rom      | 115200        |
-| [Small Computer SC503 Z180 CPU Module]^5^                      | Z50     | SCZ180_sc503.rom      | 115200        |
-| [Small Computer SC700 Z180 CPU Module]^5^                      | RCBus   | SCZ180_sc700.rom      | 115200        |
-| [Dyno Z180 SBC]^6^                                             | Dyno    | DYNO_std.rom          | 38400         |
-| [Nhyodyne Z80 MBC]^1^                                          | MBC     | MBC_std.rom           | 38400         |
-| [Rhyophyre Z180 SBC]^1^                                        | -       | RPH_std.rom           | 38400         |
-| [Z80 ZRC CPU Module]^7^                                        | RCBus   | RCZ80_zrc.rom         | 115200        |
-| [Z80 ZRC CPU Module]^7^ ROMless                                | RCBus   | RCZ80_zrc_ram.rom     | 115200        |
-| [Z80 ZRC512 CPU Module]^7^                                     | RCBus   | RCZ80_zrc512.rom      | 115200        |
-| [Z180 Z1RCC CPU Module]^7^                                     | RCBus   | RCZ180_z1rcc.rom      | 115200        |
-| [Z280 ZZRCC CPU Module]^7^                                     | RCBus   | RCZ280_zzrcc.rom      | 115200        |
-| [Z280 ZZRCC CPU Module]^7^ ROMless                             | RCBus   | RCZ280_zzrcc_ram.rom  | 115200        |
-| [Z280 ZZ80MB SBC]^7^                                           | RCBus   | RCZ280_zz80mb.rom     | 115200        |
-| [Z80-Retro SBC]^8^                                             | -       | Z80RETRO_std.rom      | 38400         |
-| [S100 Computers Z180]^9^                                       | S100    | S100_std.rom          | 57600         |
-| [Duodyne Z80 System]^1^                                        | Duo     | DUO_std.rom           | 38400         |
-| [Heath H8 Z80 System]^10^                                      | H8      | HEATH_std.rom         | 115200        |
-| [EP Mini-ITX Z180]^11^                                         | RCBus?  | EPITX_std.rom         | 115200        |
-| [NABU w/ RomWBW Option Board]^10^                              | NABU    | NABU_std.rom          | 115200        |
-| [S100 FPGA Z80]^9^                                             | S100    | FZ80_std.rom          | 9600          |
+| **Description**                                             | **Bus** | **ROM Image File**           | **Baud Rate** |
+|-------------------------------------------------------------|---------|------------------------------|--------------:|
+| [RetroBrew Z80 SBC]^1^                                      | ECB     | SBC_std.rom                  | 38400         |
+| [RetroBrew Z80 SimH]^1^                                     | -       | SBC_simh.rom                 | 38400         |
+| [RetroBrew N8 Z180 SBC]^1^ (date >= 2312)                   | ECB     | N8_std.rom                   | 38400         |
+| [Zeta Z80 SBC]^2^, ParPortProp                              | -       | ZETA_std.rom                 | 38400         |
+| [Zeta V2 Z80 SBC]^2^, ParPortProp                           | -       | ZETA2_std.rom                | 38400         |
+| [Mark IV Z180 SBC]^3^                                       | ECB     | MK4_std.rom                  | 38400         |
+| [RCBus Z80 CPU Module]^4^, 512K RAM/ROM                     | RCBus   | RCZ80_std.rom                | 115200        |
+| [RCBus Z80 CPU Module]^4^, 512K w/KIO                       | RCBus   | RCZ80_kio_std.rom            | 115200        |
+| [RCBus Z180 CPU Module]^4^ w/ ext banking                   | RCBus   | RCZ180_ext_std.rom           | 115200        |
+| [RCBus Z180 CPU Module]^4^ w/ native banking                | RCBus   | RCZ180_nat_std.rom           | 115200        |
+| [RCBus Z280 CPU Module]^4^ w/ ext banking                   | RCBus   | RCZ180_ext_std.rom           | 115200        |
+| [RCBus Z280 CPU Module]^4^ w/ native banking                | RCBus   | RCZ180_nat_std.rom           | 115200        |
+| [Easy Z80 SBC]^2^                                           | RCBus   | RCZ80_easy_std.rom           | 115200        |
+| [Tiny Z80 SBC]^2^                                           | RCBus   | RCZ80_tiny_std.rom           | 115200        |
+| [Z80-512K CPU/RAM/ROM Module]^2^                            | RCBus   | RCZ80_skz_std.rom            | 115200        |
+| [Small Computer SC126 Z180 SBC]^5^                          | BP80    | SCZ180_sc126_std.rom         | 115200        |
+| [Small Computer SC130 Z180 SBC]^5^                          | RCBus   | SCZ180_sc130_std.rom         | 115200        |
+| [Small Computer SC131 Z180 Pocket Comp]^5^                  | -       | SCZ180_sc131_std.rom         | 115200        |
+| [Small Computer SC140 Z180 CPU Module]^5^                   | Z50     | SCZ180_sc140_std.rom         | 115200        |
+| [Small Computer SC503 Z180 CPU Module]^5^                   | Z50     | SCZ180_sc503_std.rom         | 115200        |
+| [Small Computer SC700 Z180 CPU Module]^5^                   | RCBus   | SCZ180_sc700_std.rom         | 115200        |
+| [Dyno Z180 SBC]^6^                                          | Dyno    | DYNO_std.rom                 | 38400         |
+| [Nhyodyne Z80 MBC]^1^                                       | MBC     | MBC_std.rom                  | 38400         |
+| [Rhyophyre Z180 SBC]^1^                                     | -       | RPH_std.rom                  | 38400         |
+| [Z80 ZRC CPU Module]^7^                                     | RCBus   | RCZ80_zrc_std.rom            | 115200        |
+| [Z80 ZRC CPU Module]^7^ ROMless                             | RCBus   | RCZ80_zrc_ram_std.rom        | 115200        |
+| [Z80 ZRC512 CPU Module]^7^                                  | RCBus   | RCZ80_zrc512_std.rom         | 115200        |
+| [Z180 Z1RCC CPU Module]^7^                                  | RCBus   | RCZ180_z1rcc_std.rom         | 115200        |
+| [Z280 ZZRCC CPU Module]^7^                                  | RCBus   | RCZ280_zzrcc_std.rom         | 115200        |
+| [Z280 ZZRCC CPU Module]^7^ ROMless                          | RCBus   | RCZ280_zzrcc_ram_std.rom     | 115200        |
+| [Z280 ZZ80MB SBC]^7^                                        | RCBus   | RCZ280_zz80mb_std.rom        | 115200        |
+| [Z80-Retro SBC]^8^                                          | -       | Z80RETRO_std.rom             | 38400         |
+| [S100 Computers Z180]^9^                                    | S100    | S100_std.rom                 | 57600         |
+| [Duodyne Z80 System]^1^                                     | Duo     | DUO_std.rom                  | 38400         |
+| [Heath H8 Z80 System]^10^                                   | H8      | HEATH_std.rom                | 115200        |
+| [EP Mini-ITX Z180]^11^                                      | RCBus?  | EPITX_std.rom                | 115200        |
+| [NABU w/ RomWBW Option Board]^10^                           | NABU    | NABU_std.rom                 | 115200        |
+| [S100 FPGA Z80]^9^                                          | S100    | FZ80_std.rom                 | 9600          |
+| [Genesis STD Z180]^12^                                      | STD     | GMZ180_std.rom               | 115200        |

 | ^1^Designed by Andrew Lynch
 | ^2^Designed by Sergey Kiselev
@@ -274,6 +275,7 @@ is discussed in [Customizing RomWBW].
 | ^9^Designed by John Monahan
 | ^10^Designed by Les Bird
 | ^11^Designed by Alan Cox
+| ^12^Designed by Doug Jackson

 RCBus refers to Spencer Owen's RC2014 bus specification and derivatives
 including RC26, RC40, RC80, and BP80.
@@ -783,23 +785,62 @@ the [Disk Images] section of this document.

 ### Auto-Submit Batch Files

-All of the operating systems supplied with RomWBW have the ability to
-execute a "batch" of commands by creating a batch submission file
-containing the commands to be executed.  The specifics of using
-batch files in a specific operating system is covered in its specific
-documentation.
+All of the operating systems supplied with RomWBW have the ability to 
+execute a "batch" of commands by creating a batch submission file 
+containing the commands to be executed. The mechanism for running 
+commands automatically at startup varies by operating system.  In some 
+cases, it was built into the original operating system.  In other cases,
+I have added this capability in the RomWBW BIOS of the operating 
+system.

-At boot, the operating system will look for a specific batch file 
-(`PROFILE.SUB` for CP/M 2.2 and 3) on the boot drive and execute that 
-batch file automatically.  This allows you to automatically customize 
-your operating system with any commands desired at boot.  CP/M 2.2 did 
-not originally have the ability to automatically excute a batch file at 
-boot, but the CBIOS in RomWBW has added this capability.
+In all cases, the file containing the commands to run at startup must
+be on the boot drive (A:).  RomWBW automatically assigns A: to the
+disk slice you choose to boot.  Adding a startup command file to the
+ROM Disk is not recommended because it would require customizing and
+building a new ROM.  Use of bootable disk slices is preferred since
+the startup command files can be added/edited without any special
+system customization.
+
+Here is an overview for each operating system:
+
+- **CP/M 2.2** - Will run PROFILE.SUB as a SUBMIT file if it exists in
+  A: at startup.  Note that original CP/M 2.2 itself did not have this
+  ability -- it was added to the RomWBW CP/M 2.2 BIOS.  The use of SUBMIT
+  files is documented in Section 1.6.7 SUBMIT Command of the CPM Manual 
+  included in the Doc/CPM folder of the RomWBW distribution.
+
+- **Z-System (ZSDOS 1.1)** - Will run run PROFILE.SUB as a SUBMIT file 
+  if it exists in A: at startup.  Works exactly the same as CP/M 2.2.
+  The original Z-System ZSDOS 1.1 did not have this ability -- it was
+  added to the RomWBW Z-System BIOS.  The Z-System documentation does
+  not cover the use of SUBMIT files -- please refer to the CP/M 2.2
+  documentation.
+
+- **NZCOM** - Will run the command STARTZCM at startup.  This is 
+  normally an alias file.  You use SALIAS to edit such files.  Please see 
+  Section 3.1 Creating an Alias of the NZCOM Users Manual included in the 
+  Doc/CPM folder of the RomWBW distribution.  Note that the NZCOM 
+  distribution includes a PROFILE.SUB file.  NZCOM itself is launched from 
+  ZSDOS.  The included PROFILE.SUB accomplishes this.  Do not modify this 
+  file unless you fully understand the NZCOM boot process.
+
+- **CP/M 3** - Will run PROFILE.SUB as a SUBMIT file if it exists in A: 
+  at startup.  This mechanism is built into the CP/M 3 operating system.  
+  Please see Section 4.5 Executing Multiple Commands and Section 5.2.74 
+  Executing the SUBMIT Command of the CPM3 Users Guide included in the 
+  Doc/CPM folder of the RomWBW distribution.
+
+- **ZPM3** - Will run the command STARTZPM at startup.  This is normally
+  an alias file.  You use SALIAS to edit such files.  ZPM3 has no real 
+  documentation.  The NZCOM documentation of STARTZCM is generally correct
+  for ZPM3.

 Since RomWBW can utilize many disk slices, it is very easy to create 
 slices for specific workflows (editing, software development, games, 
 etc.). You can then just boot to the slice that is optimized for the 
-task you want to perform.
+task you want to perform.  Each such slice may have its own startup
+command batch file that customizes the environment for the specific
+workflow desired.

 ## System Management

@@ -1946,13 +1987,38 @@ new combo disk image.

 #### Custom Hard Disk Image

-If you want to use specific slices in a specific order, you can easily
-generate a custom hard disk image file.
-
 For hard disks, each .img file represents a single slice (CP/M 
 filesystem).  Since a hard disk can contain many slices, you can just 
 concatenate the slices (.img files) together to create your desired hard
-disk image.  For example, if you want to create a hard disk image that 
+disk image.  
+
+If you look in the Binary directory of the distribution, you will see
+that there are more disk (slice) images than the 6 that are included
+in the "combo" disk images.  These images are identified by looking
+for the files that start with hd1k_ or hd512_.
+
+You can add slices to the combo disk images simply by tacking
+slices onto the end.  For example, if you want to add a slice
+containing the MSX ROMs to the end of the combo image, you could
+use one of the following command lines depending on your operating
+system:
+
+Windows:
+
+`COPY /B hd1k_combo.img + hd1k_msxroms.img my_hd.img` 
+
+Linus/MaxOS:
+
+`cat hd1k_combo.img hd1k_msxroms.img >my_hd.img`
+
+Note that you **must** be sure to use either the hd1k_ or hd512_
+prefixed files together.  You cannot mix them.
+
+If you want to create a completely custom hard disk image that is not
+based on the existing combo image, you can generate a disk image entirely
+from scratch using whatever slices you want in whatever order you like.
+
+For example, if you want to create a hard disk image that 
 has slices for CP/M 2.2, CP/M 3, and WordStar in the hd512 format, you 
 would use the command line of your modern computer to create the final 
 image:
@@ -2314,28 +2380,12 @@ call "ZSYS.SYS".  For example:
  or MAP, you may need to run “RELOG” to get the drive properly 
  recognized by ZSDOS.

-* RomWBW fully supports both DateStamper and P2DOS file date/time
-  stamping.  You must load the desired stamping module (`LDDS` for
-  DateStamper or `LDP2D` for P2DOS).  This could be automated using
-  a `PROFILE.SUB` file.  Follow the ZSDOS documentation to initialize
-  a disk for stamping.
-
 * ZSVSTAMP expects to be running under the ZCPR 3.X command processor. 
  By default, RomWBW uses ZCPR 1.0 (intentionally, to reduce space usage) 
  and ZSVSTAMP will just abort in this case. It will work fine if you 
  implement NZCOM. ZSVSTAMP is included solely to facilitate usage 
  if/when you install NZCOM.

-* FILEDATE only works with DateStamper style date stamping. If you run 
-  it on a drive that is not initialized for DateStamper, it will complain 
-  `FILEDATE, !!!TIME&.DAT missing`. This is normal and just means that 
-  you have not initialized that drive for DateStamper (using PUTDS).
-
-* ZXD will handle either DateStamper or P2DOS type date stamping. 
-  However, it **must** be configured appropriately. As distributed, it will 
-  look for P2DOS date stamps. Use ZCNFG to reconfigure it for P2DOS if 
-  that is what you are using.
-
 * Many of the tools can be configured (using either ZCNFG or DSCONFIG). 
  The configuration process modifies the actual application file itself. 
  This will fail if you try to modify one that is on the ROM disk because 
@@ -2346,10 +2396,6 @@ call "ZSYS.SYS".  For example:
  SETTERM. So, run SETTERM on DSCONFIG before using DSCONFIG to configure 
  DATSWEEP!

-* After using PUTDS to initialize a directory for ZDS date stamping, I 
-  am finding that it is necessary to run RELOG before the stamping 
-  routines will actually start working.
-
 * Generic CP/M PIP and ZSDOS path searching do not mix well if you use 
  PIP to copy to or from a directory in the ZSDOS search path. Best to 
  use COPY from the ZSDOS distribution.
@@ -3048,8 +3094,11 @@ SAMPLE2.TXT ==> 4:/SAMPLE2.TXT ... [OK]
 RomWBW supports a variety of real time clock hardware.  If your
 system has this hardware, then it will be able to maintain the
 current date and time even while your system is turned off.
+
 Additionally, depending on the operating system being used, you may be
 able to utilize date/time stamping of files.
+To facilitate this a CP/M clock driver (WBWCLK) has been included 
+inside `CLOCKS.DAT` that will read the clock via a RomWBW HBIOS call

 You can determine if your system has a real time clock present (and
 functioning) by looking at the boot messages.  Here is an example of
@@ -3075,6 +3124,8 @@ RomwWBW includes two utilities for displaying or setting the date/time
 stored by the RTC.  They are both a bit different and are briefly
 described below.

+A third utility `TESTCLOK` is also included as part of ZSDOS
+
 ### WDATE Utility

 The `WDATE` utility (contributed by Kevin Boone) is an application
@@ -3154,6 +3205,57 @@ Do **not** enable charging unless you are sure that your system
 supports this.  If your RTC is being powered by a normal battery, it
 would be dangerous to enable charging.

+### TESTCLOK Utility
+
+The `TESTCLOK` utility is used to test a selected CPM clock driver 
+loaded from the CLOCKS.DAT file. After selecting the location of CLOCKS.DAT 
+and the clock driver (45. WBWCLK) it displays the currently configured time 
+until a key is pressed. 
+
+```
+A>testclok
+
+TESTCLOK V1.0    Copyright (C) 1988    H.F. Bower / C.W. Cotrill
+
+Extract Clock from Library ([Y]/N) : Y
+Location of CLOCKS.DAT [A0:] : <RETURN> 
+
+  1. ACTRIX             2. ALSPA              3. AMPRO-LB         
+  4. ANLYTCL-PRD        5. AP2-CDZ180         6. AP2-THND/MT      
+  7. AP2-TIMASTR        8. AP2E+PCP-TM        9. AP2E+PCPI        
+ 10. AP2E-THUNDR       11. AP2E-TMASTR       12. BIG-BD-II        
+ 13. BP-BIOS           14. CCS-WALLCLK       15. CPUPRO-SSB1      
+ 16. ELECTR-MFIO       17. EPSON-QX10        18. ETS180IO+        
+ 19. H19-SUPER19       20. H19-ULTRA         21. H19-WATZMAN      
+ 22. H89-BITZERO       23. H89-PC12          24. H89-WIDGET       
+ 25. H89-WISE          26. H89UTI            27. HEATH-BIOS       
+ 28. HOUSEMASTER       29. K83-HOLMES        30. KAYPRO-84        
+ 31. KENMOR-ZTIM       32. KPRO-ADVENT       33. KPRO-LEGACY      
+ 34. MD3-MACK          35. MTN100K-DAY       36. ONEAC-ON!        
+ 37. OTRANA-ATCH       38. P&T-HEARTBT       39. QTSYS-S100       
+ 40. RELATIVE          41. S100-5832         42. SB180-HRTBT      
+ 43. SB180-XBIOS       44. SIMHCLOK          45. WBWCLK           
+ 46. XEROX-820         47. ZSDOS-BIOS       
+
+Enter Clock Driver Selection : 45
+
+..Loading : WBWCLK      ... 
+Linking Clock Module... OK
+RomWBW HBIOS Clock      1.1
+
+RomWBW Series HBIOS Clock
+
+Press any key to quit...
+
+ 19 Oct 2023  14:24:34
+```
+
+Since this runs at the CPM driver level it is useful as an end-to-end test
+to prove that date time stamping is able to read the correct time
+
+The `TESTCLOK` utility is provided by ZSDOS, plese see the ZSDOS Manual 
+for further information
+
 ## Date/Time File Stamping

 If an RTC is available in your system, then most operating systems
@@ -3162,10 +3264,16 @@ date/time of file creation, update, and or access in the directory.
 This capability is available in all of the RomWBW operating system
 except the original DRI CP/M 2.2.

-In some cases (such as ZSDOS), you must load an RSX (memory resident
-utility) to enable date/time stamping of files.  Additionally, you
-will need to initialize the directory.  The procedure varies in each
-operation system, so you must review the associated documentation.
+Three types of date/time stamping are supported using realtime clock 
+supported by RomWBW HBIOS. DateStamper, NZT and P2DOS.
+
+In some cases (such as ZSDOS), you must load an RSX (memory resident 
+utility) to enable date/time stamping of files. This could be automated 
+using a `PROFILE.SUB` file.
+Preconfigured loaders are provided, bypassing the need to use SETUPZST.
+
+Additionally, you will need to initialize the directory. The procedure varies
+depending on the date/time stamping mechanism, so you must review the associated documentation.

 The date/time stamping mechanisms for each operating system are
 generally not compatible.  If you initialize a directory for a type
@@ -3176,6 +3284,71 @@ mechanism.  Doing so may corrupt the directory.
 The RomWBW disk images do not have date/time stamping initialized.  This
 is to avoid any chance of directory corruption.

+### DateStamper
+
+DateStamper datestamping follows the standard set by Plu*Perfect Systems. 
+This method stores stamps in a disk file named `!!!TIME&.DAT`. 
+Only DateStamper stamping stores full time and date stamps for
+file Creation, Last Modification, and Last Access, 
+and may be used with any CP/M diskette format. In addition, 
+the DateStamper protocol is supported by a mature set of compatible utilities.
+
+Key Utilities
+
+* LDDS.COM - Load DateStamper date/time stamping resident extension. (RomWBW Provided)
+* PUTDS.COM - Prepare disk for DateStamper date/time stamping.
+
+After using PUTDS to initialize a directory for ZDS date stamping,
+it may be necessary to run RELOG before the stamping routines 
+will actually start working.
+
+### P2DOS (CP/M Plus compatible)
+
+CP/M Plus-type datestamping is also widely used due to the popularity 
+of CP/M Plus (also know as CP/M 3). CP/M Plus-type file datestamping uses 
+directory sectors to store file datestamps which may be accessed more quickly 
+by programs, but there is no Last File Access stamp. Finally, the range of 
+utilities for this type of stamps is more limited than for the DateStamper protocol.
+
+Key Utilities
+
+* LDP2D.COM - Load P2DOS date/time stamping resident extension. (RomWBW Provided)
+* INITDIR.COM - Prepares disks for P2DOS-type file stamping.
+
+### NZT
+
+_The use of NZT needs to be further documented_
+
+Key Utilities
+
+* LDNZT.COM - Load NZT date/time stamping resident extension. (RomWBW Provided)
+
+### Additional Notes
+
+The following files have been provided, customised and tested for for use in RomWBW
+
+* `CLOCKS.DAT` - Library of clock drivers, which has been updated to include 
+   the RomWBW clock driver WBWCLK, and also includes the SIMHCLOK clock driver.
+   The file is just a standard LU type library and is easily updated using NULU. 
+   The members are the relocatable binaries, but with the .REL extension removed.
+* `STAMPS.DAT` - Library of available date/time stamping modules for SETUPZST.
+   The file has been replaced with an updated version from the Walnut Creek CP/M CDROM. 
+   The original version has a bug that prevents RSX (resident system extension) mode 
+   to load properly.
+
+Additional Notes
+
+* `SETUPZST` (provided by ZSDOS) Should not normally be needed since the 
+   creation of the appropriate LDTIM loaders has already been performed.
+* `FILEDATE` only works with DateStamper style date stamping. If you run
+   it on a drive that is not initialized for DateStamper, it will complain
+   `FILEDATE, !!!TIME&.DAT missing`. This is normal and just means that
+   you have not initialized that drive for DateStamper (using PUTDS).
+* `ZXD` will handle either DateStamper or P2DOS type date stamping.
+   However, it **must** be configured appropriately. As distributed, it will
+   look for P2DOS date stamps. Use ZCNFG to reconfigure it for P2DOS if
+   that is what you are using.
+
 ## Timezone

 None of the operating systems distributed with RomWBW have any concept
@@ -4609,7 +4782,7 @@ the RomWBW HBIOS configuration.

 `\clearpage`{=latex}

-#### ROM Image File:  RCZ80_kio.rom
+#### ROM Image File:  RCZ80_kio_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -4652,7 +4825,7 @@ the RomWBW HBIOS configuration.

 ### RCBus Z180 CPU Module

-#### ROM Image File:  RCZ180_ext.rom
+#### ROM Image File:  RCZ180_ext_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -4697,7 +4870,7 @@ the RomWBW HBIOS configuration.

 `\clearpage`{=latex}

-#### ROM Image File:  RCZ180_nat.rom
+#### ROM Image File:  RCZ180_nat_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -4744,7 +4917,7 @@ the RomWBW HBIOS configuration.

 ### RCBus Z280 CPU Module

-#### ROM Image File:  RCZ280_ext.rom
+#### ROM Image File:  RCZ280_ext_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -4787,7 +4960,7 @@ the RomWBW HBIOS configuration.

 `\clearpage`{=latex}

-#### ROM Image File:  RCZ280_nat.rom
+#### ROM Image File:  RCZ280_nat_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -4831,7 +5004,7 @@ the RomWBW HBIOS configuration.

 ### Easy Z80 SBC

-#### ROM Image File:  RCZ80_easy.rom
+#### ROM Image File:  RCZ80_easy_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -4876,7 +5049,7 @@ the RomWBW HBIOS configuration.

 ### Tiny Z80 SBC

-#### ROM Image File:  RCZ80_tiny.rom
+#### ROM Image File:  RCZ80_tiny_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -4920,7 +5093,7 @@ the RomWBW HBIOS configuration.

 ### Z80-512K CPU/RAM/ROM Module

-#### ROM Image File:  RCZ80_skz.rom
+#### ROM Image File:  RCZ80_skz_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -4965,7 +5138,7 @@ the RomWBW HBIOS configuration.

 ### Small Computer SC126 Z180 SBC

-#### ROM Image File:  SCZ180_sc126.rom
+#### ROM Image File:  SCZ180_sc126_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -5013,7 +5186,7 @@ the RomWBW HBIOS configuration.

 ### Small Computer SC130 Z180 SBC

-#### ROM Image File:  SCZ180_sc130.rom
+#### ROM Image File:  SCZ180_sc130_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -5059,9 +5232,9 @@ the RomWBW HBIOS configuration.

 `\clearpage`{=latex}

-### Small Computer SC131 Z180 Pocket Computer
+### Small Computer SC131 Z180 Pocket Comp

-#### ROM Image File:  SCZ180_sc131.rom
+#### ROM Image File:  SCZ180_sc131_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -5088,7 +5261,7 @@ the RomWBW HBIOS configuration.

 ### Small Computer SC140 Z180 CPU Module

-#### ROM Image File:  SCZ180_sc140.rom
+#### ROM Image File:  SCZ180_sc140_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -5135,7 +5308,7 @@ the RomWBW HBIOS configuration.

 ### Small Computer SC503 Z180 CPU Module

-#### ROM Image File:  SCZ180_sc503.rom
+#### ROM Image File:  SCZ180_sc503_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -5182,7 +5355,7 @@ the RomWBW HBIOS configuration.

 ### Small Computer SC700 Z180 CPU Module

-#### ROM Image File:  SCZ180_sc700.rom
+#### ROM Image File:  SCZ180_sc700_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -5211,7 +5384,7 @@ the RomWBW HBIOS configuration.
 - CH: IO=60
 - CHUSB: IO=62
 - CHUSB: IO=60
-S- MD: TYPE=RAM
+- MD: TYPE=RAM
 - MD: TYPE=ROM
 - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
 - FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD
@@ -5342,7 +5515,7 @@ S- MD: TYPE=RAM

 ### Z80 ZRC CPU Module

-#### ROM Image File:  RCZ80_zrc.rom
+#### ROM Image File:  RCZ80_zrc_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -5389,7 +5562,7 @@ S- MD: TYPE=RAM

 `\clearpage`{=latex}

-#### ROM Image File:  RCZ80_zrc_ram.rom
+#### ROM Image File:  RCZ80_zrc_ram_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -5436,7 +5609,7 @@ S- MD: TYPE=RAM

 ### Z80 ZRC512 CPU Module

-#### ROM Image File:  RCZ80_zrc512.rom
+#### ROM Image File:  RCZ80_zrc512_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -5483,7 +5656,7 @@ S- MD: TYPE=RAM

 ### Z180 Z1RCC CPU Module

-#### ROM Image File:  RCZ180_z1rcc.rom
+#### ROM Image File:  RCZ180_z1rcc_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -5529,7 +5702,7 @@ S- MD: TYPE=RAM

 ### Z280 ZZRCC CPU Module

-#### ROM Image File:  RCZ280_zzrcc.rom
+#### ROM Image File:  RCZ280_zzrcc_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -5575,7 +5748,7 @@ S- MD: TYPE=RAM

 `\clearpage`{=latex}

-#### ROM Image File:  RCZ280_zzrcc_ram.rom
+#### ROM Image File:  RCZ280_zzrcc_ram_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -5621,7 +5794,7 @@ S- MD: TYPE=RAM

 ### Z280 ZZ80MB SBC

-#### ROM Image File:  RCZ280_zz80mb.rom
+#### ROM Image File:  RCZ280_zz80mb_std.rom

 |                   |               |
 |-------------------|---------------|
@@ -5926,6 +6099,36 @@ SD: MODE=FZ80, IO=108, UNITS=2

 - Requires matching FPGA code

+### Genesis STD Z180
+
+#### ROM Image File:  GMZ180_std.rom
+
+|                   |               |
+|-------------------|---------------|
+| Default CPU Speed | 18.432 MHz    |
+| Interrupts        | Mode 2        |
+| System Timer      | Z180          |
+| Serial Default    | 115200 Baud   |
+| Memory Manager    | Z180          |
+| ROM Size          | 512 KB        |
+| RAM Size          | 512 KB        |
+
+##### Supported Hardware (see [Appendix B - Device Summary]):
+
+DSRTC: MODE=STD, IO=132
+INTRTC: ENABLED
+ASCI: IO=192, INTERRUPTS ENABLED
+ASCI: IO=193, INTERRUPTS ENABLED
+MD: TYPE=RAM
+MD: TYPE=ROM
+IDE: MODE=GIDE, IO=32, MASTER
+IDE: MODE=GIDE, IO=32, SLAVE
+SD: MODE=GM, IO=132, UNITS=1
+
+##### Notes:
+
+- CPU speed will be dynamically measured at startup if DSRTC is present
+
 ## Appendix B - Device Summary

 The table below briefly describes each of the possible devices that
@@ -5952,6 +6155,7 @@ may be discovered by RomWBW in your system.
 | EMM       | Disk     | Disk drive on Parallel Port emm interface (Zip Drive)  |
 | FD        | Disk     | 8272 or compatible Floppy Disk Controller              |
 | FP        | System   | Simple LED & Switch Front Panel                        |
+| FV        | Video    | S100 FPGA Z80 Onboard VGA/Keyboard                     |
 | GDC       | Video    | uPD7220 Video Display Controller                       |
 | HDSK      | Disk     | SIMH Simulator Hard Disk                               |
 | ICM       | DsKy     | ICM7218-based Display/Keypad on PPI                    |
@@ -5960,6 +6164,7 @@ may be discovered by RomWBW in your system.
 | INTRTC    | RTC      | Interrupt-based Real Time Clock                        |
 | KBD       | Keyboard | 8242 PS/2 Keyboard Controller                          |
 | KIO       | System   | Zilog Serial/ Parallel Counter/Timer                   |
+| LCD       | System   | Hitachi HD44780-based LCD Display                      |
 | LPT       | Char     | Parallel I/O Controller                                |
 | MD        | Disk     | ROM/RAM Disk                                           |
 | MSXKYB    | Keyboard | MSX Compliant Matrix Keyboard                          |
--- a/Source/FZ80/Build.cmd
+++ b/Source/FZ80/Build.cmd
@@ -5,17 +5,20 @@ set TOOLS=../../Tools

 set PATH=%TOOLS%\srecord;%PATH%

-if exist ..\..\Binary\FZ80_std.rom call :build_fz80
+for %%f in (..\..\Binary\FZ80_*.rom) do call :build %%~nf

 goto :eof

-:build_fz80
+:build
+echo.
+echo Creating %1 disk image...
+echo.

 srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
 srec_cat temp.dat -binary -exclude 0x1B8 0x200 fz80_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
-srec_cat temp.dat -binary -exclude 0x80000 0xE0000 ..\..\Binary\FZ80_std.rom -binary -offset 0x80000 -o temp.dat -binary
-move temp.dat ..\..\Binary\hd1k_fz80_prefix.dat
+srec_cat temp.dat -binary -exclude 0x80000 0xE0000 ..\..\Binary\%1.rom -binary -offset 0x80000 -o temp.dat -binary
+move temp.dat ..\..\Binary\%1_hd1k_prefix.dat

-copy /b ..\..\Binary\hd1k_fz80_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_fz80_combo.img || exit /b
+copy /b ..\..\Binary\%1_hd1k_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\%1_hd1k_combo.img || exit /b

 goto :eof
--- a/Source/FZ80/Makefile
+++ b/Source/FZ80/Makefile
@@ -1,24 +1,25 @@
-HD1KFZ80PREFIX = hd1k_fz80_prefix.dat
-HD1KFZ80COMBOIMG = hd1k_fz80_combo.img
-FZ80ROM = ../../Binary/FZ80_std.rom
-HD1KIMGS = ../../Binary/hd1k_cpm22.img ../../Binary/hd1k_zsdos.img ../../Binary/hd1k_nzcom.img \
-	../../Binary/hd1k_cpm3.img ../../Binary/hd1k_zpm3.img ../../Binary/hd1k_ws4.img
-
-OBJECTS := $(HD1KFZ80PREFIX) $(HD1KFZ80COMBOIMG)
-
 DEST=../../Binary

+HD1KIMGS = $(DEST)/hd1k_cpm22.img $(DEST)/hd1k_zsdos.img $(DEST)/hd1k_nzcom.img \
+	$(DEST)/hd1k_cpm3.img $(DEST)/hd1k_zpm3.img $(DEST)/hd1k_ws4.img
+
+ROMS := $(wildcard $(DEST)/FZ80_*.rom)
+ROMS := $(patsubst $(DEST)/%.rom,%,$(ROMS))
+
+OBJECTS := $(patsubst %,%_hd1k_prefix.dat,$(ROMS))
+OBJECTS += $(patsubst %,%_hd1k_combo.img,$(ROMS))
+
 TOOLS = ../../Tools

 include $(TOOLS)/Makefile.inc

 DIFFPATH = $(DIFFTO)/Binary

-$(HD1KFZ80PREFIX):
+%_hd1k_prefix.dat: $(DEST)/%.rom
 	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
 	srec_cat temp.dat -binary -exclude 0x1B8 0x200 fz80_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
-	srec_cat temp.dat -binary -exclude 0x80000 0xE0000 $(FZ80ROM) -binary -offset 0x80000 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x80000 0xE0000 $< -binary -offset 0x80000 -o temp.dat -binary
 	mv temp.dat $@

-$(HD1KFZ80COMBOIMG): $(HD1KFZ80PREFIX) $(HD1KIMGS)
+%_hd1k_combo.img: %_hd1k_prefix.dat  $(HD1KIMGS)
 	cat $^ > $@
--- a/Source/HBIOS/Bank
+++ b/Source/HBIOS/Bank
@@ -43,8 +43,8 @@ Standard RAM Bank Layout (512K)
 Bank ID         Usage
 -------         ------
 0x80            RomWBW HBIOS
-0x81-0x88       RAM Disk Data (3)
-0x89-0x8B	App Banks (8)
+0x81-0x88       RAM Disk Data (8)
+0x89-0x8B	App Banks (3)
 0x8C		CP/M 3 Buffers
 0x8D            CP/M 3 OS
 0x8E            User TPA
--- a/Source/HBIOS/Build.cmd
+++ b/Source/HBIOS/Build.cmd
@@ -211,31 +211,29 @@ call Build ZETA2 std || exit /b
 call Build N8 std || exit /b
 call Build MK4 std || exit /b
 call Build RCZ80 std || exit /b
-call Build RCZ80 kio || exit /b
-call Build RCZ80 easy || exit /b
-call Build RCZ80 tiny || exit /b
-call Build RCZ80 skz || exit /b
-:: call Build RCZ80 mt || exit /b
-:: call Build RCZ80 duart || exit /b
-call Build RCZ80 zrc || exit /b
-call Build RCZ80 zrc_ram || exit /b
-call Build RCZ80 zrc512 || exit /b
-call Build RCZ180 ext || exit /b
-call Build RCZ180 nat || exit /b
-call Build RCZ180 z1rcc || exit /b
-call Build RCZ280 ext || exit /b
-call Build RCZ280 nat || exit /b
-call Build RCZ280 zz80mb || exit /b
-call Build RCZ280 zzrcc || exit /b
-call Build RCZ280 zzrcc_ram || exit /b
-call Build SCZ180 sc126 || exit /b
-call Build SCZ180 sc130 || exit /b
-call Build SCZ180 sc131 || exit /b
-call Build SCZ180 sc140 || exit /b
-call Build SCZ180 sc503 || exit /b
-call Build SCZ180 sc700 || exit /b
+call Build RCZ80 kio_std || exit /b
+call Build RCZ80 easy_std || exit /b
+call Build RCZ80 tiny_std || exit /b
+call Build RCZ80 skz_std || exit /b
+call Build RCZ80 zrc_std || exit /b
+call Build RCZ80 zrc_ram_std || exit /b
+call Build RCZ80 zrc512_std || exit /b
+call Build RCZ180 ext_std || exit /b
+call Build RCZ180 nat_std || exit /b
+call Build RCZ180 z1rcc_std || exit /b
+call Build RCZ280 ext_std || exit /b
+call Build RCZ280 nat_std || exit /b
+call Build RCZ280 zz80mb_std || exit /b
+call Build RCZ280 zzrcc_std || exit /b
+call Build RCZ280 zzrcc_ram_std || exit /b
+call Build SCZ180 sc126_std || exit /b
+call Build SCZ180 sc130_std || exit /b
+call Build SCZ180 sc131_std || exit /b
+call Build SCZ180 sc140_std || exit /b
+call Build SCZ180 sc503_std || exit /b
+call Build SCZ180 sc700_std || exit /b
+call Build GMZ180 std || exit /b
 call Build DYNO std || exit /b
-call Build UNA std || exit /b
 call Build RPH std || exit /b
 call Build Z80RETRO std || exit /b
 call Build S100 std || exit /b
@@ -245,5 +243,6 @@ call Build EPITX std || exit /b
 :: call Build MON std || exit /b
 call Build NABU std || exit /b
 call Build FZ80 std || exit /b
+call Build UNA std || exit /b

 goto :eof
--- a/Source/HBIOS/Build.ps1
+++ b/Source/HBIOS/Build.ps1
@@ -28,7 +28,7 @@ $ErrorAction = 'Stop'
 #

 $PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON", "NABU", "FZ80"
-$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100", "EPITX"
+$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100", "EPITX", "GMZ180"
 $PlatformListZ280 = "RCZ280"

 #
--- a/Source/HBIOS/Build.sh
+++ b/Source/HBIOS/Build.sh
@@ -11,48 +11,47 @@ export CPUFAM

 if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	echo "!!!DISTRIBUTION BUILD!!!"
-	ROM_PLATFORM="DYNO"; ROM_CONFIG="std"; bash Build.sh
-	ROM_PLATFORM="MK4"; ROM_CONFIG="std"; bash Build.sh
-	ROM_PLATFORM="N8"; ROM_CONFIG="std"; bash Build.sh
-	ROM_PLATFORM="RCZ180"; ROM_CONFIG="ext"; bash Build.sh
-	ROM_PLATFORM="RCZ180"; ROM_CONFIG="nat"; bash Build.sh
-	ROM_PLATFORM="RCZ180"; ROM_CONFIG="z1rcc"; bash Build.sh
-	ROM_PLATFORM="RCZ280"; ROM_CONFIG="ext"; bash Build.sh
-	ROM_PLATFORM="RCZ280"; ROM_CONFIG="nat"; bash Build.sh
-	ROM_PLATFORM="RCZ280"; ROM_CONFIG="zz80mb"; bash Build.sh
-	ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrcc"; bash Build.sh
-	ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrcc_ram"; bash Build.sh
-#	ROM_PLATFORM="RCZ80"; ROM_CONFIG="mt"; bash Build.sh
-#	ROM_PLATFORM="RCZ80"; ROM_CONFIG="duart"; bash Build.sh
-	ROM_PLATFORM="RCZ80"; ROM_CONFIG="std"; bash Build.sh
-	ROM_PLATFORM="RCZ80"; ROM_CONFIG="kio"; bash Build.sh
-	ROM_PLATFORM="RCZ80"; ROM_CONFIG="easy"; bash Build.sh
-	ROM_PLATFORM="RCZ80"; ROM_CONFIG="tiny"; bash Build.sh
-	ROM_PLATFORM="RCZ80"; ROM_CONFIG="skz"; bash Build.sh
-	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc"; bash Build.sh
-	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_ram"; bash Build.sh
-	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc512"; bash Build.sh
-	ROM_PLATFORM="RPH"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="SBC"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="SBC"; ROM_CONFIG="simh"; bash Build.sh
 	ROM_PLATFORM="MBC"; ROM_CONFIG="std"; bash Build.sh
-	ROM_PLATFORM="DUO"; ROM_CONFIG="std"; bash Build.sh
-	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc126"; bash Build.sh
-	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc130"; bash Build.sh
-	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc131"; bash Build.sh
-	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc140"; bash Build.sh
-	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc503"; bash Build.sh
-	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc700"; bash Build.sh
-	ROM_PLATFORM="S100"; ROM_CONFIG="std"; bash Build.sh
-	ROM_PLATFORM="UNA"; ROM_CONFIG="std"; bash Build.sh
-	ROM_PLATFORM="Z80RETRO"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="ZETA"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="ZETA2"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="N8"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="MK4"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="RCZ80"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="RCZ80"; ROM_CONFIG="kio_std"; bash Build.sh
+	ROM_PLATFORM="RCZ80"; ROM_CONFIG="easy_std"; bash Build.sh
+	ROM_PLATFORM="RCZ80"; ROM_CONFIG="tiny_std"; bash Build.sh
+	ROM_PLATFORM="RCZ80"; ROM_CONFIG="skz_std"; bash Build.sh
+	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_std"; bash Build.sh
+	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_ram_std"; bash Build.sh
+	ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc512_std"; bash Build.sh
+	ROM_PLATFORM="RCZ180"; ROM_CONFIG="ext_std"; bash Build.sh
+	ROM_PLATFORM="RCZ180"; ROM_CONFIG="nat_std"; bash Build.sh
+	ROM_PLATFORM="RCZ180"; ROM_CONFIG="z1rcc_std"; bash Build.sh
+	ROM_PLATFORM="RCZ280"; ROM_CONFIG="ext_std"; bash Build.sh
+	ROM_PLATFORM="RCZ280"; ROM_CONFIG="nat_std"; bash Build.sh
+	ROM_PLATFORM="RCZ280"; ROM_CONFIG="zz80mb_std"; bash Build.sh
+	ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrcc_std"; bash Build.sh
+	ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrcc_ram_std"; bash Build.sh
+	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc126_std"; bash Build.sh
+	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc130_std"; bash Build.sh
+	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc131_std"; bash Build.sh
+	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc140_std"; bash Build.sh
+	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc503_std"; bash Build.sh
+	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc700_std"; bash Build.sh
+	ROM_PLATFORM="GMZ180"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="DYNO"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="RPH"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="Z80RETRO"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="S100"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="DUO"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="HEATH"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="EPITX"; ROM_CONFIG="std"; bash Build.sh
 #	ROM_PLATFORM="MON"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="NABU"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="FZ80"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="UNA"; ROM_CONFIG="std"; bash Build.sh
 	exit
 fi

--- a/Source/HBIOS/Config/GMZ180_std.asm
+++ b/Source/HBIOS/Config/GMZ180_std.asm
@@ -0,0 +1,72 @@
+;
+;==================================================================================================
+;   STD Z180 STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE PLATFORM_NAME "GM STD BUS Z180", " [", CONFIG, "]"
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_gmz180.asm"
+;
+CPUOSC	.SET	18432000	; CPU OSC FREQ IN MHZ
+CRTACT	.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+;
+LEDENABLE	.SET	FALSE		; ENABLE STATUS LED (SINGLE LED)
+LEDMODE	.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+;
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+;
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+;
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+TMSMODE	.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+;
+AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+;
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE	.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE	.SET	SDMODE_GM	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
--- a/Source/HBIOS/Config/HEATH_std.asm
+++ b/Source/HBIOS/Config/HEATH_std.asm
@@ -24,46 +24,5 @@
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;
-#include "cfg_rcz80.asm"
+#include "cfg_heath.asm"
 ;
-CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
-CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-;
-DSKYENABLE	.SET	TRUE		; ENABLES DSKY FUNCTIONALITY
-H8PENABLE	.SET	TRUE		; ENABLES HEATH H8 FRONT PANEL
-;
-FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
-FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
-;
-DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
-;
-UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-ACIAENABLE	.SET	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
-SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
-;
-LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-;
-TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
-MKYENABLE	.SET	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
-VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-VDAEMU_SERKBD	.SET	0		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-;
-AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
-AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC]
-SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-;
-FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
-;
-IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.SET	SDMODE_PIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
-SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
-IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
-;
-PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
--- a/Source/HBIOS/Config/MK4_std.asm
+++ b/Source/HBIOS/Config/MK4_std.asm
@@ -35,9 +35,6 @@ Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCAS		.SET	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.SET	TRUE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.SET	TRUE		; UART: AUTO-DETECT 4UART UART
 SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 ;
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
--- a/Source/HBIOS/Config/RCZ180_ext_std.asm
+++ b/Source/HBIOS/Config/RCZ180_ext_std.asm
--- a/Source/HBIOS/Config/RCZ180_nat_std.asm
+++ b/Source/HBIOS/Config/RCZ180_nat_std.asm
--- a/Source/HBIOS/Config/RCZ180_z1rcc_std.asm
+++ b/Source/HBIOS/Config/RCZ180_z1rcc_std.asm
--- a/Source/HBIOS/Config/RCZ280_ext_std.asm
+++ b/Source/HBIOS/Config/RCZ280_ext_std.asm
--- a/Source/HBIOS/Config/RCZ280_nat_std.asm
+++ b/Source/HBIOS/Config/RCZ280_nat_std.asm
--- a/Source/HBIOS/Config/RCZ280_zz80mb_std.asm
+++ b/Source/HBIOS/Config/RCZ280_zz80mb_std.asm
--- a/Source/HBIOS/Config/RCZ280_zzrcc_ram_std.asm
+++ b/Source/HBIOS/Config/RCZ280_zzrcc_ram_std.asm
--- a/Source/HBIOS/Config/RCZ280_zzrcc_std.asm
+++ b/Source/HBIOS/Config/RCZ280_zzrcc_std.asm
--- a/Source/HBIOS/Config/RCZ80_easy_std.asm
+++ b/Source/HBIOS/Config/RCZ80_easy_std.asm
--- a/Source/HBIOS/Config/RCZ80_kio_std.asm
+++ b/Source/HBIOS/Config/RCZ80_kio_std.asm
--- a/Source/HBIOS/Config/RCZ80_skz_std.asm
+++ b/Source/HBIOS/Config/RCZ80_skz_std.asm
--- a/Source/HBIOS/Config/RCZ80_tiny_std.asm
+++ b/Source/HBIOS/Config/RCZ80_tiny_std.asm
--- a/Source/HBIOS/Config/RCZ80_zrc512_std.asm
+++ b/Source/HBIOS/Config/RCZ80_zrc512_std.asm
--- a/Source/HBIOS/Config/RCZ80_zrc_ram_std.asm
+++ b/Source/HBIOS/Config/RCZ80_zrc_ram_std.asm
--- a/Source/HBIOS/Config/RCZ80_zrc_std.asm
+++ b/Source/HBIOS/Config/RCZ80_zrc_std.asm
--- a/Source/HBIOS/Config/SBC_simh.asm
+++ b/Source/HBIOS/Config/SBC_simh.asm
@@ -33,7 +33,15 @@ HTIMENABLE	.SET	TRUE		; ENABLE SIMH TIMER SUPPORT
 SIMRTCENABLE	.SET	TRUE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 ;
-UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTSBCFORCE	.SET	TRUE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+;
+SSERENABLE	.SET	TRUE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$6D		; SSER: STATUS PORT
+SSERDATA	.SET	$68		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00100000	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
 HDSKENABLE	.SET	TRUE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
--- a/Source/HBIOS/Config/SBC_std.asm
+++ b/Source/HBIOS/Config/SBC_std.asm
@@ -31,11 +31,6 @@ INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTSBC		.SET	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
-UARTCAS		.SET	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.SET	TRUE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.SET	TRUE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.SET	FALSE		; UART: AUTO-DETECT RC UART
 SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 ;
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
--- a/Source/HBIOS/Config/SCZ180_sc126_std.asm
+++ b/Source/HBIOS/Config/SCZ180_sc126_std.asm
--- a/Source/HBIOS/Config/SCZ180_sc130_std.asm
+++ b/Source/HBIOS/Config/SCZ180_sc130_std.asm
--- a/Source/HBIOS/Config/SCZ180_sc131_std.asm
+++ b/Source/HBIOS/Config/SCZ180_sc131_std.asm
--- a/Source/HBIOS/Config/SCZ180_sc140_std.asm
+++ b/Source/HBIOS/Config/SCZ180_sc140_std.asm
--- a/Source/HBIOS/Config/SCZ180_sc503_std.asm
+++ b/Source/HBIOS/Config/SCZ180_sc503_std.asm
--- a/Source/HBIOS/Config/SCZ180_sc700_std.asm
+++ b/Source/HBIOS/Config/SCZ180_sc700_std.asm
--- a/Source/HBIOS/Config/ZETA2_std.asm
+++ b/Source/HBIOS/Config/ZETA2_std.asm
@@ -30,9 +30,6 @@ CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
-UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTSBC		.SET	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
-;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.SET	FDMODE_ZETA2	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
--- a/Source/HBIOS/Config/ZETA_std.asm
+++ b/Source/HBIOS/Config/ZETA_std.asm
@@ -30,9 +30,6 @@ CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
-UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTSBC		.SET	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
-;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.SET	FDMODE_ZETA	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC]
 ;
--- a/Source/HBIOS/cfg_duo.asm
+++ b/Source/HBIOS/cfg_duo.asm
@@ -90,6 +90,9 @@ PKDENABLE	.EQU	TRUE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$88		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -137,18 +140,27 @@ SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	7372800		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
-UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	TRUE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	TRUE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$58		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$A8		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	SER_300_8N1	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$70		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$78		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -160,6 +172,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$60		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(7372800/4)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
@@ -186,6 +199,7 @@ VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@@ -92,6 +92,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -146,17 +149,27 @@ DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
 DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
 UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$FF		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -173,6 +186,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
@@ -203,6 +217,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/cfg_epitx.asm
+++ b/Source/HBIOS/cfg_epitx.asm
@@ -93,6 +93,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -148,17 +151,27 @@ DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
 DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	2		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$A0		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$A8		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -175,6 +188,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
@@ -205,6 +219,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/cfg_fz80.asm
+++ b/Source/HBIOS/cfg_fz80.asm
@@ -92,6 +92,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -146,17 +149,27 @@ DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
 DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
 UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$FF		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -178,6 +191,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
@@ -208,6 +222,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	TRUE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	TRUE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	FALSE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/cfg_gmz180.asm
+++ b/Source/HBIOS/cfg_gmz180.asm
@@ -0,0 +1,359 @@
+;
+;==================================================================================================
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR GENESIS MODULES STD BUS BASED Z180 VARIANTS 
+;==================================================================================================
+;
+; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
+; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
+; UNDER THIS DIRECTORY.
+;
+; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
+; FOR THE PLATFORM.
+;
+#DEFINE PLATFORM_NAME "GM STD BUS Z180", " [", CONFIG, "]"
+;
+#INCLUDE "hbios.inc"
+;
+PLATFORM	.EQU	PLT_GMZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+;
+CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
+INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+;
+Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
+Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
+;
+RTCIO		.EQU	$84		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
+FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.EQU	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+;
+DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
+LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.EQU	FALSE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+;
+BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+;
+DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.EQU	TRUE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+;
+DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
+SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
+SSERDATA	.EQU	$FF		; SSER: DATA PORT
+SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
+DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+;
+UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$80		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$88		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$A0		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$A8		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+;
+ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
+ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
+ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
+;
+Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+;
+SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.EQU	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.EQU	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+;
+MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+;
+IDEENABLE	.EQU	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.EQU	IDEMODE_GIDE	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE0BASE	.EQU	$20   		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.EQU	$20		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.EQU	$28		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+;
+PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_GM	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM]
+SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+;
+CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+;
+PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+;
+PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+;
+ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
+HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.EQU	$18		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+;
+PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+;
+IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+;
+SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+;
+PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+;
+UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+;
+AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+;
+SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
--- a/Source/HBIOS/cfg_heath.asm
+++ b/Source/HBIOS/cfg_heath.asm
@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z80
+;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR HEATHKIT Z80
 ;==================================================================================================
 ;
 ; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -11,7 +11,7 @@
 ; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
 ; FOR THE PLATFORM.
 ;
-#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]"
+#DEFINE PLATFORM_NAME "HEATHKIT", " [", CONFIG, "]"
 ;
 #INCLUDE "hbios.inc"
 ;
@@ -29,7 +29,7 @@ AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	7372800		; CPU OSC FREQ IN MHZ
+CPUOSC		.EQU	16384000	; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
@@ -72,7 +72,7 @@ WDOGIO		.EQU	$6E		; WATCHDOG REGISTER ADR
 FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
 FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
 FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPLED_DSKACT	.EQU	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
 FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
 FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
 FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
@@ -80,18 +80,21 @@ FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
 DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_SC	; LEDMODE_[STD|SC|RTC|NABU]
+LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
 DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+DSKYDSKACT	.EQU	FALSE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
 ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
 ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
 PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+H8PENABLE	.EQU	TRUE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -105,7 +108,7 @@ KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
 MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
 DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
@@ -146,23 +149,33 @@ DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
 DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$E8		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$E0		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$D8		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$D0		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
 Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT
 ACIACNT		.EQU	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
 ACIA0BASE	.EQU	$80		; ACIA 0: REGISTERS BASE ADR
@@ -174,10 +187,11 @@ ACIA1CLK	.EQU	CPUOSC		; ACIA 1: OSC FREQ IN HZ
 ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
 ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
 ;
-SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
@@ -202,12 +216,13 @@ CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMS80COLS	.EQU	TRUE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
@@ -215,7 +230,7 @@ MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
@@ -247,7 +262,7 @@ IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
 IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
 IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDEENABLE	.EQU	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
 PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
@@ -327,7 +342,7 @@ SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.EQU	AYMODE_MSX	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -121,6 +121,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -175,18 +178,27 @@ DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
 DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
 UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
-UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$FF		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -218,6 +230,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
@@ -254,6 +267,7 @@ VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/cfg_mbc.asm
+++ b/Source/HBIOS/cfg_mbc.asm
@@ -87,6 +87,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -134,18 +137,27 @@ SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	3		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
-UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	TRUE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$68		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$80		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	SER_300_8N1	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$88		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -157,6 +169,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
@@ -183,6 +196,7 @@ VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -92,6 +92,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -139,18 +142,27 @@ SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	6		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
-UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	TRUE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	TRUE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$18		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$80		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	SER_300_8N1	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$C0		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$C8		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$D0		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$D8		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -167,6 +179,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
@@ -193,6 +206,7 @@ VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/cfg_mon.asm
+++ b/Source/HBIOS/cfg_mon.asm
@@ -87,6 +87,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -141,17 +144,27 @@ DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
 DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
 UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$FF		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -173,6 +186,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
@@ -203,6 +217,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -94,6 +94,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	N8_PPI0		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -141,18 +144,27 @@ SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	5		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
-UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	TRUE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	TRUE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$80		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$C0		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$C8		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$D0		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$D8		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -169,6 +181,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
@@ -195,6 +208,7 @@ VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/cfg_nabu.asm
+++ b/Source/HBIOS/cfg_nabu.asm
@@ -92,6 +92,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -146,17 +149,27 @@ DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
 DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$48		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -178,6 +191,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
@@ -208,6 +222,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -98,6 +98,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	TRUE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$AA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -152,17 +155,27 @@ DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
 DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	TRUE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$80		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$88		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$A0		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$A8		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -179,6 +192,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
@@ -209,6 +223,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -92,6 +92,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	TRUE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -146,17 +149,27 @@ DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
 DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	TRUE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$80		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$88		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$A0		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$A8		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -183,6 +196,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
@@ -213,6 +227,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -92,6 +92,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	TRUE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -146,17 +149,27 @@ DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
 DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	TRUE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$80		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$88		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$A0		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$A8		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -178,6 +191,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
@@ -208,6 +222,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/cfg_rph.asm
+++ b/Source/HBIOS/cfg_rph.asm
@@ -92,6 +92,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	RPH_PPI0	; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -139,18 +142,27 @@ SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
-UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$FF		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -184,6 +196,7 @@ VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/cfg_s100.asm
+++ b/Source/HBIOS/cfg_s100.asm
@@ -92,6 +92,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -146,17 +149,27 @@ DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
 DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
 UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$FF		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -173,6 +186,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
@@ -203,6 +217,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -87,6 +87,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -134,18 +137,27 @@ SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	7		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
-UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	TRUE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	TRUE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	TRUE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	TRUE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$68		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$80		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	SER_300_8N1	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$18		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$C0		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$C8		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$D0		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$D8		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -157,6 +169,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
@@ -183,6 +196,7 @@ VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -92,6 +92,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	TRUE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$AA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -146,17 +149,27 @@ DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
 DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	TRUE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$80		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$88		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$A0		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$A8		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -173,6 +186,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
@@ -203,6 +217,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/cfg_z80retro.asm
+++ b/Source/HBIOS/cfg_z80retro.asm
@@ -90,6 +90,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -137,18 +140,27 @@ SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
-UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$FF		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -160,6 +172,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_Z80R	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC/2	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
@@ -190,6 +203,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@@ -79,6 +79,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -126,18 +129,27 @@ SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
-UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$68		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	SER_300_8N1	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -160,6 +172,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@@ -90,6 +90,9 @@ PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
 PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
 PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
 H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
 ;
 BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
 SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
@@ -137,18 +140,27 @@ SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
-UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
-UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$68		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	SER_300_8N1	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
@@ -171,6 +183,7 @@ VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
 MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
--- a/Source/HBIOS/esp.asm
+++ b/Source/HBIOS/esp.asm
@@ -364,7 +364,8 @@ ESPCON_INIT:
 	PUSH	IY			; COPY CONFIG ENTRY PTR
 	POP	DE			; ... TO DE
 	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
-	LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
+	;;;LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
+	CALL	CIO_SETCRT		; SET OURSELVES AS THE CRT DEVICE
 ;
 ; ANNOUNCE OURSLEVES
 ;
--- a/Source/HBIOS/fv.asm
+++ b/Source/HBIOS/fv.asm
@@ -0,0 +1,497 @@
+;======================================================================
+;	VIDEO DRIVER FOR FPGA VGA
+;	http://s100computers.com/My%20System%20Pages/FPGA%20Z80%20SBC/FPGA%20Z80%20SBC.htm
+;
+;	WRITTEN BY: WAYNE WARTHEN -- 9/2/2024
+;======================================================================
+;
+; FPGA VGA EXPOSES A FRAME BUFFER STARTING AT $E000.
+; PORT $08 CONTROLS ACCESS TO THE FRAME BUFFER.
+;   - WHEN $01, FRAME BUFFER APPEARS AT $E000 IN CPU ADDRESS SPACE
+;   - WHEN $00, FRAME BUFFER IS INACCESSIBLE BY CPU
+; PORT $C0: SET/GET CURSOR COL
+; PORT $C1: SET/GET CURSOR ROW
+; PORT $C2: CONTROLS VGA OUTPUT
+;  BIT 0: BLUE
+;  BIT 1: GREEN
+;  BIT 2: RED
+;  BIT 3: UNUSED?
+;  BIT 4: CURSOR MODE
+;  BIT 5: CURSOR BLINK
+;  BIT 6: CURSOR ENABLE
+;  BIT 7: VGA SIGNAL OUTPUT ENABLE
+; PORT $08: BUFFER SELECT, 1=SELECTED
+;
+; TODO:
+;
+;======================================================================
+; FPGA VGA DRIVER - CONSTANTS
+;======================================================================
+;
+FV_FBUF		.EQU	$E000		; ADDRESS OF FRAME BUFFER
+FV_BASE		.EQU	$C0		; BASE I/O ADDRESS
+FV_CCOL		.EQU	FV_BASE+0	; CUR COL PORT
+FV_CROW		.EQU	FV_BASE+1	; CUR ROW PORT
+FV_CTL		.EQU	FV_BASE+2	; VGA CONTROL PORT
+;
+FV_BUFCTL	.EQU	$08
+;
+FV_KBDDATA	.EQU	$03
+FV_KBDST	.EQU	$02
+;
+FV_ROWS	.EQU	40
+FV_COLS	.EQU	80
+;
+TERMENABLE	.SET	TRUE		; INCLUDE TERMINAL PSEUDODEVICE DRIVER
+;;;KBDENABLE	.SET	TRUE		; INCLUDE KBD KEYBOARD SUPPORT
+;
+		DEVECHO	"FV: IO="
+		DEVECHO	FV_BASE
+		DEVECHO	", KBD MODE=FV"
+		DEVECHO	", KBD IO="
+		DEVECHO	FV_KBDDATA
+		DEVECHO	"\n"
+;
+;======================================================================
+; FPGA VGA DRIVER - INITIALIZATION
+;======================================================================
+;
+FV_INIT:
+	LD	IY,FV_IDAT		; POINTER TO INSTANCE DATA
+;
+	CALL	NEWLINE			; FORMATTING
+	PRTS("FV: IO=0x$")
+	LD	A,FV_BASE
+	CALL	PRTHEXBYTE
+	CALL	FV_PROBE		; CHECK FOR HW PRESENCE
+	JR	Z,FV_INIT1		; CONTINUE IF HW PRESENT
+;
+	; HARDWARE NOT PRESENT
+	PRTS(" NOT PRESENT$")
+	OR	$FF			; SIGNAL FAILURE
+	RET
+;
+FV_INIT1:
+	; RECORD DRIVER ACTIVE
+	OR	$FF
+	LD	(FV_ACTIVE),A
+	; DISPLAY CONSOLE DIMENSIONS
+	LD	A,FV_COLS
+	CALL	PC_SPACE
+	CALL	PRTDECB
+	LD	A,'X'
+	CALL	COUT
+	LD	A,FV_ROWS
+	CALL	PRTDECB
+	PRTS(" TEXT$")
+
+	; HARDWARE INITIALIZATION
+	CALL 	FV_CRTINIT		; SETUP THE FPGA VGA CHIP REGISTERS
+	CALL	FV_VDAINI		; INITIALIZE
+	;CALL	KBD_INIT		; INITIALIZE KEYBOARD DRIVER
+
+	; ADD OURSELVES TO VDA DISPATCH TABLE
+	LD	BC,FV_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	LD	DE,FV_IDAT		; DE := FPGA VGA INSTANCE DATA PTR
+	CALL	VDA_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
+
+	; INITIALIZE EMULATION
+	LD	C,A			; C := ASSIGNED VIDEO DEVICE NUM
+	LD	DE,FV_FNTBL		; DE := FUNCTION TABLE ADDRESS
+	LD	HL,FV_IDAT		; HL := FPGA VGA INSTANCE DATA PTR
+	CALL	TERM_ATTACH		; DO IT
+
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+;======================================================================
+; FPGA VGA DRIVER - VIDEO DISPLAY ADAPTER (VDA) FUNCTIONS
+;======================================================================
+;
+FV_FNTBL:
+	.DW	FV_VDAINI
+	.DW	FV_VDAQRY
+	.DW	FV_VDARES
+	.DW	FV_VDADEV
+	.DW	FV_VDASCS
+	.DW	FV_VDASCP
+	.DW	FV_VDASAT
+	.DW	FV_VDASCO
+	.DW	FV_VDAWRC
+	.DW	FV_VDAFIL
+	.DW	FV_VDACPY
+	.DW	FV_VDASCR
+	.DW	FV_STAT
+	.DW	FV_FLUSH
+	.DW	FV_READ
+	.DW	FV_VDARDC
+#IF (($ - FV_FNTBL) != (VDA_FNCNT * 2))
+	.ECHO	"*** INVALID FV FUNCTION TABLE ***\n"
+	!!!!!
+#ENDIF
+
+FV_VDAINI:
+	; RESET VDA
+	CALL	FV_VDARES	; RESET VDA
+	LD	HL,0		; ZERO
+	LD	(FV_POS),HL	; ... TO POSITION
+	LD	A,' '		; BLANK THE SCREEN
+	LD	DE,FV_ROWS*FV_COLS	; FILL ENTIRE BUFFER
+	CALL	FV_FILL		; DO IT
+	LD	DE,0		; ROW = 0, COL = 0
+	CALL	FV_XY		; SEND CURSOR TO TOP LEFT
+	CALL	FV_SHOWCUR	; NOW SHOW THE CURSOR
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+FV_VDAQRY:
+	LD	C,$00		; MODE ZERO IS ALL WE KNOW
+	LD	D,FV_ROWS	; ROWS
+	LD	E,FV_COLS	; COLS
+	LD	HL,0		; EXTRACTION OF CURRENT BITMAP DATA NOT SUPPORTED
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+FV_VDARES:
+	CALL	 FV_CRTINIT
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+FV_VDADEV:
+	LD	D,VDADEV_FV	; D := DEVICE TYPE
+	LD	E,0		; E := PHYSICAL UNIT IS ALWAYS ZERO
+	LD	H,0		; H := 0, DRIVER HAS NO MODES
+	LD	L,FV_BASE	; L := BASE I/O ADDRESS
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+FV_VDASCS:
+	SYSCHKERR(ERR_NOTIMPL)	; NOT IMPLEMENTED (YET)
+	RET
+
+FV_VDASCP:
+	CALL	FV_XY		; SET CURSOR POSITION
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+FV_VDASAT:
+	; ATTRIBUTES NOT SUPPORTED BY HARDWARE
+	XOR	A
+	RET
+
+FV_VDASCO:
+	; CHARACTER COLOR NOT SUPPORT BY HARDWARE
+	XOR	A		; SIGNAL SUCCESS
+	RET			; DONE
+
+FV_VDAWRC:
+	LD	A,E		; CHARACTER TO WRITE GOES IN A
+	CALL	FV_PUTCHAR	; PUT IT ON THE SCREEN
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+FV_VDAFIL:
+	LD	A,E		; FILL CHARACTER GOES IN A
+	EX	DE,HL		; FILL LENGTH GOES IN DE
+	CALL	FV_FILL		; DO THE FILL
+	XOR	A		; SIGNAL SUCCESS
+	RET
+
+FV_VDACPY:
+	; LENGTH IN HL, SOURCE ROW/COL IN DE, DEST IS FV_POS
+	; BLKCPY USES: HL=SOURCE, DE=DEST, BC=COUNT
+	PUSH	HL		; SAVE LENGTH
+	CALL	FV_XY2IDX	; ROW/COL IN DE -> SOURCE ADR IN HL
+	POP	BC		; RECOVER LENGTH IN BC
+	LD	DE,(FV_POS)	; PUT DEST IN DE
+	JP	FV_BLKCPY	; DO A BLOCK COPY
+
+FV_VDASCR:
+	LD	A,E		; LOAD E INTO A
+	OR	A		; SET FLAGS
+	RET	Z		; IF ZERO, WE ARE DONE
+	PUSH	DE		; SAVE E
+	JP	M,FV_VDASCR1	; E IS NEGATIVE, REVERSE SCROLL
+	CALL	FV_SCROLL	; SCROLL FORWARD ONE LINE
+	POP	DE		; RECOVER E
+	DEC	E		; DECREMENT IT
+	JR	FV_VDASCR	; LOOP
+FV_VDASCR1:
+	CALL	FV_RSCROLL	; SCROLL REVERSE ONE LINE
+	POP	DE		; RECOVER E
+	INC	E		; INCREMENT IT
+	JR	FV_VDASCR	; LOOP
+
+FV_STAT:
+	IN	A,(FV_KBDST)		; GET STATUS
+	AND	$01			; ISOLATE DATA WAITING BIT
+	JP	Z,CIO_IDLE		; NO DATA, EXIT VIA IDLE PROCESS
+	RET
+
+FV_FLUSH:
+	XOR	A			; SIGNAL SUCCESS
+	RET
+
+FV_READ:
+	CALL	FV_STAT			; GET STATUS
+	JR	Z,FV_READ		; LOOP TILL DATA READY
+	IN	A,(FV_KBDDATA)		; GET BYTE
+	LD	E,A			; PUT IN E FOR RETURN
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+
+;----------------------------------------------------------------------
+; READ VALUE AT CURRENT VDU BUFFER POSITION
+; RETURN E = CHARACTER, B = COLOUR, C = ATTRIBUTES
+;----------------------------------------------------------------------
+
+FV_VDARDC:
+	CALL	FV_GETCHAR	; GET THE CHARACTER AT CUR CUR POS
+	LD	E,A		; PUT IN E
+	LD	BC,0		; COLOR AND ATTR NOT SUPPORTED
+	XOR	A		; SIGNAL SUCCESS
+	RET
+;
+;======================================================================
+; FPGA VGA DRIVER - PRIVATE DRIVER FUNCTIONS
+;======================================================================
+;
+;
+;----------------------------------------------------------------------
+; PROBE FOR FPGA VGA HARDWARE
+;----------------------------------------------------------------------
+;
+; ON RETURN, ZF SET INDICATES HARDWARE FOUND
+;
+FV_PROBE:
+	XOR	A			; ASSUME H/W EXISTS
+	RET
+;
+;----------------------------------------------------------------------
+; CRTC DISPLAY CONTROLLER CHIP INITIALIZATION
+;----------------------------------------------------------------------
+;
+FV_CRTINIT:
+	LD	A,%11001111		; WHITE ON BLACK, CURSOR ON, ENABLE OUTPUT
+	OUT	(FV_CTL),A		; WRITE TO CONTROL PORT
+	XOR	A			; ZERO ACCUM
+	RET				; DONE
+;
+;----------------------------------------------------------------------
+; SET CURSOR POSITION TO ROW IN D AND COLUMN IN E
+;----------------------------------------------------------------------
+;
+FV_XY:
+	CALL	FV_HIDECUR		; HIDE THE CURSOR
+	PUSH	DE			; SAVE NEW POSITION FOR NOW
+	CALL	FV_XY2IDX		; CONVERT ROW/COL TO BUF IDX
+	LD	(FV_POS),HL		; SAVE THE RESULT (DISPLAY POSITION)
+	POP	DE			; RECOVER INCOMING ROW/COL
+	LD	A,D			; GET ROW
+	OUT	(FV_CROW),A		; SET ROW REGISTER
+	LD	A,E			; GET COL
+	INC	A			; 1..79,0 (WHY???)
+	CP	80			; COL 80?
+	JR	NZ, FV_XY1		; SKIP IF NOT
+	XOR	A			; ELSE MAKE IT ZERO!
+FV_XY1:
+	OUT	(FV_CCOL),A		; SET COL REGISTER
+	JP	FV_SHOWCUR		; SHOW THE CURSOR AND EXIT
+;
+;----------------------------------------------------------------------
+; CONVERT XY COORDINATES IN DE INTO LINEAR INDEX IN HL
+; D=ROW, E=COL
+;----------------------------------------------------------------------
+;
+FV_XY2IDX:
+	LD	A,E			; SAVE COLUMN NUMBER IN A
+	LD	H,D			; SET H TO ROW NUMBER
+	LD	E,FV_COLS		; SET E TO ROW LENGTH
+	CALL	MULT8			; MULTIPLY TO GET ROW OFFSET, H * E = HL, E=0, B=0
+	LD	E,A			; GET COLUMN BACK
+	ADD	HL,DE			; ADD IT IN
+	RET				; RETURN
+;
+;----------------------------------------------------------------------
+; SHOW OR HIDE CURSOR
+;----------------------------------------------------------------------
+;
+FV_SHOWCUR:
+	LD	A,%11001111		; CONTROL PORT VALUE
+	;;;LD	A,%11111111		; CONTROL PORT VALUE
+	OUT	(FV_CTL),A		; SET REGISTER
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+FV_HIDECUR:
+	LD	A,%11001111		; CONTROL PORT VALUE
+	;;;LD	A,%11111111		; CONTROL PORT VALUE
+	OUT	(FV_CTL),A		; SET REGISTER
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+;----------------------------------------------------------------------
+; (DE)SELECT FRAME BUFFER
+;----------------------------------------------------------------------
+;
+FV_BUFSEL:
+	PUSH	AF
+	LD	A,$01
+	OUT	(FV_BUFCTL),A
+	POP	AF
+	RET
+;
+FV_BUFDESEL:
+	PUSH	AF
+	XOR	A
+	OUT	(FV_BUFCTL),A
+	POP	AF
+	RET
+;
+;----------------------------------------------------------------------
+; WRITE VALUE IN A TO CURRENT VDU BUFFER POSITION, ADVANCE CURSOR
+;----------------------------------------------------------------------
+;
+FV_PUTCHAR:
+	; WRITE CHAR AT CURRENT CURSOR POSITION.
+	PUSH	AF			; SAVE INCOMING CHAR
+	CALL	FV_HIDECUR		; HIDE CURSOR
+	CALL	FV_BUFSEL		; SELECT FRAME BUFFER
+	POP	AF
+	LD	HL,(FV_POS)		; GET CUR BUF POSITION
+	LD	DE,FV_FBUF		; START OF FRAME BUF
+	ADD	HL,DE			; ADD IT IN
+	LD	(HL),A			; PUT THE CHAR
+;
+	; SET NEW POSITION
+	LD	HL,(FV_POS)		; GET POSITION
+	INC	HL			; BUMP POSITION
+	LD	(FV_POS),HL		; SAVE NEW POSITION
+;
+	; PUT CUROR IN PLACE
+	LD	DE,FV_COLS		; COLS PER LINE
+	CALL	DIV16			; BC=ROW, HL=COL
+	LD	D,C
+	LD	E,L
+	CALL	FV_XY
+	CALL	FV_BUFDESEL		; DESELECT FRAME BUFFER
+	JP	FV_SHOWCUR		; SHOW IT AND RETURN
+;
+;----------------------------------------------------------------------
+; GET CHAR VALUE TO A FROM CURRENT VDU BUFFER POSITION
+;----------------------------------------------------------------------
+;
+FV_GETCHAR:
+	XOR	A
+	RET
+;
+;----------------------------------------------------------------------
+; FILL AREA IN BUFFER WITH SPECIFIED CHARACTER AND CURRENT COLOR/ATTRIBUTE
+; STARTING AT THE CURRENT FRAME BUFFER POSITION
+;   A: FILL CHARACTER
+;   DE: NUMBER OF CHARACTERS TO FILL
+;----------------------------------------------------------------------
+;
+FV_FILL:
+	PUSH	AF			; SAVE INCOMING FILL CHAR
+	CALL	FV_HIDECUR		; HIDE CURSOR
+	CALL	FV_BUFSEL		; SELECT BUFFER
+	LD	HL,(FV_POS)		; CUR POS TO HL
+	LD	BC,FV_FBUF		; ADR OF FRAME
+	ADD	HL,BC			; ADD IT IN
+	POP	AF
+	LD	C,A			; FILL CHAR TO C
+FV_FILL1:
+	LD	A,D			; CHECK FILL
+	OR	E			; ... COUNTER
+	JR	Z,FV_FILL2		; DONE IF ZERO
+	LD	(HL),C			; FILL ONE CHAR
+	INC	HL			; BUMP BUF PTR
+	DEC	DE			; DEC FILL COUNTER
+	JR	FV_FILL1		; LOOP
+;
+FV_FILL2:
+	CALL	FV_BUFDESEL		; DESELECT BUFFER
+	JP	FV_SHOWCUR		; EXIT VIA SHOW CURSOR
+;
+;----------------------------------------------------------------------
+; SCROLL ENTIRE SCREEN FORWARD BY ONE LINE (CURSOR POSITION UNCHANGED)
+;----------------------------------------------------------------------
+;
+FV_SCROLL:
+	CALL	FV_BUFSEL				; SELECT FRAME BUFFER
+;
+	; COPY "UP" ONE LINE
+	LD	HL,FV_FBUF + FV_COLS 			; FROM SECOND LINE
+	LD	DE,FV_FBUF				; TO FIRST LINE
+	LD	BC,+(FV_ROWS - 1) * FV_COLS		; ALL BUT ONE LINE
+	LDIR						; DO IT
+;
+	; FILL LAST LINE OF SCREEN
+	LD	HL,FV_FBUF + ((FV_ROWS - 1) * FV_COLS)	; LAST LINE
+	LD	A,' '					; FILL CHAR
+	LD	(HL),A					; COPY 1 CHAR
+	LD	DE,FV_FBUF + ((FV_ROWS - 1) * FV_COLS) + 1	; SECOND POS IN LAST LINE
+	LD	BC,FV_COLS - 1				; COLS PER LINE - 1
+	LDIR						; FILL IT
+;
+	CALL	FV_BUFDESEL				; DESELECT FRAME BUFFER
+	RET						; DONE
+;
+;----------------------------------------------------------------------
+; REVERSE SCROLL ENTIRE SCREEN BY ONE LINE (CURSOR POSITION UNCHANGED)
+;----------------------------------------------------------------------
+;
+FV_RSCROLL:
+	CALL	FV_BUFSEL				; SELECT FRAME BUFFER
+;
+	; COPY "DOWN" ONE LINE
+	LD	HL,FV_FBUF + (FV_COLS * (FV_ROWS - 1)) - 1 	; FROM END OF SECOND TO LAST LINE
+	LD	DE,FV_FBUF + (FV_COLS * FV_ROWS) - 1	; TO END OF LAST LINE
+	LD	BC,+(FV_ROWS - 1) * FV_COLS		; ALL BUT ONE LINE
+	LDDR						; DO IT IN REVERSE
+;
+	; FILL FIRST LINE OF SCREEN
+	LD	HL,FV_FBUF				; FIRST LINE
+	LD	A,' '					; FILL CHAR
+	LD	(HL),A					; COPY 1 CHAR
+	LD	DE,FV_FBUF + 1				; SECOND POS IN FIRST LINE
+	LD	BC,FV_COLS - 1				; COLS PER LINE - 1
+	LDIR						; FILL IT
+;
+	CALL	FV_BUFDESEL				; DESELECT FRAME BUFFER
+	RET						; DONE
+;
+;----------------------------------------------------------------------
+; BLOCK COPY BC BYTES FROM HL TO DE
+;----------------------------------------------------------------------
+;
+FV_BLKCPY:
+
+	CALL	FV_BUFSEL				; SELECT FRAME BUFFER
+	PUSH	BC					; SAVE LENGTH
+	LD	BC,FV_FBUF				; FRAME BUFFER ADR
+	ADD	HL,BC					; ADD TO SOURCE
+	EX	DE,HL					; EXCHANGE
+	ADD	HL,BC					; ADD TO DEST
+	EX	DE,HL					; EXCHANGE
+	POP	BC					; RECOVER LENGTH
+	LDIR						; LDIR DOES THE COPY
+	CALL	FV_BUFDESEL				; DESELECT FRAME BUFFER
+	RET						; DONE
+;
+;==================================================================================================
+;   FPGA VGA DRIVER - DATA
+;==================================================================================================
+;
+FV_POS		.DW 	0	; CURRENT DISPLAY POSITION
+FV_ACTIVE	.DB	FALSE	; FLAG FOR DRIVER ACTIVE
+;
+;==================================================================================================
+;   VGA DRIVER - INSTANCE DATA
+;==================================================================================================
+;
+FV_IDAT:
+	.DB	KBDMODE_FV	; FPGA VGA KEYBOARD CONTROLLER
+	.DB	FV_KBDST
+	.DB	FV_KBDDATA
--- a/Source/HBIOS/h8p.asm
+++ b/Source/HBIOS/h8p.asm
@@ -12,8 +12,31 @@
 ;	+--10--+  80
 ;
 ;
-	DEVECHO	"H8P: IO=??"
-	;DEVECHO	0
+H8PKEYNONE	.EQU	$FF		; NONE
+H8PKEY0		.EQU	$FE
+H8PKEY1		.EQU	$FC
+H8PKEY2		.EQU	$FA
+H8PKEY3		.EQU	$F8
+H8PKEY4		.EQU	$F6
+H8PKEY5		.EQU	$F4
+H8PKEY6		.EQU	$F2
+H8PKEY7		.EQU	$F0
+H8PKEY8		.EQU	$EF
+H8PKEY9		.EQU	$CF
+H8PKEYPLUS	.EQU	$AF		; PLUS
+H8PKEYMINUS	.EQU	$8F		; MINUS
+H8PKEYMUL	.EQU	$6F		; MULTIPLY
+H8PKEYDIV	.EQU	$4F		; DIVIDE
+H8PKEYNUM	.EQU	$2F		; NUMBER
+H8PKEYDOT	.EQU	$0F		; DOT
+;
+H8P_TICCNT	.EQU	$FFEA		; TICCNT AT $FFEA IS COPIED DOWN TO $000B FOR HEATH COMPATIBILITY
+H8P_SPEED	.EQU	$FFEC		; SPEED CONTROL VALUE IS STORED HERE
+H8P_SPDIO	.EQU	$30
+H8FPIO		.EQU	$F0
+;
+	DEVECHO	"H8P: IO="
+	DEVECHO	H8FPIO
 	DEVECHO	"\n"
 ;
 ;__H8P_PREINIT_______________________________________________________________________________________
@@ -24,144 +47,856 @@
 ; HARDWARE RESET PRIOR TO ROMWBW CONSOLE INITIALIZATION
 ;
 H8P_PREINIT:
-	LD	A,(DSKY_DISPACT)	; DSKY DISPATCHER ALREADY SET?
-	OR	A			; SET FLAGS
-	RET	NZ			; IF ALREADY ACTIVE, ABORT
-;
-	; REGISTER DRIVER WITH HBIOS
-	LD	BC,H8P_DISPATCH
-	CALL	DSKY_SETDISP
+	LD	HL,H8P_INTR
+	CALL	HB_ADDIM1
 ;
 	RET
 ;
 ;__H8P_INIT__________________________________________________________________________________________
 ;
-;  DISPLAY DSKY INFO ON ROMWBW CONSOLE
+;  DISPLAY H8 FRONT PANEL INFO ON ROMWBW CONSOLE
 ;____________________________________________________________________________________________________
 ;
 H8P_INIT:
 	CALL	NEWLINE			; FORMATTING
-	PRTS("H8P:$")			; DRIVER TAG
+	PRTS("H8FP:$")			; FORMATTING
+;
+	PRTS(" IO=0x$")			; FORMATTING
+	LD	A,H8FPIO		; GET BASE PORT
+	CALL	PRTHEXBYTE		; PRINT BASE PORT
 ;
 	RET				; DONE
 ;
-; DSKY DEVICE FUNCTION DISPATCH ENTRY
-;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
-;   B: FUNCTION (IN)
+; H8 FRONT PANEL INTERRUPT
 ;
-H8P_DISPATCH:
-	LD	A,B			; GET REQUESTED FUNCTION
-	AND	$0F			; ISOLATE SUB-FUNCTION
-	JP	Z,H8P_RESET		; RESET DSKY HARDWARE
-	DEC	A	
-	JP	Z,H8P_STAT		; GET KEYPAD STATUS
-	DEC	A	
-	JP	Z,H8P_GETKEY		; READ A KEY FROM THE KEYPAD
-	DEC	A	
-	JP	Z,H8P_SHOWHEX		; DISPLAY A 32-BIT BINARY VALUE IN HEX
-	DEC	A	
-	JP	Z,H8P_SHOWSEG		; DISPLAY SEGMENTS
-	DEC	A	
-	JP	Z,H8P_KEYLEDS		; SET KEYPAD LEDS
-	DEC	A	
-	JP	Z,H8P_STATLED		; SET STATUS LED
-	DEC	A	
-	JP	Z,H8P_BEEP		; BEEP DSKY SPEAKER
-	DEC	A
-	JP	Z,H8P_DEVICE		; DEVICE INFO
-	SYSCHKERR(ERR_NOFUNC)
+H8P_INTR:
+	LD	(H8P_BCVAL),BC
+	LD	(H8P_DEVAL),DE
+	LD	(H8P_HLVAL),HL
+	LD	HL,(H8P_TICCNT)		; 2MS TIC COUNTER
+	INC	HL
+	LD	(H8P_TICCNT),HL
+	CALL	H8P_TIMER		; UP TIMER
+	CALL	H8P_STAT		; CHECK KEYPAD PRESS
+	CALL	H8P_GETSEGIDX		; SEGMENT INDEX IN (C)
+	CALL	H8P_HORN
+	OR	C
+	OUT	(H8FPIO),A		; CLEAR INTERRUPT AND SET LED IDX
+	LD	C,A
+	LD	A,(H8P_FPENA)
+	OR	A
+	LD	A,$FF
+	CALL	NZ,H8P_GETSEGPAT
+	OUT	(H8FPIO+1),A		; SET LED PATTERN
+;
+	CALL	H8P_KEYPAD
+	LD	A,(H8P_STTIMER)
+	INC	A
+	AND	$1F			; UPDATE LEDS EVERY 32 TICKS
+	LD	(H8P_STTIMER),A
+	CALL	Z,H8P_HDLSTATE
+	LD	A,(H8P_HBTICK)		; ROMWBW TIMER
+	INC	A
+	LD	(H8P_HBTICK),A
+	CP	10
+	RET	NZ
+	CALL	HB_TICK
+	XOR	A
+	LD	(H8P_HBTICK),A
+	INC	A			; INTERRUPT HANDLED
 	RET
 ;
-; RESET DSKY -- CLEAR DISPLAY AND KEYPAD FIFO
+; HANDLE FRONT PANEL SPEAKER SOUNDS
 ;
-H8P_RESET:
-	XOR	A			; SIGNAL SUCCESS
+H8P_HORN:
+	LD	HL,(H8P_HORNDUR)
+	LD	A,H
+	OR	L
+	LD	A,$D0			; HORN OFF
+	RET	Z
+	DEC	HL
+	LD	(H8P_HORNDUR),HL
+	LD	A,$50			; HORN ON
 	RET
 ;
-;  CHECK FOR KEY PRESS, SAVE RAW VALUE, RETURN STATUS
+; HANDLE UP-TIME TIMER
+;
+H8P_TIMER:
+	LD	HL,(H8P_ONESEC)
+	DEC	HL
+	LD	(H8P_ONESEC),HL
+	LD	A,H
+	OR	L
+	RET	NZ
+	LD	HL,(H8P_UPTIME)
+	INC	HL
+	LD	(H8P_UPTIME),HL
+	LD	HL,500
+	LD	(H8P_ONESEC),HL
+	CALL	H8P_TIMER1
+	LD	A,(H8P_STATE)
+	OR	A
+	CALL	Z,H8P_TIMER2
+	RET
+; ADVANCE DIGITS
+H8P_TIMER1:
+	LD	C,9
+	LD	HL,H8P_UPTDIG+8
+	CALL	H8P_ADVDIG
+	RET
+; SHOW DIGITS
+H8P_TIMER2:
+	LD	DE,H8P_UPTDIG+8
+	LD	HL,H8P_SEGBUF+8
+	LD	C,9
+H8P_TIMER3:
+	PUSH	BC
+	PUSH	HL
+	LD	A,C
+	CP	7
+	JR	Z,H8P_TIMER4
+	CP	4
+	JR	Z,H8P_TIMER4
+	JR	H8P_TIMER5
+H8P_TIMER4:
+	LD	A,$80
+	JR	H8P_TIMER6
+H8P_TIMER5:
+	LD	HL,H8P_DIGMAP
+	LD	A,(DE)
+	LD	C,A
+	LD	B,0
+	ADD	HL,BC
+	LD	A,(HL)
+H8P_TIMER6:
+	POP	HL
+	LD	(HL),A
+	DEC	HL
+	DEC	DE
+	POP	BC
+	DEC	C
+	JR	NZ,H8P_TIMER3
+	RET
+H8P_ADVDIG:
+	LD	A,(HL)			; 000.000.00X
+	INC	A
+	LD	(HL),A
+	CP	10			; 0-9
+	RET	NZ
+	LD	(HL),0
+	DEC	HL
+	LD	A,(HL)			; 000.000.0X0
+	INC	A
+	LD	(HL),A
+	CP	6			; 0-5
+	RET	NZ
+	LD	(HL),0
+	DEC	HL
+	DEC	HL
+	LD	A,(HL)			; 000.00X.000
+	INC	A
+	LD	(HL),A
+	CP	10			; 0-9
+	RET	NZ
+	LD	(HL),0
+	DEC	HL
+	LD	A,(HL)			; 000.0X0.000
+	INC	A
+	LD	(HL),A
+	CP	6			; 0-5
+	RET	NZ
+	LD	(HL),0
+	DEC	HL
+	DEC	HL
+	LD	A,(HL)			; 00X.000.000
+	INC	A
+	LD	(HL),A
+	CP	10			; 0-9
+	RET	NZ
+	LD	(HL),0
+	DEC	HL
+	LD	A,(HL)			; 0X0.000.000
+	INC	A
+	LD	(HL),A
+	CP	10			; 0-9
+	RET	NZ
+	LD	(HL),0
+	DEC	HL
+	LD	A,(HL)			; X00.000.000
+	INC	A
+	LD	(HL),A
+	CP	10			; 0-9
+	RET	NZ
+	LD	(HL),0
+	RET
+;
+;  CHECK FOR KEY PRESS, SAVE RAW VALUE
 ;
 H8P_STAT:
-	XOR	A			; ZERO KEYS PENDING (FOR NOW)
+	IN	A,(H8FPIO)
+	LD	(H8P_KEYBUF),A
 	RET
 ;
-;  WAIT FOR A DSKY KEYPRESS AND RETURN
+;  GET KEY AND RESET KEYBUF
 ;
 H8P_GETKEY:
-	; PUT KEY VALUE IN REGISTER E
-	XOR	A			; SIGNAL SUCCESS	
+	LD	A,(H8P_KEYBUF)
 	RET
 ;
-; DISPLAY HEX VALUE FROM DE:HL
+H8P_KEYPAD:
+	CALL	H8P_GETKEY
+	LD	C,A
+	LD	A,(H8P_LSTKEY)
+	CP	C
+	RET	Z
+	LD	A,C
+	LD	(H8P_LSTKEY),A
+	CP	H8PKEYNONE
+	RET	Z
+	LD	HL,$04
+	LD	(H8P_HORNDUR),HL
+	CP	H8PKEYDIV		; / KEY (ALTER)
+	JP	Z,H8P_KEYPADALT
+	CP	H8PKEYMUL		; * KEY (CANCEL)
+	JP	Z,H8P_KEYPADCAN
+	CP	H8PKEYNUM		; MEM KEY
+	JP	Z,H8P_KEYPADMEM
+	CP	H8PKEYDOT		; REG KEY
+	JP	Z,H8P_KEYPADREG
+	CP	H8PKEY9
+	JP	Z,H8P_KEYPAD9
+	CP	H8PKEY8
+	JP	Z,H8P_KEYPAD8
+	CP	H8PKEY7
+	JP	Z,H8P_KEYPAD7
+	CP	H8PKEY6
+	JP	Z,H8P_KEYPAD6
+	CP	H8PKEY5
+	JP	Z,H8P_KEYPAD5
+	CP	H8PKEY4
+	JP	Z,H8P_KEYPAD4
+	CP	H8PKEY3
+	JP	Z,H8P_KEYPAD3
+	CP	H8PKEY2
+	JP	Z,H8P_KEYPAD2
+	CP	H8PKEY1
+	JP	Z,H8P_KEYPAD1
+	CP	H8PKEY0
+	JP	Z,H8P_KEYPAD0
+	CP	H8PKEYPLUS
+	JP	Z,H8P_KEYPADPLUS
+	CP	H8PKEYMINUS
+	JP	Z,H8P_KEYPADMINUS
+	RET
+; RESET TIMER
+H8P_KEYPADALT:
+	LD	A,(H8P_FPENA)
+	OR	A
+	RET	Z
+	LD	A,(H8P_STATE)
+	OR	A
+	RET	NZ
+	XOR	A
+	LD	C,9
+	LD	HL,H8P_UPTDIG
+H8P_KEYPADALTL:
+	LD	(HL),A
+	INC	HL
+	DEC	C
+	JR	NZ,H8P_KEYPADALTL
+	RET
+; ENABLE FRONT PANEL DISPLAY
+H8P_KEYPADCAN:
+	LD	A,(H8P_FPENA)
+	CPL
+	LD	(H8P_FPENA),A
+	RET
+; SET MEM STATE
+H8P_KEYPADMEM:
+	LD	A,2
+	LD	(H8P_STATE),A
+	LD	(H8P_MEMENTER),A
+	XOR	A
+	LD	(H8P_MEMADRIDX),A
+	CALL	H8P_UPDMEMLOC
+	RET
+; SET REG STATE
+H8P_KEYPADREG:
+	LD	A,1
+	LD	(H8P_STATE),A
+	XOR	A
+	LD	(H8P_MEMENTER),A
+	RET
+; NOTHING
+H8P_KEYPAD9:
+;	RET
+; TIMER
+H8P_KEYPAD8:
+	LD	A,(H8P_STATE)
+	CP	2
+	RET	Z
+	LD	A,0
+	LD	(H8P_STATE),A
+	RET
+; SPEED CONTROL
+H8P_KEYPAD7:
+	LD	A,(H8P_STATE)
+	CP	2			; MEM MODE
+	LD	A,7
+	JP	Z,H8P_KEYPADDIG
+	LD	A,3
+	LD	(H8P_STATE),A
+	RET
+; PC (OUT)
+H8P_KEYPAD6:
+	LD	A,(H8P_STATE)
+	CP	2			; MEM MODE
+	LD	A,6
+	JP	Z,H8P_KEYPADDIG
+	LD	A,5
+	LD	(H8P_REGNUM),A
+	RET
+; HL (IN)
+H8P_KEYPAD5:
+	LD	A,(H8P_STATE)
+	CP	2			; MEM MODE
+	LD	A,5
+	JP	Z,H8P_KEYPADDIG
+	LD	A,3
+	LD	(H8P_REGNUM),A
+	RET
+; DE
+H8P_KEYPAD4:
+	LD	A,(H8P_STATE)
+	CP	2			; MEM MODE
+	LD	A,4
+	JP	Z,H8P_KEYPADDIG
+	LD	A,2
+	LD	(H8P_REGNUM),A
+	RET
+; BC
+H8P_KEYPAD3:
+	LD	A,(H8P_STATE)
+	CP	2			; MEM MODE
+	LD	A,3
+	JP	Z,H8P_KEYPADDIG
+	LD	A,1
+	LD	(H8P_REGNUM),A
+	RET
+; AF
+H8P_KEYPAD2:
+	LD	A,(H8P_STATE)
+	CP	2			; MEM MODE
+	LD	A,2
+	JP	Z,H8P_KEYPADDIG
+	LD	A,0
+	LD	(H8P_REGNUM),A
+	RET
+; SP
+H8P_KEYPAD1:
+	LD	A,(H8P_STATE)
+	CP	2			; MEM MODE
+	LD	A,1
+	JP	Z,H8P_KEYPADDIG
+	LD	A,4
+	LD	(H8P_REGNUM),A
+	RET
+; NOTHING
+H8P_KEYPAD0:
+	LD	A,(H8P_STATE)
+	CP	2			; MEM MODE
+	JP	NZ,H8P_KEYPAD8
+	LD	A,0
 ;
-H8P_SHOWHEX:
-	LD	BC,DSKY_HEXBUF		; POINT TO HEX BUFFER
-	CALL	ST32			; STORE 32-BIT BINARY THERE
-	LD	HL,DSKY_HEXBUF		; FROM: BINARY VALUE (HL)
-	LD	DE,DSKY_BUF		; TO: SEGMENT BUFFER (DE)
-	CALL	DSKY_BIN2SEG		; CONVERT
-	LD	HL,DSKY_BUF		; POINT TO SEGMENT BUFFER
-	; AND FALL THRU TO DISPLAY IT
-;
-; DISPLAY BYTE VALUES POINTED TO BY DE.  THE INCOMING BYTES ARE IN
-; THE STANDARD ROMWBW SEGMENT ENCODING AND MUST BE TRANSLATED TO THE
-; HEATH ENCODING (SEE ICM.ASM FOR EXAMPLE):
-;
-;
-;	From:		To:
-;	+--01--+	+--02--+
-;	20    02	40    04
-;	+--40--+	+--01--+
-;	10    04	20    08
-;	+--08--+  80	+--10--+  80
-;
-H8P_SHOWSEG:
-	XOR	A			; SIGNAL SUCCESS
+H8P_KEYPADDIG:
+	LD	C,A
+	LD	A,(H8P_MEMENTER)
+	OR	A
+	JR	Z,H8P_KEYPADDIG1
+	LD	A,(H8P_MEMADRIDX)
+	OR	A
+	CALL	Z,H8P_SETDIG0
+	DEC	A
+	CALL	Z,H8P_SETDIG1
+	DEC	A
+	CALL	Z,H8P_SETDIG2
+	DEC	A
+	CALL	Z,H8P_SETDIG3
+	DEC	A
+	CALL	Z,H8P_SETDIG4
+	DEC	A
+	CALL	Z,H8P_SETDIG5
+	CALL	H8P_UPDMEMLOC
+; NEXT MEMORY ADR INDEX
+	LD	A,(H8P_MEMADRIDX)
+	INC	A
+	LD	(H8P_MEMADRIDX),A
+	CP	6
+	RET	NZ
+	XOR	A
+	LD	(H8P_MEMADRIDX),A
+	RET
+; CHECK FOR IN/OUT TO PORT
+H8P_KEYPADDIG1:
+	LD	A,C
+	CP	5			; IN PORT
+	JR	Z,H8P_KEYPADINP
+	CP	6			; OUT PORT
+	JR	Z,H8P_KEYPADOUT
+	RET
+H8P_KEYPADINP:
+	LD	BC,(H8P_MEMLOC)
+	IN	A,(C)
+	LD	B,A
+	LD	(H8P_MEMLOC),BC
+	JP	H8P_UPDMEMLOC
+H8P_KEYPADOUT:
+	LD	BC,(H8P_MEMLOC)
+	LD	A,B
+	OUT	(C),A
+	RET
+H8P_UPDMEMLOC:
+	LD	BC,H8P_MEMLOC
+	LD	HL,H8P_SEGBUF
+	CALL	H8P_FILLOCT
+	RET
+; C=VAL
+H8P_SETDIG0:
+	LD	HL,(H8P_MEMLOC)
+	LD	B,H
+	CALL	H8P_SETOCTH
+	LD	H,A
+	LD	(H8P_MEMLOC),HL
+	LD	A,$FF
+	RET
+H8P_SETDIG1:
+	LD	HL,(H8P_MEMLOC)
+	LD	B,H
+	CALL	H8P_SETOCTM
+	LD	H,A
+	LD	(H8P_MEMLOC),HL
+	LD	A,$FF
+	RET
+H8P_SETDIG2:
+	LD	HL,(H8P_MEMLOC)
+	LD	B,H
+	CALL	H8P_SETOCTL
+	LD	H,A
+	LD	(H8P_MEMLOC),HL
+	LD	A,$FF
+	RET
+H8P_SETDIG3:
+	LD	HL,(H8P_MEMLOC)
+	LD	B,L
+	CALL	H8P_SETOCTH
+	LD	L,A
+	LD	(H8P_MEMLOC),HL
+	LD	A,$FF
+	RET
+H8P_SETDIG4:
+	LD	HL,(H8P_MEMLOC)
+	LD	B,L
+	CALL	H8P_SETOCTM
+	LD	L,A
+	LD	(H8P_MEMLOC),HL
+	LD	A,$FF
+	RET
+H8P_SETDIG5:
+	LD	HL,(H8P_MEMLOC)
+	LD	B,L
+	CALL	H8P_SETOCTL
+	LD	L,A
+	LD	(H8P_MEMLOC),HL
+	XOR	A
+	LD	(H8P_MEMENTER),A
+	LD	A,$FF
+	RET
+H8P_SETDIGD:
+	LD	A,(H8P_MEMVAL)
+	PUSH	AF
+	CALL	H8P_GETOCTH
+	LD	(H8P_SEGBUF+6),A
+	POP	AF
+	PUSH	AF
+	CALL	H8P_GETOCTM
+	LD	(H8P_SEGBUF+7),A
+	POP	AF
+	CALL	H8P_GETOCTL
+	LD	(H8P_SEGBUF+8),A
+	RET
+; MEM/SPEED INCREASE
+H8P_KEYPADPLUS:
+	LD	A,(H8P_STATE)
+	CP	3
+	JR	Z,H8P_KEYPADPLUS3
+	CP	2
+	RET	NZ
+	LD	HL,(H8P_MEMLOC)
+	INC	HL
+	LD	(H8P_MEMLOC),HL
+	JP	H8P_UPDMEMLOC
+H8P_KEYPADPLUS3:
+	LD	A,(H8P_SPEED)
+	OR	A
+	RET	Z
+	DEC	A
+	LD	(H8P_SPEED),A
+	OUT	(H8P_SPDIO),A
+	RET
+; MEM/SPEED DECREASE
+H8P_KEYPADMINUS:
+	LD	A,(H8P_STATE)
+	CP	3
+	JR	Z,H8P_KEYPADMINUS3
+	CP	2
+	RET	NZ
+	LD	HL,(H8P_MEMLOC)
+	DEC	HL
+	LD	(H8P_MEMLOC),HL
+	JP	H8P_UPDMEMLOC
+H8P_KEYPADMINUS3:
+	LD	A,(H8P_SPEED)
+	CP	3
+	RET	Z
+	INC	A
+	LD	(H8P_SPEED),A
+	OUT	(H8P_SPDIO),A
 	RET
 ;
-; UPDATE KEY LEDS (H8 HAS NONE)
+; HANDLE FRONT PANEL STATE
 ;
-H8P_KEYLEDS:
-	XOR	A			; SIGNAL SUCCESS
+H8P_HDLSTATE:
+	LD	A,(H8P_STATE)
+	OR	A
+	RET	Z			; UP-TIME TIMER
+	DEC	A
+	JP	Z,H8P_HDLREG		; SHOWING REGISTER VALUES
+	DEC	A
+	JP	Z,H8P_HDLMEM		; SHOWING MEMORY LOCATION VALUE
+	DEC	A
+	JP	Z,H8P_HDLSPD		; MODIFYING SPEED
 	RET
 ;
-; SET STATUS LEDS BASED ON BITS IN E
-;
-H8P_STATLED:
-	XOR	A			; SIGNAL SUCCESS
+H8P_HDLREG:
+	LD	A,(H8P_REGNUM)
+	LD	HL,H8P_REGAF
+	OR	A
+	JP	Z,H8P_HDLREGAF
+	DEC	A
+	LD	HL,H8P_REGBC
+	JP	Z,H8P_HDLREGBC
+	DEC	A
+	LD	HL,H8P_REGDE
+	JP	Z,H8P_HDLREGDE
+	DEC	A
+	LD	HL,H8P_REGHL
+	JP	Z,H8P_HDLREGHL
+	DEC	A
+	LD	HL,H8P_REGSP
+	JP	Z,H8P_HDLREGSP
+	DEC	A
+	LD	HL,H8P_REGPC
+	JP	Z,H8P_HDLREGPC
+	RET
+H8P_HDLREGAF:
+	CALL	H8P_UPDLEDS
+	LD	HL,HBX_INTSTK
+	DEC	HL
+	LD	A,(HL)			; (HL)=AF LOW
+	LD	(H8P_AFVAL),A
+	DEC	HL
+	LD	A,(HL)			; (HL)=AF HIGH
+	LD	(H8P_AFVAL+1),A
+	LD	BC,H8P_AFVAL
+	LD	HL,H8P_SEGBUF
+	JP	H8P_FILLOCT
+H8P_HDLREGBC:
+	LD	BC,H8P_BCVAL
+	CALL	H8P_FILLOCT
+	JP	H8P_UPDLEDS
+H8P_HDLREGDE:
+	LD	BC,H8P_DEVAL
+	CALL	H8P_FILLOCT
+	JP	H8P_UPDLEDS
+H8P_HDLREGHL:
+	CALL	H8P_UPDLEDS
+	LD	HL,(HBX_INT_SP)
+	LD	A,(HL)
+	LD	(H8P_HLVAL),A
+	INC	HL
+	LD	A,(HL)
+	LD	(H8P_HLVAL+1),A
+	LD	BC,H8P_HLVAL
+	LD	HL,H8P_SEGBUF
+	JP	H8P_FILLOCT
+H8P_HDLREGSP:
+	LD	BC,HBX_INT_SP
+	CALL	H8P_FILLOCT
+	JP	H8P_UPDLEDS
+H8P_HDLREGPC:
+	CALL	H8P_UPDLEDS
+	LD	HL,(HBX_INT_SP)		; (HL)=HL LOW
+	INC	HL			; (HL)=HL HIGH
+	INC	HL			; (HL)=PC LOW
+	LD	A,(HL)
+	LD	(H8P_PCVAL),A
+	INC	HL			; (HL)=PC HIGH
+	LD	A,(HL)
+	LD	(H8P_PCVAL+1),A
+	LD	BC,H8P_PCVAL
+	LD	HL,H8P_SEGBUF
+	JP	H8P_FILLOCT
+H8P_HDLMEM:
+	CALL	H8P_SETDIGD
+	RET
+H8P_HDLSPD:
+	LD	HL,H8P_SPD16
+	LD	A,(H8P_SPEED)
+	OR	A
+	JR	Z,H8P_UPDLEDS
+	LD	HL,H8P_SPD08
+	DEC	A
+	JR	Z,H8P_UPDLEDS
+	LD	HL,H8P_SPD04
+	DEC	A
+	JR	Z,H8P_UPDLEDS
+	LD	HL,H8P_SPD02
+H8P_UPDLEDS:
+	LD	C,9
+	LD	DE,H8P_SEGBUF
+H8P_UPDLEDS1:
+	LD	A,(HL)
+	INC	HL
+	LD	(DE),A
+	INC	DE
+	DEC	C
+	JR	NZ,H8P_UPDLEDS1
 	RET
 ;
-; BEEP THE SPEAKER ON THE H8P
+H8P_GETSEGIDX:
+	LD	A,(H8P_SEGIDX)
+	DEC	A
+	LD	(H8P_SEGIDX),A
+	LD	C,A
+	RET	NZ
+	LD	A,9
+	LD	(H8P_SEGIDX),A
+	LD	C,A
+	RET
+;
+;	A = SEG IDX
+;
+;	+--02--+
+;	40    04
+;	+--01--+
+;	20    08
+;	+--10--+  80
+;
+H8P_GETSEGPAT:
+	LD	A,C
+	AND	$0F			; IDX=1 THRU 9
+	DEC	A
+	LD	C,A
+	LD	B,0
+	LD	HL,H8P_SEGBUF
+	ADD	HL,BC
+	LD	E,(HL)
+	LD	A,(H8P_MEMENTER)
+	OR	A
+	JR	Z,H8P_GETSEGPATX
+	LD	A,(H8P_MEMADRIDX)
+	CP	C
+	JR	NZ,H8P_GETSEGPATX
+	LD	A,$80
+	OR	E
+	LD	E,A
+H8P_GETSEGPATX:
+	LD	A,E
+	CPL
+	RET
+; BC=MEMLOC, HL=LED BUFFER
+H8P_FILLOCT:
+	PUSH	HL
+	INC	BC			; POINT TO HIGH BYTE
+	LD	A,(BC)
+	CALL	H8P_GETOCTH
+	LD	(HL),A
+	INC	HL
+	LD	A,(BC)
+	CALL	H8P_GETOCTM
+	LD	(HL),A
+	INC	HL
+	LD	A,(BC)
+	CALL	H8P_GETOCTL
+	LD	(HL),A
+	INC	HL
+	DEC	BC			; POINT TO LOW BYTE
+	LD	A,(BC)
+	CALL	H8P_GETOCTH
+	LD	(HL),A
+	INC	HL
+	LD	A,(BC)
+	CALL	H8P_GETOCTM
+	LD	(HL),A
+	INC	HL
+	LD	A,(BC)
+	CALL	H8P_GETOCTL
+	LD	(HL),A
+	POP	HL
+	RET
+; HIGH OCTAL BITS
+H8P_GETOCTH:
+	AND	$C0
+	RRA
+	RRA
+	RRA
+	RRA
+	RRA
+	RRA
+	JR	H8P_GETOCTX
+; MEDIUM OCTAL BITS
+H8P_GETOCTM:
+	AND	$38
+	RRA
+	RRA
+	RRA
+	JR	H8P_GETOCTX
+; LOW OCTAL BITS
+H8P_GETOCTL:
+	AND	$07
+H8P_GETOCTX:
+	PUSH	HL
+	LD	E,A
+	LD	D,0
+	LD	HL,H8P_DIGMAP
+	ADD	HL,DE
+	LD	A,(HL)			; VALUE CONVERTED TO LED SEGMENT PATTERN
+	POP	HL
+	RET
+; B=CURVAL, C=NEWVAL
+H8P_SETOCTH:
+	LD	A,C
+	AND	$03
+	RLA
+	RLA
+	RLA
+	RLA
+	RLA
+	RLA
+	LD	C,A
+	LD	A,B
+	AND	$3F
+	OR	C
+	RET
+H8P_SETOCTM:
+	LD	A,C
+	AND	$07
+	RLA
+	RLA
+	RLA
+	LD	C,A
+	LD	A,B
+	AND	$C7
+	OR	C
+	RET
+H8P_SETOCTL:
+	LD	A,C
+	AND	$07
+	LD	C,A
+	LD	A,B
+	AND	$F8
+	OR	C
+	CALL	H8P_BEEP
+	RET
 ;
 H8P_BEEP:
-	POP	BC
-	XOR	A			; SIGNAL SUCCESS
+	PUSH	HL
+	LD	HL,16
+	LD	(H8P_HORNDUR),HL
+	POP	HL
 	RET
 ;
 ; DEVICE INFORMATION
 ;
 H8P_DEVICE:
-	LD	D,DSKYDEV_H8P		; D := DEVICE TYPE
+;	LD	D,DSKYDEV_H8P		; D := DEVICE TYPE
 	LD	E,0			; E := PHYSICAL DEVICE NUMBER
 	LD	H,0			; H := MODE
-	LD	L,0			; L := BASE I/O ADDRESS
+	LD	L,H8FPIO		; L := BASE I/O ADDRESS
 	XOR	A			; SIGNAL SUCCESS
 	RET
 ;
-;_KEYMAP_TABLE_____________________________________________________________________________________________________________
+; DIGITS TO LED PATTERNS
+;	+--02--+
+;	40    04
+;	+--01--+
+;	20    08
+;	+--10--+  80
 ;
-H8P_KEYMAP:	; *** NEEDS TO BE UPDATED ***
-	; POS	$00  $01  $02  $03  $04  $05  $06  $07
-	; KEY   [0]  [1]  [2]  [3]  [4]  [5]  [6]  [7]
-	.DB	$0D, $04, $0C, $14, $03, $0B, $13, $02
+H8P_DIGMAP:
+	;	  0    1    2    3    4    5    6    7
+	.DB	$7E, $0C, $37, $1F, $4D, $5B, $7B, $0E
+	;	  8    9    A    B    C    D    E    F
+	.DB	$7F, $5F, $6F, $79, $72, $3D, $73, $63
 ;
-	; POS	$08  $09  $0A  $0B  $0C  $0D  $0E  $0F
-	; KEY   [8]  [9]  [A]  [B]  [C]  [D]  [E]  [F]
-	.DB	$0A, $12, $01, $09, $11, $00, $08, $10
+H8P_REGNUM:
+	.DB	0
+H8P_REGAF:
+	.DB	$00, $00, $00, $00, $00, $00, $00, $6F, $63
+H8P_REGBC:
+	.DB	$00, $00, $00, $00, $00, $00, $00, $79, $72
+H8P_REGDE:
+	.DB	$00, $00, $00, $00, $00, $00, $00, $3D, $73
+H8P_REGHL:
+	.DB	$00, $00, $00, $00, $00, $00, $00, $6D, $70
+H8P_REGSP:
+	.DB	$00, $00, $00, $00, $00, $00, $00, $5B, $67
+H8P_REGPC:
+	.DB	$00, $00, $00, $00, $00, $00, $00, $67, $72
+H8P_SPD16:
+	.DB	$00, $00, $00, $00, $0C, $7B, $5B, $67, $3D
+H8P_SPD08:
+	.DB	$00, $00, $00, $00, $00, $7F, $5B, $67, $3D
+H8P_SPD04:
+	.DB	$00, $00, $00, $00, $00, $4D, $5B, $67, $3D
+H8P_SPD02:
+	.DB	$00, $00, $00, $00, $00, $37, $5B, $67, $3D
+H8P_MEMADRIDX:
+	.DB	0
+H8P_MEMENTER:
+	.DB	0
+H8P_AFVAL:
+	.DW	0
+H8P_BCVAL:
+	.DW	0
+H8P_DEVAL:
+	.DW	0
+H8P_HLVAL:
+	.DW	0
+H8P_PCVAL:
+	.DW	0
 ;
-	; POS	$10  $11  $12  $13  $14  $15  $16  $17
-	; KEY   [FW] [BK] [CL] [EN] [DE] [EX] [GO] [BO]
-	.DB	$05, $15, $1D, $1C, $1B, $1A, $19, $18
-
-	; POS	$18  $19  $1A  $1B
-	; KEY   [F4] [F3] [F2] [F1]
-	.DB	$23, $22, $21, $20
+H8P_STATE:
+	.DB	00
+H8P_STTIMER:
+	.DB	00
+H8P_FPENA:
+	.DB	$FF
+H8P_SEGIDX:
+	.DB	09
+H8P_HBTICK:
+	.DB	00
+H8P_KEYBUF:
+	.DB	00
+H8P_LSTKEY:
+	.DB	00
+H8P_SEGBUF:
+	.DB	$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
+H8P_HORNDUR:
+	.DW	$0080
+H8P_ONESEC:
+	.DW	500
+H8P_UPTIME:
+	.DW	0
+H8P_UPTDIG:
+	.DB	0,0,0,0,0,0,0,0,0
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Wayne Warthen	6e8bdb141d	Finalize S100 FPGA Z80 Onboard VGA/PS2 Support - RomWBW will now "follow" the S100 monitors console selection for all 3 possibilities (USB Serial, Propeller Console, and Onboard VGA/PS2).	2024-09-04 17:15:23 -07:00
Wayne Warthen	d152cab8c8	Update Doc	2024-09-04 12:22:58 -07:00
Wayne Warthen	3dd394e3c9	Update GMZ180_std.asm - Minor filename case issue caused some build scenarios to fail.	2024-09-04 11:40:36 -07:00
Wayne Warthen	2fd65ab4b0	Miscellaneous - Cosmetic updates - Fix fv.asm keyboard status function - Bump version number	2024-09-04 11:25:41 -07:00
Wayne Warthen	14dd7bf290	Merge pull request #416 from drj113/master Genesis Modules initial commit	2024-09-04 10:46:25 -07:00
drj113	673f4358b2	Rectified GM configuration to support current hbios.asm Re-added commented out code in the various disk drivers now that I am using the correct hbios.asm file	2024-09-04 11:16:45 +10:00
drj113	34e472a553	Initial Commit for Genesis Modules boards Supports GM STD Z180 and GM IDE Disk Controller	2024-09-04 10:13:05 +10:00
Wayne Warthen	e07c38dc1a	Doc Fixes per HubertH See Issue #415. This commit is intended to clarify the documentation with respect to this issue. Thanks and credit to HubertH.	2024-09-03 15:04:50 -07:00
Wayne Warthen	9e6780a248	Add FPGA Z80 Onboard VGA/PS2 Support	2024-09-03 12:05:34 -07:00
Wayne Warthen	d80c44045f	Merge pull request #414 from kiwisincebirth/map/fix-lcd-cpu	2024-08-30 08:11:04 -07:00
Mark Pruden	b7352da5c1	Fix for LCD Display of CPU Type	2024-08-30 13:33:44 +10:00
Wayne Warthen	2b6fbe7c58	HD44780 LCD Support	2024-08-27 15:34:44 -07:00
Wayne Warthen	e3173ff802	Regen PDF Docs	2024-08-26 13:11:13 -07:00
Wayne Warthen	8aebf93fdf	Merge pull request #411 from kiwisincebirth/map/clock-userguide Realtime Clock User Guide	2024-08-26 13:01:02 -07:00
Mark Pruden	51676238c7	Merge remote-tracking branch 'origin/master' into map/clock-userguide # Conflicts: # Doc/ChangeLog.txt	2024-08-26 18:58:45 +10:00
Mark Pruden	983c0ff52b	Improved section Real Time Clock in User Guide document	2024-08-26 18:37:09 +10:00
Mark Pruden	764abddb49	Improved section Reat Time Clock in User Guide document	2024-08-26 18:22:30 +10:00
Wayne Warthen	df0562bba8	Bump Build Version Number	2024-08-23 09:49:48 -07:00
Wayne Warthen	eaf0431b20	Merge pull request #409 from lesbird/master Adding in Heathkit H8 support	2024-08-23 09:33:25 -07:00
Les Bird	6394605a20	Some minor formatting changes for Heathkit related HBIOS code. Add a script to build a CF image with MSX ROMs which includes CPM22,ZSDOS and CPM3	2024-08-22 09:48:44 -06:00
Les Bird	17f1d1cb99	Merge branch 'master' of https://github.com/lesbird/RomWBW	2024-08-21 15:08:46 -06:00
Les Bird	03e34a54d4	Add Heathkit H8 support. Front panel generates interrupts at 500Hz to update the LEDs and read the front panel keypad.	2024-08-21 15:04:17 -06:00
Wayne Warthen	797ee4d1a4	Update Makefile - Missed a file.	2024-08-21 13:17:37 -07:00
Wayne Warthen	f775a07365	Add MSXROMs - Les Bird has given permission to include his extensive library of MSX ROM images. Please see https://github.com/lesbird/MSX8 for more information. - Appropriate MSX8 ROM player and hardware required to use these. - Provided as supplemental RomWBW disk image slices (msxroms1.img, msxroms2.img). Co-Authored-By: Les Bird <lesbird65@gmail.com>	2024-08-21 12:18:58 -07:00
Wayne Warthen	e6117e9639	Refactor Build Post-processing - Post-processing of disk-hosted ROMs such as FZ80 and ZRC has been modified to handle custom user configurations. - Standardized all distribution ROM names to end in _std.	2024-08-19 14:53:11 -07:00
Wayne Warthen	9df87738ad	Fix FZ80 Makefile (Issue #407 ) - FZ80 Makefile failed to handle individual ROM build scenario. Credit and thanks to Mark Pruden for this. - Updated SIMH emulator to v4.1	2024-08-18 19:31:06 -07:00
Wayne Warthen	ebfb5b3fed	Bump Version Number	2024-08-18 12:43:22 -07:00
Wayne Warthen	f125efcca3	Customize NZ-COM Disk Image - Substantial customization of NZ-COM Disk Image	2024-08-18 11:33:10 -07:00
Wayne Warthen	317ba99b37	Update ReadMe.txt Windows marks files downloaded from the Internet and may prompt you during the RomWBW build process with repeated security warnings. Added instructions for "unblocking" distribution files when using the Windows build. Credit and Thanks to Derek for this tip. Co-Authored-By: Extreme Electronics <102665314+extremeelectronics@users.noreply.github.com>	2024-08-17 13:57:36 -07:00
Wayne Warthen	add41fdb69	SD Driver Bug Fix - Fixes a stupid bug I introduced in the previous change to sd.asm. SD Card initialization could hang in previous release.	2024-08-16 18:13:22 -07:00
Wayne Warthen	457aa44832	SD Card Compatibility Improvement - Modified SD driver to keep SD card clock consistently fast after card init. This only seemed to effect a Lexar 32GB uSD Card on CSIO interface. Thanks and credit to Richard Deane for reporting this. - Improved hard disk layout documentation.	2024-08-16 14:06:36 -07:00
Wayne Warthen	7e2b2b8f40	Implement SIOINTS Setting in SIO Driver - SIOINTS allows disabling use of interrupts in the SIO driver when interrupts are enabled globally. It will not allow you to enable SIO interrupts if interrupts are globally disabled (INTMODE 0).	2024-08-04 13:39:44 -07:00
Wayne Warthen	e68cbded97	SD Card Speed Improvement for FZ80 - Removed wait routines for FZ80 in SD driver. Latest FPGA code does not require them. - Minor improvements to disk layout documentation.	2024-08-04 12:12:16 -07:00
Wayne Warthen	cd70a62d67	Documentation Updates - Minor improvements to hard disk documentation in System Guide.	2024-08-01 11:40:23 -07:00
Wayne Warthen	307b8bb11b	Add Tick Counter Size - Documents the date field size of the tick counter.	2024-07-31 14:53:58 -07:00
Wayne Warthen	fd59d2e4f8	Add UMAP - UMAP application has been added to the ZPM3 and NZCOM disk images.	2024-07-30 11:06:25 -07:00
Wayne Warthen	e021735876	More Enhancements to Startup Command Documentation	2024-07-28 13:31:06 -07:00
Wayne Warthen	91debe53c4	Improve Startup Commands Documentation	2024-07-28 12:08:35 -07:00
Wayne Warthen	8e0af1720a	Application Boot Tweaks - Reduces failure scenarios with application boot - Catches and diagnoses common bank mismatch which application boot cannot handle	2024-07-27 15:17:58 -07:00
Wayne Warthen	83d26a4faf	- Improve PPIDE Device Detection - Some PPI chips were falsely detecting the presence of an IDE device. Added code to preset PPI register with a value that avoids false positives.	2024-07-26 09:38:24 -07:00
Wayne Warthen	c2f7a75cdd	Add hour/minute/second display to TIMER app (MartinR) Co-Authored-By: MartinR <174514335+MartinR-UK@users.noreply.github.com>	2024-07-24 11:24:41 -07:00
Wayne Warthen	888706149d	Improve Application Start Mode - If the new AUX bank happens to be the same as the old HBIOS bank, an application start would fail. Relocated the copy to avoid this.	2024-07-22 16:40:53 -07:00
Wayne Warthen	a078820745	Fix Duodyne MMU Regression	2024-07-21 16:40:59 -07:00
Wayne Warthen	21df9d8797	Missing Files	2024-07-20 17:27:59 -07:00
Wayne Warthen	cd23863226	Refactor UART Mode Settings - Replaced hard-coded mode settings with per-chip configuration settings.	2024-07-20 15:20:05 -07:00