Merge pull request #647 from b3rendsh/master

Update loader for MSX

.github/pull_request_template.md

@@ -4,6 +4,7 @@ BEFORE YOU CREATE A PULL REQUEST:
 - Please base all pull requests against the master branch
 - Include a clear description of your change
 - Reference related Issue(s) (e.g., "Resolves Issue #123")
+- Indicate whether an AI LLM was utilized
 
 Thank you for contributing to RomWBW!  I will review your pull request as soon as possible.
 

CONTRIBUTING.md

@@ -1,42 +1,91 @@
 # Contributing to RomWBW
 
-> **WARNING**: The `dev` branch of RomWBW has been deprecated as of v3.4.  All Pull Requests should now target the `master` branch.
+> **WARNING**: The `dev` branch of RomWBW has been deprecated as of
+  v3.4.  All Pull Requests should now target the `master` branch.
 
-Contributions of all kinds to RomWBW are welcomed and greatly appreciated.
+Contributions of all kinds to RomWBW are welcomed and greatly
+appreciated.
 
 - Reporting bug(s) and suggesting new feature(s)
 - Discussing the current state of the code
-- Submitting a fixes and enhancements
+- Submitting fixes and enhancements
 
 ## RomWBW GitHub Repository
 
-The [RomWBW GitHub Repository](https://github.com/wwarthen/RomWBW) is the primary location for developing, supporting, and distributing RomWBW.  Although input is gladly accepted from almost any channel, the GitHub Repository is preferred.
+The [RomWBW GitHub Repository](https://github.com/wwarthen/RomWBW) is
+the primary location for developing, supporting, and distributing
+RomWBW.  Although input is gladly accepted from almost any channel, the
+GitHub Repository is preferred.
 
-- Use **Issues** to report bugs, request enhancements, or ask usage questions.
+- Use **Issues** to report bugs, request enhancements, or ask usage
+  questions
 - Use **Discussions** to interact with others
 - Use **Pull Requests** to submit content (code, documentation, etc.)
 
 ## Submitting Content
 
-This RomWBW Project uses the standard [GitHub Flow](https://docs.github.com/en/get-started/quickstart/github-flow).  Submission of content changes (including code) are ideally done via Pull Requests.
+This RomWBW Project uses the standard
+[GitHub Flow](https://docs.github.com/en/get-started/quickstart/github-flow).
+Submission of content changes (including code) are ideally done via Pull
+Requests.
 
-- Submitters are advised to contact [Wayne Warthen](mailto:wwarthen@gmail.com) or start a GitHub Discussion prior to starting any significant work.  This is simply to ensure that submissions are consistent
-  with the overall goals and intentions of RomWBW.
-- All submissions should be based on the `master` branch.  To create your submission, fork the RomWBW repository and create your branch from `master`.  Make (and test) your changes in your personal fork.
-- Please update relevant documentation and the `ChangeLog` found in the `Doc` folder.
-- You are encouraged to comment your submissions to ensure your work is properly attributed.
-- When ready, submit a Pull Request to merge your forked branch into the RomWBW master branch.
+- Submitters are advised to contact [Wayne Warthen](mailto:wwarthen@
+  gmail.com) or start a GitHub Discussion prior to starting any
+  significant work.  This is simply to ensure that submissions are
+  consistent   with the overall goals and intentions of RomWBW.
+- All submissions should be based on the `master` branch.  To create
+  your submission, fork the RomWBW repository and create your branch from
+  `master`.  Make (and test) your changes in your personal fork.
+- Please update relevant documentation and the `ChangeLog` found in the
+  `Doc` folder.
+- You are encouraged to comment your submissions to ensure your work is
+  properly attributed.
+- When ready, submit a Pull Request to merge your forked branch into the
+  RomWBW master branch.  In the comments, be sure to indicate if an
+  AI LLM was utilized in any way.
 
 ## Coding Style
 
-Due to the nature of the project, you will find a variety of coding styles.  When making changes to existing code, please try to be consistent with the existing coding style.  You may not like the current style, but no one likes mixed styles
-in one file/module.
+Due to the nature of the project, you will find a variety of coding
+styles.  When making changes to existing code, please try to be
+consistent with the existing coding style.  You may not like the current
+style, but no one likes mixed styles in one file/module.
 
-Be careful with white space.  RomWBW is primarily assembly langauge code.  The use of tab stops at every 8 characters is pretty standard for assembler.  If you use something else, then your code will look odd when viewed by others.
+Be careful with white space.  RomWBW is primarily assembly langauge
+code.  The use of tab stops at every 8 characters is pretty standard for
+assembler.  If you use something else, then your code will look odd
+when viewed by others.
 
-In most cases, the use of `<cr><lf>` line endings is preferred.  This is standard for the operating systems of the era that RomWBW provides.  Also note that CP/M text files should end with a ctrl-Z (0x1A).  This is not magically added by the
-tools that generate the disk images.
+In most cases, the use of `<cr><lf>` line endings is preferred.  This is
+standard for the operating systems of the era that RomWBW provides.
+Also note that CP/M text files should end with a ctrl-Z (0x1A).  This is
+not magically added by the tools that generate the disk images.
+
+## Hints for Developers
+
+- The majority of RomWBW is assembled with TASM (and it's compatible
+  equivalent sz80as).  These tools have quirks that are very subtle.  For
+  example, TASM does not evaluate expressions in the standard way.  It
+  uses a left to right approach.  Check the TASM documentation carefully.
+
+- The following two Z80 instructions highlight a common issue with the
+  Z80 assembler syntax.  Parens in operands frequently indicate an
+  indirect reference.  To treat the operand as an expression, use the
+  second format.
+
+```
+	LD	A,(5+5)		; Load A with the value at address 10
+	LD	A,0+(5+5)	; Load A with the value 10
+```
+
+- The RomWBW documewntation in the Doc directory is generated with a
+  process outside of the normal build process.  To update documentation,
+  please update the .md files in Source/Doc.  Those are the Markdown
+  source files for the documentation.  The PDF files will be updated
+  offline from those.
 
 ## License
 
-RomWBW is licensed under GPLv3.  When you submit code changes, your submissions are understood to be under the same [GPLv3 License](https://www.gnu.org/licenses/gpl-3.0.html) that covers the project.
+RomWBW is licensed under GPLv3.  When you submit code changes, your
+submissions are understood to be under the same [GPLv3 License]
+(https://www.gnu.org/licenses/gpl-3.0.html) that covers the project.

Doc/ChangeLog.txt

@@ -34,6 +34,12 @@ Version 3.6
 - HJB: Added IDE driver master media detect option
 - WBW: Add support for S100 Serial I/O DLP Serial connection
 - P?D: Generate compressed ROM for EaZyZ80 512
+- DDW: Added support for the 'N8PC' platform. Includes support for the M6242 RTC chip
+- JMD: Added VGMINFO application
+- WBW: Created SCSI Driver derived from code from Jay Cotton
+- WBW: Add official RC2014 platform (derived from RCZ80)
+- D?N: Added improved TMS Driver hardware/configuration detection and reporting
+- WBW: Removed driver module INIT lists, replaced with init phase system
 
 Version 3.5.1
 -------------

ReadMe.md

@@ -7,7 +7,7 @@
 **RomWBW Introduction** \
 Version 3.6 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-15 Oct 2025
+06 Jan 2026
 
 # Overview
 
@@ -363,6 +363,9 @@ let me know if I missed you!
 
 - Henk Berends added support for the MSX platform.
 
+- Jay Cotton provided the SCSI transport code upon which the SCSI driver
+  is based.
+
 ## Related Projects
 
 Outside of the hardware platforms adapted to RomWBW, there are a variety

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW Introduction
 Wayne Warthen (wwarthen@gmail.com)
-15 Oct 2025
+06 Jan 2026
 
 
 
@@ -370,6 +370,9 @@ let me know if I missed you!
 
 - Henk Berends added support for the MSX platform.
 
+- Jay Cotton provided the SCSI transport code upon which the SCSI driver
+  is based.
+
 
 Related Projects
 

Source/Apps/Test/ps2info/ps2info.asm

@@ -12,6 +12,7 @@
 ; WBW 2022-04-02: Fix prtchr register saving/recovery
 ; WBW 2023-10-19: Add support for Duodyne
 ; WBW 2024-06-10: Add support for RC2014
+; WBW 2025-12-04: Add support for S100 MS-DOS Support Board
 ;
 ;=======================================================================
 ;
@@ -29,6 +30,9 @@ iodat_duo	.equ	$4C	; PS/2 controller data port address
 ; RC2014 (EP/Sally)
 iocmd_rc	.equ	$64	; PS/2 controller command port address
 iodat_rc	.equ	$60	; PS/2 controller data port address
+; S100 MS-DOS Support Board
+iocmd_s100	.equ	$64	; PS/2 controller command port address
+iodat_s100	.equ	$60	; PS/2 controller data port address
 
 ;
 cpumhz	.equ	8	; for time delay calculations (not critical)
@@ -94,6 +98,8 @@ setup1:
 	jr	z,setup_duo
 	cp	'4'			; RC2014 EP/Sally
 	jr	z,setup_rc
+	cp	'5'			; S100
+	jr	z,setup_s100
 	cp	'X'
 	jr	z,exit
 	jr	setup
@@ -130,6 +136,14 @@ setup_rc:
 	ld	de,str_rc
 	jr	setup2
 ;
+setup_s100:
+	ld	a,iocmd_s100
+	ld	(iocmd),a
+	ld	a,iodat_s100
+	ld	(iodat),a
+	ld	de,str_s100
+	jr	setup2
+;
 setup2:
 	call	prtstr
 	call	crlf2
@@ -1452,18 +1466,20 @@ delay1:
 ; Constants
 ;=======================================================================
 ;
-str_banner		.db	"PS/2 Keyboard/Mouse Information v0.9, 10-Jun-2024",0
+str_banner		.db	"PS/2 Keyboard/Mouse Information v1.0, 4-Dec-2025",0
 str_hwmenu		.db	"PS/2 Controller Port Options:\r\n\r\n"
 			.db	"  1 - Nhyodyne\r\n"
 			.db	"  2 - Rhyophyre\r\n"
 			.db	"  3 - Duodyne\r\n"
 			.db	"  4 - RC2014\r\n"
+			.db	"  5 - S100 MS-DOS Support Board\r\n"
 			.db	"  X - Exit Application\r\n"
 			.db	"\r\nSelection? ",0
 str_mbc			.db	"Nhyodyne",0
 str_rph			.db	"Rhyophyre",0
 str_duo			.db	"Duodyne",0
 str_rc			.db	"RC2014 (Saly)",0
+str_s100		.db	"S100 (MS-DOS Support Board)",0
 str_menu		.db	"PS/2 Testing Options:\r\n\r\n"
 			.db	"  C - Test PS/2 Controller\r\n"
 			.db	"  K - Test PS/2 Keyboard\r\n"

Source/Apps/VGM/Build.cmd

@@ -7,6 +7,8 @@ set TASMTABS=%TOOLS%\tasm32
 
 tasm -t80 -g3 -fFF -dWBW vgmplay.asm vgmplay.com vgmplay.lst || exit /b
 tasm -t80 -g3 -fFF -dWBW ymfmdemo.asm ymfmdemo.com ymfmdemo.lst || exit /b
+tasm -t80 -g3 -fFF -dWBW vgminfo.asm vgminfo.com vgminfo.lst || exit /b
 
 copy /Y vgmplay.com ..\..\..\Binary\Apps\ || exit /b
+copy /Y vgminfo.com ..\..\..\Binary\Apps\ || exit /b
 copy /Y Tunes\*.vgm ..\..\..\Binary\Apps\Tunes\ || exit /b

Source/Apps/VGM/Makefile

@@ -1,4 +1,4 @@
-OBJECTS = vgmplay.com
+OBJECTS = vgmplay.com vgminfo.com
 DEST = ../../../Binary/Apps
 TOOLS = ../../../Tools
 OTHERS = *.LST
@@ -13,6 +13,9 @@ vgmplay.com: $(DEPS)
 ym2612.com: 
 	$(TASM) -dWBW ymfmdemo.asm ymfmdemo.com ymfmdemo.lst
 
+vgminfo.com: 
+	$(TASM) -dWBW vgminfo.asm vgminfo.com vgminfo.lst
+
 all::
 	mkdir -p $(DEST)/Tunes
 	cp Tunes/*.vgm $(DEST)/Tunes

Source/Apps/VGM/vgminfo.asm

@@ -0,0 +1,854 @@
+;------------------------------------------------------------------------------
+; VGM File Info Display for CP/M
+;------------------------------------------------------------------------------
+;
+; Scans all .VGM files in current directory and displays chip information
+; in a formatted table
+;
+; (c) 2025 Joao Miguel Duraes
+; Licensed under the MIT License
+;
+; Version: 1.1 - 06-Dec-2025
+;
+; Assemble with:
+;   TASM -80 -b vgminfo.asm vgminfo.com
+;
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+; CP/M definitions
+;------------------------------------------------------------------------------
+
+BOOT            .equ    0000H               ; boot location
+BDOS            .equ    0005H               ; bdos entry point
+FCB             .equ    005CH               ; file control block
+FCBCR           .equ    FCB + 20H           ; fcb current record
+BUFF            .equ    0080H               ; DMA buffer
+
+PRINTF          .equ    9                   ; BDOS print string function
+OPENF           .equ    15                  ; BDOS open file function
+CLOSEF          .equ    16                  ; BDOS close file function
+READF           .equ    20                  ; BDOS sequential read function
+SETDMA          .equ    26                  ; BDOS set DMA address
+SFIRST          .equ    17                  ; BDOS search first
+SNEXT           .equ    18                  ; BDOS search next
+
+CR              .equ    0DH                 ; carriage return
+LF              .equ    0AH                 ; line feed
+
+;------------------------------------------------------------------------------
+; VGM Header offsets
+;------------------------------------------------------------------------------
+
+DEBUG_SUM       .equ    1                   ; 1 = build with checksum support
+
+VGM_IDENT       .equ    00H                 ; "Vgm " identifier
+VGM_VERSION     .equ    08H                 ; Version
+VGM_SN76489_CLK .equ    0CH                 ; SN76489 clock (4 bytes, little-endian)
+VGM_YM2612_CLK  .equ    2CH                 ; YM2612 clock (4 bytes, little-endian)
+VGM_YM2151_CLK  .equ    30H                 ; YM2151 clock (4 bytes, little-endian)
+VGM_DATAOFF     .equ    34H                 ; VGM data offset (relative to 0x34)
+VGM_AY8910_CLK  .equ    74H                 ; AY-3-8910 clock (4 bytes, little-endian)
+
+;------------------------------------------------------------------------------
+; VGM Command codes (subset)
+;------------------------------------------------------------------------------
+
+VGM_PSG1_W      .equ    050H                ; PSG (SN76489) write
+VGM_PSG2_W      .equ    030H                ; PSG #2 write
+VGM_YM26121_W   .equ    052H                ; YM2612 port 0 write
+VGM_YM26122_W   .equ    053H                ; YM2612 port 1 write
+VGM_YM26123_W   .equ    0A2H                ; YM2612 #2 port 0 write
+VGM_YM26124_W   .equ    0A3H                ; YM2612 #2 port 1 write
+VGM_YM21511_W   .equ    054H                ; YM2151 write
+VGM_YM21512_W   .equ    0A4H                ; YM2151 #2 write
+VGM_OPL2_W      .equ    05AH                ; YM3812 (OPL2) write
+VGM_OPL31_W     .equ    05EH                ; YMF262 (OPL3) port 0 write
+VGM_OPL32_W     .equ    05FH                ; YMF262 (OPL3) port 1 write
+VGM_AY_W        .equ    0A0H                ; AY-3-8910 write
+VGM_ESD         .equ    066H                ; End of sound data
+VGM_WNS         .equ    061H                ; Wait n samples
+VGM_W735        .equ    062H                ; Wait 735 samples
+VGM_W882        .equ    063H                ; Wait 882 samples
+
+;------------------------------------------------------------------------------
+; Program Start
+;------------------------------------------------------------------------------
+
+                .ORG    100H
+
+START:          LD      SP, STACK           ; Setup stack
+                
+                ; Parse command tail for debug flags (e.g. "D" or "/D")
+                CALL    PARSE_DEBUG
+                
+                ; Display header
+                LD      DE, MSG_HEADER
+                CALL    PRTSTR
+                LD      DE, MSG_DIVIDER
+                CALL    PRTSTR
+
+                ; Setup search for *.VGM files
+                LD      DE, SEARCH_FCB
+                LD      C, SFIRST
+                CALL    BDOS
+                CP      0FFH                ; No files found?
+                JP      Z, NO_FILES
+
+FILE_LOOP:      
+                ; A contains directory entry index (0-3)
+                ; Each entry is 32 bytes, so multiply by 32
+                AND     03H                 ; Mask to 0-3
+                RLCA
+                RLCA
+                RLCA
+                RLCA
+                RLCA                        ; Multiply by 32
+                LD      L, A
+                LD      H, 0
+                LD      DE, BUFF
+                ADD     HL, DE              ; HL now points to directory entry
+                
+                ; Copy filename from directory entry to our FCB
+                INC     HL                  ; Skip user number
+                LD      DE, FILE_FCB+1      ; Destination
+                LD      BC, 11              ; 8+3 filename
+                LDIR
+                
+                ; Open and process this file
+                CALL    PROCESS_FILE
+                
+                ; Search for next file
+                LD      DE, SEARCH_FCB
+                LD      C, SNEXT
+                CALL    BDOS
+                CP      0FFH
+                JP      NZ, FILE_LOOP
+
+                ; Done
+                LD      DE, MSG_DIVIDER
+                CALL    PRTSTR
+                JP      BOOT                ; Exit to CP/M
+
+NO_FILES:       LD      DE, MSG_NOFILES
+                CALL    PRTSTR
+                JP      BOOT
+
+;------------------------------------------------------------------------------
+; Process a VGM file - read header and display info
+;------------------------------------------------------------------------------
+
+PROCESS_FILE:   
+                ; Reset FCB
+                XOR     A
+                LD      (FILE_FCB), A       ; Default drive
+                LD      (FILE_FCB+12), A    ; Clear extent
+                LD      (FILE_FCB+32), A    ; Clear current record
+                
+                ; Open file
+                LD      DE, FILE_FCB
+                LD      C, OPENF
+                CALL    BDOS
+                CP      0FFH
+                RET     Z                   ; Can't open, skip
+                
+                ; Set DMA to our buffer for first block
+                LD      DE, VGMBUF
+                LD      C, SETDMA
+                CALL    BDOS
+                
+                ; Read first 128 bytes (header)
+                LD      DE, FILE_FCB
+                LD      C, READF
+                CALL    BDOS
+                OR      A
+                JR      NZ, READ_DONE       ; EOF or error
+                
+                ; Read second 128 bytes (to allow scanning right after header)
+                LD      DE, VGMBUF+128
+                LD      C, SETDMA
+                CALL    BDOS
+                LD      DE, FILE_FCB
+                LD      C, READF
+                CALL    BDOS
+                
+                ; Read third 128 bytes
+                LD      DE, VGMBUF+256
+                LD      C, SETDMA
+                CALL    BDOS
+                LD      DE, FILE_FCB
+                LD      C, READF
+                CALL    BDOS
+                
+                ; Read fourth 128 bytes
+                LD      DE, VGMBUF+384
+                LD      C, SETDMA
+                CALL    BDOS
+                LD      DE, FILE_FCB
+                LD      C, READF
+                CALL    BDOS
+                
+READ_DONE:
+                
+                ; Restore DMA
+                LD      DE, BUFF
+                LD      C, SETDMA
+                CALL    BDOS
+                
+                ; Close file
+                LD      DE, FILE_FCB
+                LD      C, CLOSEF
+                CALL    BDOS
+                
+                ; Check if valid VGM
+                LD      HL, VGMBUF
+                LD      A, (HL)
+                CP      'V'
+                RET     NZ
+                INC     HL
+                LD      A, (HL)
+                CP      'g'
+                RET     NZ
+                INC     HL
+                LD      A, (HL)
+                CP      'm'
+                RET     NZ
+                INC     HL
+                LD      A, (HL)
+                CP      ' '
+                RET     NZ
+                
+                ; Display filename (exactly 8 chars from FCB)
+                LD      HL, FILE_FCB+1
+                LD      B, 8
+PRINT_NAME:     LD      A, (HL)
+                CALL    PRTCHR
+                INC     HL
+                DJNZ    PRINT_NAME
+                
+                ; Add 2-space gap
+                LD      A, ' '
+                CALL    PRTCHR
+                LD      A, ' '
+                CALL    PRTCHR
+
+#if DEBUG_SUM
+                ; Compute and optionally print 512-byte checksum over VGMBUF
+                CALL    CALC_SUM512
+                LD      A, (DBG_SUM)
+                OR      A
+                JR      Z, PAD_DONE
+
+                ; Print space + [HHLL] + space between filename and chips
+                LD      A, ' '
+                CALL    PRTCHR
+                LD      A, '['
+                CALL    PRTCHR
+                LD      A, (SUM_HI)
+                CALL    PRTHEX8
+                LD      A, (SUM_LO)
+                CALL    PRTHEX8
+                LD      A, ']'
+                CALL    PRTCHR
+                LD      A, ' '
+                CALL    PRTCHR
+#endif
+
+PAD_DONE:
+                
+                ; Check and display chip info
+                CALL    CHECK_CHIPS
+                
+                ; New line
+                CALL    CRLF
+                
+                RET
+
+;------------------------------------------------------------------------------
+; Check which chips are used: hybrid approach
+; 1. Check header clocks to see which chip types are present
+; 2. Scan commands to detect multiple instances of same chip type
+;------------------------------------------------------------------------------
+
+CHECK_CHIPS:    
+                ; Initialize chip flags
+                XOR     A
+                LD      (CHIP_FLAGS), A
+                LD      (CHIP_TYPES), A         ; Types present from header
+                
+                ; Check SN76489 clock (4 bytes at 0x0C)
+                LD      HL, VGMBUF+VGM_SN76489_CLK
+                LD      A, (HL)
+                INC     HL
+                OR      (HL)
+                INC     HL
+                OR      (HL)
+                INC     HL
+                OR      (HL)
+                JR      Z, CHK_YM2612_CLK
+                LD      A, (CHIP_TYPES)
+                OR      01H                     ; bit 0 = SN76489 present
+                LD      (CHIP_TYPES), A
+                
+CHK_YM2612_CLK:
+                ; Check YM2612 clock (4 bytes at 0x2C)
+                LD      HL, VGMBUF+VGM_YM2612_CLK
+                LD      A, (HL)
+                INC     HL
+                OR      (HL)
+                INC     HL
+                OR      (HL)
+                INC     HL
+                OR      (HL)
+                JR      Z, CHK_YM2151_CLK
+                LD      A, (CHIP_TYPES)
+                OR      02H                     ; bit 1 = YM2612 present
+                LD      (CHIP_TYPES), A
+                
+CHK_YM2151_CLK:
+                ; Check YM2151 clock (4 bytes at 0x30)
+                LD      HL, VGMBUF+VGM_YM2151_CLK
+                LD      A, (HL)
+                INC     HL
+                OR      (HL)
+                INC     HL
+                OR      (HL)
+                INC     HL
+                OR      (HL)
+                JR      Z, CHK_AY_CLK
+                LD      A, (CHIP_TYPES)
+                OR      04H                     ; bit 2 = YM2151 present
+                LD      (CHIP_TYPES), A
+                
+CHK_AY_CLK:
+                ; Check AY-3-8910 clock (4 bytes at 0x74, only valid in VGM v1.51+)
+                LD      HL, VGMBUF+VGM_VERSION
+                LD      A, (HL)                 ; Get low byte of version
+                CP      51H                     ; Check if >= 0x51 (v1.51)
+                JR      C, START_CMD_SCAN       ; Skip if < v1.51
+                INC     HL
+                LD      A, (HL)                 ; Get high byte
+                CP      01H                     ; Must be 0x01
+                JR      NZ, START_CMD_SCAN      ; Skip if not v1.xx
+                
+                LD      HL, VGMBUF+VGM_AY8910_CLK
+                LD      A, (HL)
+                INC     HL
+                OR      (HL)
+                INC     HL
+                OR      (HL)
+                INC     HL
+                OR      (HL)
+                JR      Z, START_CMD_SCAN
+                LD      A, (CHIP_TYPES)
+                OR      08H                     ; bit 3 = AY present
+                LD      (CHIP_TYPES), A
+                
+START_CMD_SCAN:
+                ; Clear AY flags if AY is not present in header
+                LD      A, (CHIP_TYPES)
+                BIT     3, A                      ; Check if AY is present
+                JR      NZ, SCAN_CMDS            ; If present, continue
+                LD      A, (CHIP_FLAGS)
+                AND     3FH                       ; Clear bits 6 and 7 (AY flags)
+                LD      (CHIP_FLAGS), A
+SCAN_CMDS:
+                ; If chip type is present, scan commands to detect multiples
+                ; Set base flags from types
+                LD      A, (CHIP_TYPES)
+                BIT     0, A
+                JR      Z, NO_SN_BASE
+                LD      A, (CHIP_FLAGS)
+                OR      01H                     ; Set SN #1
+                LD      (CHIP_FLAGS), A
+NO_SN_BASE:
+                LD      A, (CHIP_TYPES)
+                BIT     1, A
+                JR      Z, NO_YM2612_BASE
+                LD      A, (CHIP_FLAGS)
+                OR      04H                     ; Set YM2612 #1
+                LD      (CHIP_FLAGS), A
+NO_YM2612_BASE:
+                LD      A, (CHIP_TYPES)
+                BIT     2, A
+                JR      Z, NO_YM2151_BASE
+                ; Do NOT pre-mark YM2151 as used from the header alone.
+                ; YM2151 will only be marked used when a command is seen.
+NO_YM2151_BASE:
+                ; Do NOT pre-mark AY as used from the header alone.
+                ; AY will only be marked used when an 0xA0 command is seen.
+NO_AY_BASE:
+
+COMPUTE_DATA_START:
+                LD      HL, (VGMBUF+VGM_DATAOFF)
+                LD      A, H
+                OR      L
+                JR      NZ, GOT_OFFSET
+                LD      HL, 000CH           ; Default for VGM < 1.50 (0x40-0x34)
+GOT_OFFSET:     LD      DE, VGMBUF+VGM_DATAOFF
+                ADD     HL, DE              ; HL = VGMBUF + 0x34 + offset
+                
+                ; Constrain to our 256-byte buffer
+                LD      DE, VGMBUF
+                SBC     HL, DE              ; HL = offset from VGMBUF base
+                ADD     HL, DE              ; restore HL absolute inside VGMBUF
+                
+                ; Scan up to 255 commands or until EOD
+                LD      C, 255
+SCAN_LOOP:      LD      A, (HL)
+                INC     HL
+                
+                CP      VGM_ESD
+                JP      Z, SCAN_DONE
+                
+                CP      VGM_PSG1_W
+                JP      NZ, CHK_PSG2
+                LD      A, (CHIP_FLAGS)
+                OR      01H                 ; bit 0 = SN #1
+                LD      (CHIP_FLAGS), A
+                INC     HL                  ; Skip data byte
+                JP      SCAN_NEXT
+                
+CHK_PSG2:       CP      VGM_PSG2_W
+                JP      NZ, CHK_YM2612
+                LD      A, (CHIP_TYPES)     ; Only if SN76489 is present
+                BIT     0, A
+                JR      Z, SCAN_NEXT_1
+                LD      A, (CHIP_FLAGS)
+                OR      02H                 ; bit 1 = SN #2
+                LD      (CHIP_FLAGS), A
+SCAN_NEXT_1:    INC     HL
+                JP      SCAN_NEXT
+                
+CHK_YM2612:     CP      VGM_YM26121_W
+                JR      Z, GOT_YM2612_1
+                CP      VGM_YM26122_W
+                JR      Z, GOT_YM2612_1
+                CP      VGM_YM26123_W
+                JR      Z, GOT_YM2612_2
+                CP      VGM_YM26124_W
+                JP      NZ, CHK_YM2151
+GOT_YM2612_2:   LD      A, (CHIP_TYPES)     ; Only if YM2612 is present
+                BIT     1, A
+                JR      Z, SCAN_NEXT_2
+                LD      A, (CHIP_FLAGS)
+                OR      08H                 ; bit 3 = YM2612 #2
+                LD      (CHIP_FLAGS), A
+SCAN_NEXT_2:    INC     HL
+                INC     HL                  ; Skip 2 data bytes
+                JP      SCAN_NEXT
+GOT_YM2612_1:   LD      A, (CHIP_FLAGS)
+                OR      04H                 ; bit 2 = YM2612 #1
+                LD      (CHIP_FLAGS), A
+                INC     HL
+                INC     HL
+                JP      SCAN_NEXT
+                
+CHK_YM2151:     CP      VGM_YM21511_W
+                JR      Z, GOT_YM2151_1
+                CP      VGM_YM21512_W
+                JP      NZ, CHK_AY
+                LD      A, (CHIP_TYPES)     ; Only if YM2151 is present
+                BIT     2, A
+                JR      Z, SCAN_NEXT_3
+                LD      A, (CHIP_FLAGS)
+                OR      20H                 ; bit 5 = YM2151 #2
+                LD      (CHIP_FLAGS), A
+SCAN_NEXT_3:    INC     HL
+                INC     HL
+                JP      SCAN_NEXT
+GOT_YM2151_1:   LD      A, (CHIP_FLAGS)
+                OR      10H                 ; bit 4 = YM2151 #1
+                LD      (CHIP_FLAGS), A
+                INC     HL
+                INC     HL
+                JP      SCAN_NEXT
+                
+CHK_AY:         CP      VGM_AY_W
+                JP      NZ, CHK_OPL2
+                LD      A, (CHIP_TYPES)     ; Only if AY is present
+                BIT     3, A
+                JR      Z, SCAN_SKIP_AY     ; Skip if AY not present in header
+                LD      A, (HL)             ; Get register/chip byte
+                BIT     7, A                ; Bit 7 = chip 2?
+                JR      Z, GOT_AY1
+                LD      A, (CHIP_FLAGS)
+                OR      80H                 ; bit 7 = AY #2
+                LD      (CHIP_FLAGS), A
+                JR      SCAN_SKIP_AY
+GOT_AY1:        LD      A, (CHIP_FLAGS)
+                OR      40H                 ; bit 6 = AY #1
+                LD      (CHIP_FLAGS), A
+SCAN_SKIP_AY:    INC     HL
+                INC     HL                  ; Skip 2 data bytes
+                JP      SCAN_NEXT
+                
+CHK_OPL2:       CP      VGM_OPL2_W
+                JP      NZ, CHK_OPL3
+                ; Mark OPL2 present
+                LD      A, (CHIP_TYPES)
+                OR      010H                 ; bit 4 = OPL2
+                LD      (CHIP_TYPES), A
+                INC     HL                   ; skip register
+                INC     HL                   ; skip data
+                JP      SCAN_NEXT
+                
+CHK_OPL3:       CP      VGM_OPL31_W
+                JR      Z, GOT_OPL3
+                CP      VGM_OPL32_W
+                JP      NZ, CHK_WAIT
+GOT_OPL3:       ; Mark OPL3 present
+                LD      A, (CHIP_TYPES)
+                OR      020H                 ; bit 5 = OPL3
+                LD      (CHIP_TYPES), A
+                INC     HL                   ; skip register
+                INC     HL                   ; skip data
+                JP      SCAN_NEXT
+                
+CHK_WAIT:       CP      VGM_WNS
+                JR      NZ, CHK_W735
+                INC     HL
+                INC     HL                  ; Skip 2-byte wait value
+                JP      SCAN_NEXT
+                
+CHK_W735:       CP      VGM_W735
+                JR      Z, SCAN_NEXT
+                CP      VGM_W882
+                JR      Z, SCAN_NEXT
+                
+                ; Unknown command or short wait 0x70-0x7F -> just continue
+                CP      70H
+                JR      C, SCAN_NEXT
+                CP      80H
+                JR      NC, SCAN_NEXT
+                
+SCAN_NEXT:      DEC     C
+                JP      NZ, SCAN_LOOP
+                
+SCAN_DONE:      ; Display chips found
+                LD      B, 0                ; Chip counter
+                LD      A, (CHIP_FLAGS)
+                LD      C, A                ; Save flags
+                
+                ; SN76489
+                AND     03H                 ; bits 0-1
+                JP      Z, NO_SN
+                LD      A, B
+                OR      A
+                CALL    NZ, PRINT_COMMA
+                LD      A, C
+                AND     03H
+                CP      03H                 ; Both chips?
+                JR      Z, SN_DUAL
+                LD      DE, MSG_SN76489
+                CALL    PRTSTR
+                JR      SN_DONE
+SN_DUAL:        LD      DE, MSG_SN76489X2
+                CALL    PRTSTR
+SN_DONE:        INC     B
+NO_SN:
+                ; YM2612
+                LD      A, C
+                AND     0CH                 ; bits 2-3
+                JR      Z, NO_YM2612
+                LD      A, B
+                OR      A
+                CALL    NZ, PRINT_COMMA
+                LD      A, C
+                AND     0CH
+                CP      0CH                 ; Both chips?
+                JR      Z, YM2612_DUAL
+                LD      DE, MSG_YM2612
+                CALL    PRTSTR
+                JR      YM2612_DONE
+YM2612_DUAL:    LD      DE, MSG_YM2612X2
+                CALL    PRTSTR
+YM2612_DONE:    INC     B
+NO_YM2612:
+                ; YM2151
+                LD      A, C
+                AND     30H                 ; bits 4-5
+                JR      Z, NO_YM2151
+                LD      A, B
+                OR      A
+                CALL    NZ, PRINT_COMMA
+                LD      A, C
+                AND     30H
+                CP      30H                 ; Both chips?
+                JR      Z, YM2151_DUAL
+                LD      DE, MSG_YM2151
+                CALL    PRTSTR
+                JR      YM2151_DONE
+YM2151_DUAL:    LD      DE, MSG_YM2151X2
+                CALL    PRTSTR
+YM2151_DONE:    INC     B
+NO_YM2151:
+                ; OPL2 (YM3812)
+                LD      A, (CHIP_TYPES)
+                BIT     4, A
+                JR      Z, NO_OPL2
+                LD      A, B
+                OR      A
+                CALL    NZ, PRINT_COMMA
+                LD      DE, MSG_OPL2
+                CALL    PRTSTR
+                INC     B
+NO_OPL2:
+                ; OPL3 (YMF262)
+                LD      A, (CHIP_TYPES)
+                BIT     5, A
+                JR      Z, NO_OPL3
+                LD      A, B
+                OR      A
+                CALL    NZ, PRINT_COMMA
+                LD      DE, MSG_OPL3
+                CALL    PRTSTR
+                INC     B
+NO_OPL3:
+                ; AY-3-8910
+                LD      A, C
+                AND     0C0H                ; bits 6-7
+                JR      Z, NO_AY
+                LD      A, B
+                OR      A
+                CALL    NZ, PRINT_COMMA
+                LD      A, C
+                AND     0C0H
+                CP      0C0H                ; Both chips?
+                JR      Z, AY_DUAL
+                LD      DE, MSG_AY8910
+                CALL    PRTSTR
+                JR      AY_DONE
+AY_DUAL:        LD      DE, MSG_AY8910X2
+                CALL    PRTSTR
+AY_DONE:        INC     B
+NO_AY:
+                ; None
+                LD      A, B
+                OR      A
+                RET     NZ
+                LD      DE, MSG_UNKNOWN
+                CALL    PRTSTR
+                RET
+
+PRINT_COMMA:    LD      A, ','
+                CALL    PRTCHR
+                LD      A, ' '
+                CALL    PRTCHR
+                RET
+
+
+;------------------------------------------------------------------------------
+; Parse CP/M command tail for debug flag (D or /D) -> sets DBG_SUM
+;------------------------------------------------------------------------------
+
+PARSE_DEBUG:    LD      HL, BUFF            ; CP/M command tail buffer
+                LD      A, (HL)             ; length byte
+                OR      A
+                RET     Z                   ; empty tail, no flags
+
+                LD      B, A                ; B = remaining chars
+                INC     HL                  ; HL -> first character
+
+PD_LOOP:        LD      A, (HL)
+                CP      ' '                 ; skip spaces
+                JR      Z, PD_NEXT
+
+                CP      '/'
+                JR      Z, PD_SLASH
+
+                CP      'D'
+                JR      Z, PD_SET
+                CP      'd'
+                JR      Z, PD_SET
+                JR      PD_NEXT
+
+PD_SLASH:       ; look at next char for D/d
+                INC     HL
+                DJNZ    PD_CHECK2
+                RET
+
+PD_CHECK2:      LD      A, (HL)
+                CP      'D'
+                JR      Z, PD_SET
+                CP      'd'
+                JR      Z, PD_SET
+                JR      PD_NEXT_CONT
+
+PD_NEXT:        INC     HL
+PD_NEXT_CONT:   DJNZ    PD_LOOP
+                RET
+
+PD_SET:         LD      A, 1
+                LD      (DBG_SUM), A
+                RET
+
+
+;------------------------------------------------------------------------------
+; 512-byte checksum over VGMBUF (simple 16-bit sum)
+;------------------------------------------------------------------------------
+
+CALC_SUM512:    PUSH    AF
+                PUSH    BC
+                PUSH    DE
+                PUSH    HL
+
+                LD      HL, VGMBUF
+                LD      DE, 0200H           ; 512 bytes
+                XOR     A
+                LD      (SUM_LO), A
+                LD      (SUM_HI), A
+
+SUM_LOOP:       LD      A, (HL)
+                INC     HL
+                LD      B, A
+                LD      A, (SUM_LO)
+                ADD     A, B
+                LD      (SUM_LO), A
+                LD      A, (SUM_HI)
+                ADC     A, 0
+                LD      (SUM_HI), A
+                DEC     DE
+                LD      A, D
+                OR      E
+                JR      NZ, SUM_LOOP
+
+                POP     HL
+                POP     DE
+                POP     BC
+                POP     AF
+                RET
+
+;------------------------------------------------------------------------------
+; Print A as two hex digits
+;------------------------------------------------------------------------------
+
+PRTHEX8:        PUSH    AF
+                PUSH    BC
+
+                LD      B, A                ; Save original byte in B
+                SRL     A
+                SRL     A
+                SRL     A
+                SRL     A                   ; High nibble
+                CALL    PRTHEX_NIB
+
+                LD      A, B
+                AND     0FH                 ; Low nibble
+                CALL    PRTHEX_NIB
+
+                POP     BC
+                POP     AF
+                RET
+
+PRTHEX_NIB:     CP      0AH
+                JR      C, HEX_DIGIT
+                ADD     A, 'A' - 10
+                JR      PRTHEX_OUT
+HEX_DIGIT:      ADD     A, '0'
+PRTHEX_OUT:     CALL    PRTCHR
+                RET
+
+
+;------------------------------------------------------------------------------
+; Print string pointed to by DE (terminated by 0)
+;------------------------------------------------------------------------------
+
+PRTSTR:         LD      A, (DE)
+                OR      A
+                RET     Z
+                CALL    PRTCHR
+                INC     DE
+                JR      PRTSTR
+
+;------------------------------------------------------------------------------
+; Print character in A
+;------------------------------------------------------------------------------
+
+PRTCHR:         PUSH    BC
+                PUSH    DE
+                PUSH    HL
+                LD      E, A
+                LD      C, 2
+                CALL    BDOS
+                POP     HL
+                POP     DE
+                POP     BC
+                RET
+
+;------------------------------------------------------------------------------
+; Print CR/LF
+;------------------------------------------------------------------------------
+
+CRLF:           LD      A, CR
+                CALL    PRTCHR
+                LD      A, LF
+                CALL    PRTCHR
+                RET
+
+;------------------------------------------------------------------------------
+; Messages
+;------------------------------------------------------------------------------
+
+MSG_HEADER:     .DB     CR, LF
+                .DB     "VGM Music Chip Scanner v1.1 - 06-Dec-2025", CR, LF
+                .DB     "(c)2025 Joao Miguel Duraes - MIT License", CR, LF
+                .DB     CR, LF
+                .DB     "Filename  Chips Used", CR, LF
+                .DB     0
+
+MSG_DIVIDER:    .DB     "========  =====================", CR, LF
+                .DB     0
+
+MSG_NOFILES:    .DB     "No .VGM files found in current directory", CR, LF
+                .DB     0
+
+MSG_SN76489:    .DB     "SN76489", 0
+MSG_SN76489X2:  .DB     "2xSN76489", 0
+MSG_YM2612:     .DB     "YM2612", 0
+MSG_YM2612X2:   .DB     "2xYM2612", 0
+MSG_YM2151:     .DB     "YM2151", 0
+MSG_YM2151X2:   .DB     "2xYM2151", 0
+MSG_OPL2:       .DB     "YM3812", 0
+MSG_OPL3:       .DB     "YMF262", 0
+MSG_AY8910:     .DB     "AY-3-8910", 0
+MSG_AY8910X2:   .DB     "2xAY-3-8910", 0
+MSG_UNKNOWN:    .DB     "Unknown/None", 0
+
+;------------------------------------------------------------------------------
+; Data area
+;------------------------------------------------------------------------------
+
+; Search FCB for *.VGM
+SEARCH_FCB:     .DB     0                   ; Default drive
+                .DB     '?','?','?','?','?','?','?','?'  ; Filename (wildcard)
+                .DB     'V','G','M'         ; Extension
+                .FILL   24, 0               ; Rest of FCB
+
+; FCB for opening files
+FILE_FCB:       .DB     0                   ; Default drive
+                .FILL   35, 0               ; Rest of FCB
+
+DIR_CODE:       .DB     0                   ; Directory code from search
+CHIP_FLAGS:     .DB     0                   ; Detected chip flags
+                                            ; bit0 SN76489 #1, bit1 SN76489 #2
+                                            ; bit2 YM2612 #1, bit3 YM2612 #2
+                                            ; bit4 YM2151 #1, bit5 YM2151 #2
+                                            ; bit6 AY #1, bit7 AY #2
+CHIP_TYPES:     .DB     0                   ; Chip types present from header
+                                            ; bit0 SN76489, bit1 YM2612
+                                            ; bit2 YM2151, bit3 AY-3-8910
+                                            ; bit4 OPL2 (YM3812), bit5 OPL3 (YMF262)
+
+SUM_LO:         .DB     0                   ; Low byte of 16-bit checksum
+SUM_HI:         .DB     0                   ; High byte of 16-bit checksum
+DBG_SUM:        .DB     0                   ; 0=disable checksum print, non-zero=enable
+
+; Buffer for VGM header + first data sector (256 bytes)
+VGMBUF:         .FILL   512, 0
+
+; Stack space
+                .FILL   64, 0
+STACK:          .DW     0
+
+                .END

Source/Apps/VGM/vgminfo.txt

@@ -0,0 +1,88 @@
+VGM File Info Scanner for CP/M
+===============================
+
+A utility that scans all .VGM files in the current directory and
+displays a table showing which audio chips each file uses.
+
+Version 1.1 uses a hybrid detection approach:
+- Checks VGM header clock values to detect chip types
+- Scans VGM command stream to detect multiple instances of same chip type
+
+Usage:
+------
+
+Simply run the program from a directory containing VGM files:
+
+    VGMINFO
+
+No command line arguments are needed. The program will automatically scan
+all .VGM files in the current directory.
+
+Output:
+-------
+
+The program displays a formatted table with two columns:
+  - Filename: The name of the VGM file
+  - Chips Used: A comma-separated list of audio chips used in that file
+
+Supported Chips:
+----------------
+
+The program can detect the following audio chips:
+  - SN76489 (PSG - Programmable Sound Generator)
+  - YM2612 (FM Synthesis chip used in Sega Genesis/Mega Drive)
+  - YM2151 (OPM - FM Operator Type-M)
+  - YM3812 (OPL2 - FM synthesis chip)
+  - YMF262 (OPL3 - Enhanced FM synthesis chip)
+  - AY-3-8910 (PSG used in many arcade and home computers)
+
+Example Output:
+---------------
+
+VGM Music Chip Scanner v1.1
+
+Filename  Chips Used
+========  =====================
+BGM       2xAY-3-8910
+ENDING    AY-3-8910
+INCHINA   YM2612
+SHIRAKAW  SN76489, YM2612
+STARTDEM  2xSN76489, AY-3-8910
+WONDER01  2xSN76489
+========  =====================
+
+Notes:
+------
+
+- The program reads the VGM file headers and scans up to 255 commands from
+  the VGM data stream for accurate chip detection.
+  
+- Files that don't have a valid VGM header are silently skipped.
+
+- Chip detection uses a hybrid approach:
+  * VGM header clock values (offsets 0x0C, 0x2C, 0x30, 0x74) determine
+    which chip types are present
+  * Command stream scanning detects multiple instances (e.g., "2xSN76489")
+
+- AY-3-8910 clock detection respects VGM version - only checked for v1.51+
+  to avoid false positives from invalid header data in older VGM versions.
+
+Building:
+---------
+
+To rebuild from source:
+
+    build_vgminfo.cmd
+
+Or manually with TASM:
+
+    tasm -t80 -b -g3 -fFF vgminfo.asm vgminfo.com
+
+Author:
+-------
+
+Created for RomWBW/CP/M systems
+Based on VGM format specification from vgmrips.net
+
+An AI LLM was utilized in the creation of this
+application.

Source/Apps/assign/assign.asm

@@ -40,6 +40,7 @@
 ;                    overflow when the drives are finally added
 ;   2025-07-19 [D?N] Support for native USB drivers
 ;   2025-08-09 [WBW] Support for ESPSD driver
+;   2025-11-10 [WBW] Support for SCSI driver
 ;_______________________________________________________________________________
 ;
 ; ToDo:
@@ -2430,7 +2431,7 @@ devtbl:				; device table
 	.dw	dev04, dev05, dev06, dev07
 	.dw	dev08, dev09, dev10, dev11
 	.dw	dev12, dev13, dev14, dev15
-	.dw	dev16, dev17
+	.dw	dev16, dev17, dev18
 ;
 devunk	.db	"?",0
 dev00	.db	"MD",0
@@ -2450,9 +2451,10 @@ dev13	.db	"CHUSB",0
 dev14	.db	"CHSD",0
 dev15	.db	"USB",0
 dev16	.db	"ESPSD",0
-dev17	.equ	devunk
+dev17	.db	"SCSI",0
+dev18	.equ	devunk
 ;
-devcnt	.equ	18		; 18 device types defined
+devcnt	.equ	19		; 19 device types defined
 ;
 udevram		.db	"RAM",0
 udevrom		.db	"ROM",0
@@ -2470,10 +2472,10 @@ stack	.equ	$		; stack top
 ; Messages
 ;
 indent	.db	"   ",0
-msgban1	.db	"ASSIGN v2.2 for RomWBW CP/M ",0
+msgban1	.db	"ASSIGN v2.3 for RomWBW CP/M ",0
 msg22	.db	"2.2",0
 msg3	.db	"3",0
-msbban2	.db	", 9-Aug-2025",0
+msbban2	.db	",10-Dec-2025",0
 msghb	.db	" (HBIOS Mode)",0
 msgub	.db	" (UBIOS Mode)",0
 msgban3	.db	"Copyright 2025, Wayne Warthen, GNU GPL v3",0

Source/Apps/copysl/copysl.asm

@@ -11,7 +11,8 @@
 ; ----------------
 ; 0.1 - Initial Version written by Mark Pruden
 ; 0.2 - Added support for /v (verify) option.
-; 0.3 - refresh CP/M disk buffers after completion
+; 0.3 - Refresh CP/M disk buffers after completion
+; 0.4 - Correct slice fit within partition calculation
 ; ----------------
 ;
     .ORG 100H
@@ -273,7 +274,7 @@ exit:
 ; =========================================
 ;
 msg_welcome:
-    .DB  "CopySlice v0.3 (RomWBW) March 2025 - M.Pruden", 13, 10, 0
+    .DB  "CopySlice v0.4 (RomWBW) December 2025 - M.Pruden", 13, 10, 0
 msg_overite_partition:
     .DB  13,10
     .DB  "Warning: Copying to Slice 0 of hd512 media, "
@@ -951,36 +952,36 @@ slicecalc3:
 
     ; add sps once again, to get Required (upper sector) needed
     add     hl, bc
-    JR      NC, slicecalc4
+    jr      nc, slicecalc4
     inc     de
+
 slicecalc4:
-    ; DE : HL has the total Sector requirement
-
-    ; subtract the total Media / Partition Sixe from the Capcity
-    ; we are not interested in the result, just the C Flag
-    ;
-    or      a ; clear cary flag
-    ;
-    ld      c, (ix + off_lbasize +0) ; capacity LSW
-    ld      b, (ix + off_lbasize +1) ; capacity LSW
-    sbc     hl, bc ; Requirement - Capacity LSW
-    ;
-    ex      de, hl ; Requirement MSW
-    ld      c, (ix + off_lbasize +2) ; capacity MSW
-    ld      b, (ix + off_lbasize +3) ; capacity MSW
-    sbc     hl, bc ; Requirement - Capacity MSW
-
-    ; pop Sector Offset
+    ; de:hl has the required number of sectors (on media) for the slice
+    push    de			; save dsk_req (msw)
+    push    hl			; save dsk_req (lsw)
+;
+    ; check dsk_capacity >= cap_required, CF set on overflow
+    ; no need to save actual result
+    or      a                           ; clear carry for sbc
+    ld      l, (ix + off_lbasize + 0)   ; capacity LSW
+    ld      h, (ix + off_lbasize + 1)   ; capacity LSW
+    pop     bc                          ; required lsw
+    sbc     hl, bc                      ; capacity - required (lsw)
+    ld      l, (ix + off_lbasize + 2)   ; capacity MSW
+    ld      h, (ix + off_lbasize + 3)   ; capacity MSW
+    pop     bc                          ; required msw
+    sbc     hl, bc                      ; capacity - required (msw)
+;
+    ; restore starting offset sector
     pop     de
     pop     hl
-
-    ; Require - Capacity - generates Cary if Capity > Require
-    JR      C, slicecalc5 ; C -> Require - Capacity : Require <= Capacity
+;
+    ; capacity - required -> generates no carry if capacity >= requirement
+    jr      nc, slicecalc5 		; if we have enough capacity
     or      0FFh ; otherwise signal not enough capacity
-    RET
+    ret
 
 slicecalc5:
-
     ; add lba offset to DEHL to get slice offset, commented code above
     ld      c, (ix + off_lbaoffset+0)
     ld      b, (ix + off_lbaoffset+1)

Source/Apps/copysl/copysl.doc

@@ -88,6 +88,7 @@ History
 * v 0.1 Initial Release
 * v 0.2 Added the /v command option to read and verify after write
 * v 0.3 Refresh CP/M disk buffers after completion
+* v 0.4 Correct slice fit within partition calculation
 
 Future
 ------

Source/CBIOS/cbios.asm

@@ -3408,7 +3408,7 @@ DEVTBL:	; DEVICE TABLE
 	.DW	DEV04, DEV05, DEV06, DEV07
 	.DW	DEV08, DEV09, DEV10, DEV11
 	.DW	DEV12, DEV13, DEV14, DEV15
-	.DW	DEV16, DEV17
+	.DW	DEV16, DEV17, DEV18
 ;
 DEVUNK	.DB	"???$"
 DEV00	.DB	"MD$"
@@ -3428,7 +3428,8 @@ DEV13	.DB	"CHUSB$"
 DEV14	.DB	"CHSD$"
 DEV15	.DB	"USB$"
 DEV16	.DB	"ESPSD$"
-DEV17	.EQU	DEVUNK
+DEV17	.DB	"SCSI$"
+DEV18	.EQU	DEVUNK
 ;
 #ENDIF
 ;

Source/Doc/Applications.md

@@ -330,8 +330,8 @@ and display the contents in hexadecimal.
 
 **`K`** - Echo any key-presses from the terminal. Press 'ESC' key
 to quit. This facility provides that any key stroke sent to
-the computer will be echoed back to the terminal. File down
-loads will be echoed as well while this facility is ‘on’.
+the computer will be echoed back to the terminal. File downloads
+will be echoed as well while this facility is ‘on’.
 
 #### Load Hex
 
@@ -364,7 +364,7 @@ Use clip leaded LEDs to confirm the data written.
 #### Program Memory
 
 **`P xxxx`** - Program memory location xxxx. This routine will
-allow you to program a hexadecimal value 'into memory starting
+allow you to program a hexadecimal value into memory starting
 at location xxxx. Press 'Enter' on a blank line to
 return to the Monitor prompt.
 
@@ -496,14 +496,14 @@ A comprehensive instruction manual is available in the Doc/Contrib directory.
 
 TastyBASIC offers a minimal implementation of BASIC that is only 2304
 bytes in size. It originates from Li-Chen Wang's Palo Alto Tiny BASIC
-from around 1976. It's small size is suited the tiny memory capacities of
+from around 1976. It's small size suited the tiny memory capacities of
 the time. This implementation is by Dimitri Theulings and his original
 source can be found at <https://github.com/dimitrit/tastybasic>.
 
 ### Features / Limitations
 
 - Integer arithmetic, numbers -32767 to 32767
-- Singles letter variables A-Z
+- Single letter variables A-Z
 - 1-dimensional array support
 - Strings are not supported
 
@@ -587,12 +587,12 @@ Extensions and changes to this implementation compared to the original distribut
 
 | Word | Syntax                     | Description                   |
 |------|----------------------------|-------------------------------|
-| D+	| d1 d2 -- d1+d2             | Add double numbers            |
-| 2>R	| d --                       | 2 to R                        |
-| 2R>	| d --                       | fetch 2 from R                |
-| M*/	| d1 n2 u3 --  d=(d1*n2)/u3  | double precision mult. div    |
-| SVC	| hl de bc n -- hl de bc af  | Execute a RomWBW function     |
-| P!	| n p --                     | Write a byte to a I/O port    |
+| D+   | d1 d2 -- d1+d2             | Add double numbers            |
+| 2>R  | d --                       | 2 to R                        |
+| 2R>  | d --                       | fetch 2 from R                |
+| M\*/ | d1 n2 u3 --  d=(d1\*n2)/u3 | double precision mult. div    |
+| SVC  | hl de bc n -- hl de bc af  | Execute a RomWBW function     |
+| P!   | n p --                     | Write a byte to a I/O port    |
 | P@   | p -- n                     | Read a byte from and I/O port |
 
 ## Play a Game (2048)
@@ -721,10 +721,10 @@ character-input/output device is to be used as the serial device for transfer.
 
 When your console is the serial device used for the transfer, no progress 
 information is displayed as this would disrupt the x-modem file transfer. 
-If you use an alternate character-input/output devices as the serial device 
+If you use an alternate character-input/output device as the serial device 
 for the transfer then progress information will be displayed on the console device.
 
-Due to different platform processor speeds,  serials speeds and flow 
+Due to different platform processor speeds, serial speeds and flow 
 control capabilities the default console or serial device speed may 
 need to be reduced for a successful transfer and flash to occur. 
 The **Set Console Interface/Baud code** option at the Boot Loader can 
@@ -758,14 +758,14 @@ Option ( < ) - Revert to Original Baud Rate
 
 Option ( U ) - Begin Update
 
-The will begin the update process. The updater will expect to start receiving
+This will begin the update process. The updater will expect to start receiving
 an x-modem file on the serial device unit.
 
 X-modem sends the file in packets of 128 bytes. The updater will cache 32
 packets which is 1 flash sector and then write that sector to the
 flash device.
 
-If using separate console, bank and sector progress information will shown
+If using separate console, bank and sector progress information will be shown
 
 ```
 BANK 00 s00 s01 s02 s03 s04 s05 s06 s06 s07
@@ -819,7 +819,7 @@ Option ( 3 ) - Calculate and display CRC32 of a 1024k (2x512Kb) ROM.
 
 Can be used to verify if a ROM image has been transferred and flashed 
 correctly. Refer to the Tera Term section below for details on 
-configuring the automatic display of a files CRC after it has been 
+configuring the automatic display of a file's CRC after it has been 
 transferred.
 
 In Windows, right clicking on a file should also give you a context 
@@ -837,7 +837,7 @@ process could be worthwhile if you are:
 * Doing development on RomWBW drivers
 
 Macros can be used to automate sending ROM updates or images and 
-for my own purposed I have set up a separate macro for transferring 
+for my own purpose I have set up a separate macro for transferring 
 each of the standard build ROM, my own custom configuration ROM 
 and update ROM.
 
@@ -883,7 +883,6 @@ Feedback to the RomWBW developers on these guidelines would be appreciated.
 
 ### Notes
 
-Notes
 * All testing was done with Tera Term x-modem, Forcing checksum mode 
   using macros was found to give  the most reliable transfer.
 * Partial writes can be completed with 39SF040 chips. Other chips  
@@ -925,7 +924,7 @@ Users should not remove this check from the templated code.
 If required, the user application may make use of the Z80 interrupt system
 but if the user application wishes to rely on HBIOS functionality then it
 must adhere to the HBIOS framework for managing interupts. Alternatively,
-if the user appliction has no need for the HBIOS then it may use its own
+if the user application has no need for the HBIOS then it may use its own
 custom code for handling interrupts. In that case, a hard reset, rather
 than an HBIOS warm start, would be necessary to return control to RomWBW.
 
@@ -989,6 +988,7 @@ included within RomWBW may be found within the Binary/Apps directory.
 | TIMER       | Yes      | Yes        |
 | TUNE        | No       | Yes        |
 | VGMPLAY     | No       | Yes        |
+| VGMINFO     | No       | Yes        |
 | WDATE       | No       | Yes        |
 | XM          | Yes      | Yes        |
 | ZMD         | No       | Yes        |
@@ -1020,9 +1020,9 @@ Disk-based CP/M:
 
 For systems starting CP/M from a disk created from an image file, there are a small number
 of additional applications stored in the ```USER 2``` area of the disk. These applications
-do not form part of CP/M, but rather are small utilities used for test purposes during develpment work.
-They may, or may not, fuction correctly with any given hardware or software configuration.
-Documentation for these untilities is very limited, though the source files maybe found
+do not form part of CP/M, but rather are small utilities used for test purposes during development work.
+They may, or may not, function correctly with any given hardware or software configuration.
+Documentation for these utilities is very limited, though the source files may be found
 in the /Source folder. Note that these utiltites are not available when starting CP/M
 from the ROM image or from a floppy disk.
 
@@ -1354,13 +1354,15 @@ The functionality is highly dependent on the capabilities of your system.
 
 #### Syntax
 
-| `CPUSPD [`*`<speed>`*`[,[`*`<memws>`*`][,[`*`<iows>`*`]]]`
+| `CPUSPD [`*\<speed\>*`[,[`*\<memws\>*`][,[`*\<iows\>*`]]]`
 | `CPUSPD (W)armBoot`
 | `CPUSPD (C)oldBoot`
 
-*`<speed>`* is one of (H)alf, (F)ull, (D)ouble, or (Q)uad.
-*`<memws>`* is a number specifying the desired memory wait states.
-*`<iows>`* is a number specifying the desired I/O wait states.
+*\<speed\>* is one of (H)alf, (F)ull, (D)ouble, or (Q)uad.
+
+*\<memws\>* is a number specifying the desired memory wait states.
+
+*\<iows\>* is a number specifying the desired I/O wait states.
 
 #### Usage
 
@@ -1369,7 +1371,7 @@ and wait state information of the running system.  Wait state
 information is not available for all systems.
 
 To modify the running speed of a system, you can specify the
-`*`<speed>`*` parameter.  To modify either or both of the wait
+*\<speed\>* parameter.  To modify either or both of the wait
 states, you can enter the desired number.  Either or both of the wait
 state parameters may be omitted and the current wait state settings
 will remain in effect.
@@ -1436,20 +1438,20 @@ The source code is provided in the RomWBW distribution.
 The purpose of this utility is to allow the copying of whole disk slices
 from one disk slice to another slice
 
-This tool is only supported by RomWBW HBIOS, it uses HBIOS for all its
+This tool is only supported by RomWBW HBIOS; it uses HBIOS for all its
 disk IO. UNA UBIOS is not supported by this tool.
 
 This tool is running on CP/M 2.2 or 3.0 and has access to full 64kb of
 RAM, with a minimum of 48kb TPA
 
-This tool only works with hard disk devices, other media types like
+This tool only works with hard disk devices; other media types like
 floppy, are not supported at this time. This tool works across different
 hard disk device types, even of different physical type
 
 Both hd1k and hd512 are fully supported, however copying from one layout
 type to the other is not supported.
 
-During operation data is copied in a single read/write pass, data is not
+During operation, data is copied in a single read/write pass; data is not
 verified by default. If there is a write error, it will be reported, and
 operation will stop.
 
@@ -1477,7 +1479,7 @@ V - Verify. Does an additional read and verify after write.
 
 #### Usage
 
-When run COPYSL will perform command line argument validation and display
+When run, COPYSL will perform command line argument validation and display
 an error if they are illegal. Also any disk IO errors will cause COPYSL
 to exit.
 
@@ -1766,7 +1768,7 @@ provided in the RomWBW distribution.
 | Disk-based          |Yes|
 
 Most of the hardware platforms that run RomWBW support the use of
-EEPROMs -- Electronically Erasable Programmable ROMs. The `FLASH`
+EEPROMs -- Electrically Erasable Programmable ROMs. The `FLASH`
 application can be used to reprogram such ROMS in-situ (in-place),
 thus making it possible to upgrade ROMs without a programmer or even
 removing the ROM from your system.
@@ -1799,7 +1801,7 @@ Options:
 #### Usage
 
 To program your EEPROM ROM chip, first transfer the file to your
-RomWBW system. Then use the command `FLASH WRITE *`<filename>`*. The
+RomWBW system. Then use the command `FLASH WRITE `*\<filename\>*. The
 application will auto-detect the type of EEPROM chip you have,
 program it, and verify it.
 
@@ -2081,7 +2083,7 @@ support most of the hardware variations included with RomWBW.
 
 Display or change the label of a disk slice.
 
-The label applied is only used as informational purposes, displayed by RomWBW 
+The label applied is only used for informational purposes, displayed by RomWBW 
 when an OS is booted. It has no correlation with any OS volume label scheme 
 that may exist. i.e. It does not affect the CP/M 3 disk label as applied by 
 the `SET` command
@@ -2113,7 +2115,7 @@ This will only display labels for the first 64 slices of any device. Slices
 higher than this are currently ignored.
 
 Only bootable RomWBW disk images have a label, which is defined by the OS
-which is booted. i.e. NZ-COM has a label of "ZSDOS 1.1" since that is the 
+that is booted. i.e. NZ-COM has a label of "ZSDOS 1.1" since that is the 
 booted OS. Prior to RomWBW 3.5 all disk images were defined with the label 
 "Unlabeled".
 
@@ -2169,7 +2171,7 @@ discover ports that are 'write-only'.
 | Disk-based          |Yes|
 
 System Configuration (`SYSCONF`) is a utility that allows system configuration to
-be set, dynamically and stored in NVRAM provided by an RTC chip.
+be set dynamically and stored in NVRAM provided by an RTC chip.
 
 (`SYSCONF`) is both a ROM utility ('W' Menu option), and a CP/M application.
 Noting however the CP/M application is not included on an disk image, it is found in
@@ -2205,7 +2207,6 @@ Commands:
   (H)elp [{SW}] - This help menu, or help on a switch
   e(X)it - Exit Configuration
   
-$
 ```
 
 When you run (`SYSCONF`) for the first time the NVRAM will be uninitialised, and can
@@ -2225,7 +2226,7 @@ To exit from the application use the (Q)uit command.
 
 #### Commands and Syntax
 
-The following are the accepted commands, unless otherwise specified a "Space"
+The following are the accepted commands, unless otherwise specified. A "Space"
 character is used to delimit parameters in the command.
 
 | Command   | Argument(s)      | Description                                   |
@@ -2259,7 +2260,7 @@ Making changes to auto boot has no affect until the next reboot.
 | Type     | Arguments  | Description                                            |
 |----------|------------|--------------------------------------------------------|
 | Enable   | 'E'        | Auto Boot. eg. "E,10" will auto boot, after 10 seconds |
-|          | Timout     | Timeout in seconds in the range 0-15, 0 = immediate    |
+|          | Timeout    | Timeout in seconds in the range 0-15, 0 = immediate    |
 | Disabled | 'D'        | No Auto Boot. e.g. "D" will disable autoboot           |
 
 **Examples**
@@ -2365,7 +2366,7 @@ considered its own operating system. Each slice can be made bootable
 with its own system tracks.
 
 `SYSCOPY` uses drive letters to specify where to read/write the system
-boot images. However, at startup, the boot loaded will require you to
+boot images. However, at startup, the boot(?) loaded will require you to
 enter the actual disk device and slice to boot from. So, you need to
 be careful to pay attention to the device and slice that is assigned
 to a drive letter so you will know what to enter at the boot loader
@@ -2377,10 +2378,10 @@ not currently assigned to a drive letter, you will need to assign a
 drive letter first.
 
 Not all disk formats include space for system tracks. Such disk
-formats cannot contains a system boot image and, therefore, cannot be
+formats cannot contain a system boot image and, therefore, cannot be
 made bootable. The best example of such disk formats are the ROM and
 RAM disks. To maximize usable file space on these drives, they do not
-have system tracks. Obviously, ROM operating system is supported by
+have system tracks. Obviously, the ROM operating system is supported by
 choosing a ROM operating system at the boot loader prompt. Any attempt
 to write a system boot image to disk media with no system tracks will
 cause SYSCOPY to fail with an error message.
@@ -2493,7 +2494,7 @@ displays the value of the counter.
 
 Use `TIMER` to display the current value of the counter.
 
-Use `TIMER /C` to display the value of the counter continuously.
+Use `TIMER /C` to display the value of the counter continuously.  Press any key to exit.
 
 Use `TIMER /Z` to zero the seconds counter.
 
@@ -2518,7 +2519,7 @@ fraction will increment 0.02 seconds with each timer tick.
 The primary use of the `TIMER` application is to test the system
 timer functionality of your system.  However, it can be used to
 capture the value before and after some process you want to measure
-elapsed runtime.
+the elapsed runtime of.
 
 #### Etymology
 
@@ -2538,7 +2539,7 @@ If your RomWBW system has a sound card based on either an AY-3-8190 or
 YM2149F sound chip, you can use the `TUNE` application to play PT or
 MYM sound files.
 
-Note: TUNE will detect an AY-3-8910/YM2149 Sound Module re-gardless of 
+Note: TUNE will detect an AY-3-8910/YM2149 Sound Module regardless of 
 whether support for it is included in the RomWBW HBIOS configuration
 
 #### Syntax
@@ -2640,6 +2641,67 @@ The source code is provided in the RomWBW distribution.
 
 `\clearpage`{=latex}
 
+## VGMINFO (Video Game Music File Information)
+
+| VGMPLAY             |   |
+| --------------------|---|
+| ROM-based           |No |
+| Disk-based          |Yes|
+
+A utility that scans all .VGM files in the current directory and
+displays a table showing which audio chips each file uses.
+
+Version 1.1 uses a hybrid detection approach:
+
+- Checks VGM header clock values to detect chip types
+- Scans VGM command stream to detect multiple instances of same chip type
+
+#### Syntax
+
+| `VGMINFO`
+
+#### Usage
+
+No command line arguments are needed. The program will automatically scan
+all .VGM files in the current directory.
+
+The program displays a formatted table with two columns:
+
+  - Filename: The name of the VGM file
+  - Chips Used: A comma-separated list of audio chips used in that file
+
+The program can detect the following audio chips:
+
+  - SN76489 (PSG - Programmable Sound Generator)
+  - YM2612 (FM Synthesis chip used in Sega Genesis/Mega Drive)
+  - YM2151 (OPM - FM Operator Type-M)
+  - YM3812 (OPL2 - FM synthesis chip)
+  - YMF262 (OPL3 - Enhanced FM synthesis chip)
+  - AY-3-8910 (PSG used in many arcade and home computers)
+
+#### Notes
+
+- The program reads the VGM file headers and scans up to 255 commands from
+  the VGM data stream for accurate chip detection.
+  
+- Files that don't have a valid VGM header are silently skipped.
+
+- Chip detection uses a hybrid approach:
+  * VGM header clock values (offsets 0x0C, 0x2C, 0x30, 0x74) determine
+    which chip types are present
+  * Command stream scanning detects multiple instances (e.g., "2xSN76489")
+
+- AY-3-8910 clock detection respects VGM version - only checked for v1.51+
+  to avoid false positives from invalid header data in older VGM versions.
+
+#### Etymology
+
+The `VGMINFO` application was written and contributed to RomWBW by
+Joao Miguel Duraes.  An AI LLM was utilized in the creation of this
+application.
+
+`\clearpage`{=latex}
+
 ## VGMPLAY (Video Game Music Play)
 
 | VGMPLAY             |   |
@@ -2829,6 +2891,7 @@ files between systems using a serial port.
 | `XM R `*`<filename>`*
 
 The following may be added to the action codes:
+
 | `S`: Send a file
 | `L`: Send a file from a library
 | `R`: Receive a file
@@ -2865,7 +2928,7 @@ the following:
 to be sent.
 
 2. On your host computer, specify the name to assign to the received
-file and initiate and XModem receive operation.
+file and initiate an XModem receive operation.
 
 Please refer to the documentation of your host computer's terminal
 emulation software for specific instructions on how to use XModem.
@@ -2946,7 +3009,7 @@ To transfer a file from your host computer to your RomWBW computer, do
 the following:
 
 1. Enter one of the `ZMD` receive commands specifying the name you want
-to give to the received file (no filename required for ZModem transfers).
+to give to the received file (no filename required for ZModem transfers).["ZMD does not do ZModem transfers"]
 
 2. On your host computer select a file to send and initiate an XModem or
 YModem send operation.

Source/Doc/Catalog.md

@@ -978,6 +978,7 @@ The following files are found in
 | `TSTDSKNG.COM`      | DSKY NEXT GENERATION TEST APPLICATION                   |
 | `VDCONLY.COM`       | COLOR VDU TEST                                          |
 | `VDCTEST.COM`       | COLOR VDU TEST                                          |
+| `Z80TYPE.COM`       | Z80 Chip Variant Detection                              |
 | `ZEXALL.COM`        | Z80 Instruction Set Exerciser                           |
 | `ZEXDOC.COM`        | Z80 Instruction Set Exerciser                           |
 
@@ -1433,15 +1434,15 @@ The following files are found in
 | `TURBO.OVR`    | Part of TURBO Pascal           |
 | `TURBOMSG.OVR` | Part of TURBO Pascal           |
 
-## WordStar 4 (Word processor)
+## Word Processing
 
-| Floppy Disk Image: **fd_ws4.img**
-| Hard Disk Image: **hd_ws4.img**
+| Floppy Disk Image: **fd_wp.img**
+| Hard Disk Image: **hd_wp.img**
 | Combo Disk Image: **Slice 5**
 
 The following files are found in
 
-*  /Source/Images/d_ws4
+*  /Source/Images/d_wp
 
 | **File**       | **Description** |
 |----------------|-----------------|

Source/Doc/Hardware.md

@@ -28,6 +28,7 @@ including RC26, RC40, RC80, and BP80.
 
 | **Description**                                             | **Bus** | **ROM Image File**           | **Baud Rate** |
 |-------------------------------------------------------------|---------|------------------------------|--------------:|
+| [RC2014 Z80 CPU Module], 512K RAM/ROM                       | RCBus   | RC2014_std.rom               | 115200        |
 | [RCBus Z80 CPU Module], 512K RAM/ROM                        | RCBus   | RCZ80_std.rom                | 115200        |
 | [RCBus Z80 CPU Module (KIO)], 512K w/KIO                    | RCBus   | RCZ80_kio_std.rom            | 115200        |
 | [RCBus Z180 CPU Module (External)]                          | RCBus   | RCZ180_ext_std.rom           | 115200        |
@@ -117,10 +118,11 @@ Others
 | [Genesis Z180 System]^7^                                    | STD      | GMZ180_std.rom              |        115200 |
 | [Heath H8 Z80 System]^5^                                    | H8       | HEATH_std.rom               |        115200 |
 | [MSX]^9^                                                    | MSX      | MSX_std.rom                 |        115200 |
+| [N8 PC]^10^                                                 | ISA      | N8PC_std.rom                |         38400 |
 | [NABU w/ RomWBW Option Board]^5^                            | NABU     | NABU_std.rom                |        115200 |
-| [S100 Computers Z180 SBC]^4^                                | S100     | S100_std.rom                |         57600 |
-| [S100 Computers Z80 CPU]^4^                                 | S100     | SZ80_std.rom                |          9600 |
-| [S100 Computers FPGA Z80 SBC]^4^                            | S100     | SZ80_fpga.rom               |          9600 |
+| [S100 Computers Z180 SBC]^4^                                | S100     | SZ180_std.rom               |         57600 |
+| [S100 Computers Z80 CPU]^4^                                 | S100     | SZ80_std.rom                |         19200 |
+| [S100 Computers T35 FPGA Z80 SBC]^4^                        | S100     | SZ80_t35.rom                |          9600 |
 | [UNA Hardware BIOS]^1^                                      | -        | UNA_std.rom                 |             - |
 | [Z80-Retro SBC]^3^                                          | -        | Z80RETRO_std.rom            |         38400 |
 | [Z180 Mark IV SBC]^1^                                       | ECB      | MK4_std.rom                 |         38400 |
@@ -134,6 +136,7 @@ Others
 | ^7^Designed by Doug Jackson
 | ^8^Designed by Dean Netherton
 | ^9^MSX Port by Henk Berends
+| ^10^Designed by Dan Werner
 
 `\clearpage`{=latex}
 
@@ -434,39 +437,48 @@ Z80-based S100 Modular System
 | Default CPU Speed | 8.000 MHz     |
 | Interrupts        | None          |
 | System Timer      | None          |
-| Serial Default    | 9600 Baud     |
+| Serial Default    | 19200 Baud    |
 | Memory Manager    | SZ80          |
 | ROM Size          | 0 KB          |
-| RAM Size          | 512 KB        |
+| RAM Size          | 1024 KB       |
 
 #### Supported Hardware
 
+- FP: LEDIO=5
+- DLPSER: IO=172
+- SCC MODE=SZ80, IO=160, CHANNEL A
+- SCC MODE=SZ80, IO=160, CHANNEL B
 - SCON: IO=0
 - ESPSD: IO=128, PRIMARY
 - ESPSD: IO=128, SECONDARY
 - MD: TYPE=RAM
-- PPIDE: MODE=STD, IO=48, MASTER
-- PPIDE: MODE=STD, IO=48, SLAVE
-- PPIDE: MODE=S100A, IO=56, MASTER
-- PPIDE: MODE=S100A, IO=56, SLAVE
-- PPIDE: MODE=S100B, IO=56, MASTER
-- PPIDE: MODE=S100B, IO=56, SLAVE
-- SD: MODE=FZ80, IO=108, UNITS=2
+- PPIDE: MODE=S100A, IO=48, MASTER
+- PPIDE: MODE=S100A, IO=48, SLAVE
+- PPIDE: MODE=S100B, IO=48, MASTER
+- PPIDE: MODE=S100B, IO=48, SLAVE
 
 #### Notes:
 
-- Requires Propeller Console Board (or equivalent)
+- Initial console will depend on the IOBYTE dip switch settings.
+  See website for dip switch settings.
+
+- Version 6.0 or greater of the S100 Z80 Monitor ROM is required to
+  load and run RomWBW.
+
+- RomWBW is loaded by the S100 monitor from either CF Card or SD Card.
+  The CF/SD Card should be imaged using SZ80_std_hd1k_combo.img which
+  includes RomWBW.
 
 `\clearpage`{=latex}
 
-### S100 Computers FPGA Z80 SBC
+### S100 Computers T35 FPGA Z80 SBC
 
-An FPGA Z80 based S100 SBC
+A T35 FPGA Z80 based S100 SBC
 
 * Creator: John Monahan
 * Website: [S100 Computers FPGA Z80 SBC](http://www.s100computers.com/My%20System%20Pages/FPGA%20Z80%20SBC/FPGA%20Z80%20SBC.htm)
 
-#### ROM Image File:  SZ80_fpga.rom
+#### ROM Image File:  SZ80_t35.rom
 
 |                   |               |
 |-------------------|---------------|
@@ -474,17 +486,21 @@ An FPGA Z80 based S100 SBC
 | Default CPU Speed | 8.000 MHz     |
 | Interrupts        | None          |
 | System Timer      | None          |
-| Serial Default    | 9600 Baud     |
+| Serial Default    | 19200 Baud    |
 | Memory Manager    | Z2            |
 | ROM Size          | 0 KB          |
 | RAM Size          | 512 KB        |
 
 #### Supported Hardware
 
+- FP: LEDIO=255
 - DS5RTC: RTCIO=104, IO=104
-- SSER: IO=52
-- LPT: MODE=S100, IO=199
-- FV: IO=192, KBD MODE=FV, KBD IO=3
+- TSER: IO=53
+- DLPSER: IO=172
+- SCC MODE=SZ80, IO=160, CHANNEL A
+- SCC MODE=SZ80, IO=160, CHANNEL B
+- LPT: MODE=T35, IO=199
+- TVGA: IO=192, KBD MODE=T35, KBD IO=3
 - KBD: ENABLED
 - SCON: IO=0
 - ESPSD: IO=128, PRIMARY
@@ -496,11 +512,24 @@ An FPGA Z80 based S100 SBC
 - PPIDE: MODE=S100A, IO=56, SLAVE
 - PPIDE: MODE=S100B, IO=56, MASTER
 - PPIDE: MODE=S100B, IO=56, SLAVE
-- SD: MODE=FZ80, IO=108, UNITS=2
+- SD: MODE=T35, IO=108, UNITS=2
+
 
 #### Notes:
 
-- Requires matching FPGA code, see [S100 Projects RomWBW T35 Project](https://github.com/s100projects/ROMWBW_T35).
+- This RomWBW build is specifically for the Trion T35 based module on
+  the S100 Z80 FPGA board.  The Waveshare FPGA module is not supported
+  at this time.
+
+- Requires matching FPGA code, see
+  [S100 Projects RomWBW T35 Project](https://github.com/s100projects/ROMWBW_T35).
+
+- Initial console will depend on the IOBYTE dip switch settings.
+  See website for dip switch settings.
+
+- RomWBW is loaded by the S100 monitor from either CF Card or SD Card.
+  The CF/SD Card should be imaged using SZ80_t35_hd1k_combo.img which
+  includes RomWBW.
 
 `\clearpage`{=latex}
 
@@ -903,8 +932,101 @@ This configuration is for the N8-2312 and latter (4314) revisions
 
 `\clearpage`{=latex}
 
+## N8 PC
+
+This is a variant of the N8 computer.
+
+* Creator: Dan Werner
+* Project GitHub: [N8 PC](https://github.com/danwerner21/N8PC)
+
+#### ROM Image File:  N8PC_std.rom
+
+|                   |               |
+|-------------------|---------------|
+| Bus               | ISA           |
+| Default CPU Speed | 9.216 MHz     |
+| Interrupts        | None          |
+| System Timer      | Z180          |
+| Serial Default    | 38400 Baud    |
+| Memory Manager    | N8            |
+| ROM Size          | 512 KB        |
+| RAM Size          | 512 KB        |
+
+#### Supported Hardware
+
+- PKD: IO=132, SIZE=8X1
+- M6242RTC: IO=160
+- ASCI: IO=64
+- ASCI: IO=65
+- TMS: MODE=N8PC, IO=152, SCREEN=80X24, KEYBOARD=KBD
+- KBD: ENABLED
+- MD: TYPE=RAM
+- MD: TYPE=ROM
+- FD: MODE=N8, IO=140, DRIVE 0, TYPE=3.5" HD
+- FD: MODE=N8, IO=140, DRIVE 1, TYPE=3.5" HD
+- PPIDE: MODE=STD, IO=132, MASTER
+- PPIDE: MODE=STD, IO=132, SLAVE
+- AY38910: MODE=N8, IO=156, CLOCK=3579545 HZ
+
+#### Notes:
+
+`\clearpage`{=latex}
+
 ## RCBus Z80
 
+The RC2014 ROM is for the official RC2014 Kits by Spencer Owen.
+
+* Creator: Spencer Owen
+* Google Groups: [RC2014-Z80](https://groups.google.com/g/rc2014-z80)
+* Github: [RC2014](https://github.com/RC2014Z80/RC2014)
+
+### RC2014 Z80 CPU Module
+
+Generic Rom Image.
+
+#### ROM Image File:  RC2014_std.rom
+
+|                   |               |
+|-------------------|---------------|
+| Bus               | RCBus         |
+| Default CPU Speed | 7.372 MHz     |
+| Interrupts        | Mode 1        |
+| System Timer      | None          |
+| Serial Default    | 115200 Baud   |
+| Memory Manager    | Z2            |
+| ROM Size          | 512 KB        |
+| RAM Size          | 512 KB        |
+
+#### Supported Hardware
+
+- FP: LEDIO=0, SWIO=0
+- LCD: IO=218, SIZE=20X4
+- DSRTC: MODE=STD, IO=192
+- UART: IO=128
+- UART: IO=136
+- UART: IO=160
+- UART: IO=168
+- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED
+- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED
+- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED
+- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED
+- ACIA: IO=128, INTERRUPTS ENABLED
+- CH: IO=62
+- CH: IO=60
+- CHUSB: IO=62
+- CHUSB: IO=60
+- MD: TYPE=RAM
+- MD: TYPE=ROM
+- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD
+- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD
+- IDE: MODE=RC, IO=16, MASTER
+- IDE: MODE=RC, IO=16, SLAVE
+- PPIDE: IO=32, MASTER
+- PPIDE: IO=32, SLAVE
+- SD: MODE=PIO, IO=105, UNITS=1
+
+`\clearpage`{=latex}
+
 ### RCBus Z80 CPU Module
 
 Generic Rom Image.
@@ -1871,7 +1993,7 @@ as defined by the IEEE-696 specs.
 * Creator: John Monahan                                                                           |
 * Website: [S100 Computers Z180 SBC](http://www.s100computers.com/My%20System%20Pages/Z180%20SBC/Z180%20SBC.htm)
 
-#### ROM Image File:  S100_std.rom
+#### ROM Image File:  SZ180_std.rom
 
 |                   |               |
 |-------------------|---------------|
@@ -1887,19 +2009,21 @@ as defined by the IEEE-696 specs.
 #### Supported Hardware
 
 - INTRTC: ENABLED
+- DLPSER: IO=172
 - ASCI: IO=192, INTERRUPTS ENABLED
 - ASCI: IO=193, INTERRUPTS ENABLED
+- SCC MODE=SZ80, IO=160, CHANNEL A
+- SCC MODE=SZ80, IO=160, CHANNEL B
 - SCON: IO=0
-- MD: TYPE=RAM
-- MD: TYPE=ROM
-- SD: MODE=SC, IO=12, UNITS=1
 - ESPSD: IO=128, PRIMARY
 - ESPSD: IO=128, SECONDARY
-- ESPSD occupies 995 bytes.
+- MD: TYPE=RAM
+- MD: TYPE=ROM
 - PPIDE: MODE=S100A, IO=48, MASTER
 - PPIDE: MODE=S100A, IO=48, SLAVE
 - PPIDE: MODE=S100B, IO=48, MASTER
 - PPIDE: MODE=S100B, IO=48, SLAVE
+- SD: MODE=SC, IO=12, UNITS=1
 
 #### Notes:
 
@@ -2215,7 +2339,7 @@ Z180 CPU (eg. SC722) with 1MB linear memory (eg. SC721)
 - PPIDE: IO=32, SLAVE
 - SD: MODE=SC, IO=12, UNITS=1
 
-\clearpage`{=latex}
+`\clearpage`{=latex}
 
 ## Z80-Retro SBC
 
@@ -2361,8 +2485,11 @@ may be discovered by RomWBW in your system.
 | PPPCON    | ParPortProp Serial Console Interface                   |
 | PRPCON    | PropIO Serial Console Interface                        |
 | SCON      | S100 Console                                           |
-| SIO       | Zilog Serial Port Interface                            |
+| SIO       | Zilog Serial Input/Output Controller (SIO)             |
+| SCC       | Zilog Serial Communications Controller (SCC)           |
 | SSER      | Simple Serial Interface                                |
+| TSER      | Trion FPGA Serial Interface                            |
+| DLPSER    | DLP USB Serial Interface                               |
 | UART      | 16C550 Family Serial Interface                         |
 | USB-FIFO  | FT232H-based ECB USB FIFO                              |
 | Z2U       | Zilog Z280 CPU Built-in Serial Ports                   |
@@ -2372,16 +2499,20 @@ discovers for the initial console.  The following character devices are
 scanned in the order shown.  The available character devices depend on
 the active platform and configuration.
 
-#. SSER: Simple Serial Interface
 #. ASCI: Zilog Z180 CPU Built-in Serial Ports
 #. Z2U: Zilog Z280 CPU Built-in Serial Ports
 #. UART: 16C550 Family Serial Interface
 #. DUART: SCC2681 or compatible Dual UART
-#. SIO: Zilog Serial Port Interface
+#. SIO: Zilog Serial Port Interface (SIO)
+#. SCC: Zilog Serial Port Interface (SCC)
 #. EZ80UART: eZ80 Serial Port Interface
 #. ACIA: MC68B50 Asynchronous Communications Interface Adapter
+#. SSER: Simple Serial Interface
+#. TSER: Trion FPGA Serial Interface
+#. DLPSER: DLP USB Serial Interface
 #. USB-FIFO: FT232H-based ECB USB FIFO
 
+
 ## Disk
 
 | **ID**    | **Description**                                        |
@@ -2401,6 +2532,7 @@ the active platform and configuration.
 | SD        | SD Card Interface                                      |
 | SYQ       | Iomega SparQ Drive on PPI                              |
 | ESPSD     | S100 ESP32-based SD Card Interface                     |
+| SCSI      | 5380 SCSI Interface                                    |
 
 ## Video
 
@@ -2408,10 +2540,10 @@ the active platform and configuration.
 |-----------|--------------------------------------------------------|
 | CVDU      | MC8563-based Video Display Controller                  |
 | EF        | EF9345 Video Display Controller                        |
-| FV        | S100 FPGA Z80 Onboard VGA/Keyboard                     |
+| TVGA      | S100 Trion FPGA Onboard VGA/Keyboard                   |
 | GDC       | uPD7220 Video Display Controller                       |
 | TMS       | TMS9918/38/58 Video Display Controller                 |
-| VDU       | MC6845 Family Video Display Controller (*)             |
+| VDU       | MC6845 Family Video Display Controller (\*)            |
 | VGA       | HD6445CP4-based Video Display Controller               |
 | VRC       | VGARC Video Display Controller                         |
 | XOSERA    | XOSERA FPGA-based Video Display Controller             |
@@ -2457,6 +2589,9 @@ Note:
 | PCF       | PCF8584-based I2C Real-Time Clock                      |
 | RP5C01    | Ricoh RPC01A Real-Time Clock w/ NVRAM                  |
 | SIMRTC    | SIMH Simulator Real-Time Clock                         |
+| MMRTC     | NS MM58167B Real-Time Clock (no NVRAM)                 |
+| DS12RTC   | Dallas Semiconductor DS1288x Real-Time Clock w/ NVRAM  |
+| M6242     | MSM6242 Real-Time Clock (no NVRAM)                     |
 
 ## DsKy (DiSplay KeYpad)
 
@@ -2540,3 +2675,4 @@ for more information on UNA.
   CP/M 3, ZPM3, and p-System.
   
 - Some of the RomWBW-specific applications are not UNA compatible.
+

Source/Doc/Introduction.md

@@ -347,6 +347,9 @@ please let me know if I missed you!
 
 * Henk Berends added support for the MSX platform.
 
+* Jay Cotton provided the SCSI transport code upon which the SCSI
+  driver is based.
+
 `\clearpage`{=latex}
 
 ## Related Projects

Source/Doc/SystemGuide.md

@@ -1101,6 +1101,7 @@ below enumerates their values.
 | DIODEV_CHSD     | 0x0E   | CH375/376 SD Card                        | ch.asm     |
 | DIODEV_USB      | 0x0F   | CH376 Native USB Device                  | ch376.asm  |
 | DIODEV_ESPSD    | 0x10   | S100 ESP32 SD Card                       | espsd.asm  |
+| DIODEV_SCSI     | 0x11   | 5380 SCSI Interface                      | scsi.asm   |
 
 A fixed set of media types are defined. The currently defined media 
 types identifiers are listed below. Each driver will support one or
@@ -1208,8 +1209,8 @@ point, all disk drivers support both LBA and CHS addressing.
 | E: Sector Count                        |                                        |
 | HL: Buffer Address                     |                                        |
 
-Read Sector Count (E) sectors into the buffer located in Buffer Bank ID (D) 
-at Buffer Address (HL) starting at the Current Sector.  The returned 
+Read Sector Count (E) sectors into the buffer located in Buffer Bank ID 
+(D) at Buffer Address (HL) starting at the Current Sector.  The returned
 Status (A) is a standard HBIOS result code.
 
 The Current Sector is established by a prior DIOSEEK function call;
@@ -1219,18 +1220,21 @@ successfully read. On error, the Current Sector will be the sector where
 the error occurred. Sectors Read (E) indicates the number of sectors 
 successfully read.
 
+A Sector Count of zero will result in no sectors being read and a
+status of success.  The buffer will not be modified.
+
+For buffers in the bottom 32KB ram, the Bank ID is used to identify the 
+bank to use for the buffer. If the buffer is located in your current 
+active bank, you will need to provide the current Bank ID, which can be 
+obtained using [Function 0xF3 -- System Get Bank (SYSGETBNK)].  For 
+buffers in the top 32K of memory the Bank ID is not strictly required as
+this memory is always mapped to the common bank. 
+
 The caller must ensure that the Buffer Address is large enough to
 contain all sectors requested.  Disk data transfers will be faster if
 the buffer resides in the top 32K of memory because it avoids a
 double buffer copy.
 
-Also for buffers in the top 32K of memory the Bank ID is not
-strictly required as this memory is alway mapped to the common bank.
-For buffers in the bottom 32KB ram, the Bank ID is used to identify
-the bank to use for the buffer. If you do not wih to use banked memory
-you will need to provide the current Bank ID, which can be obtained
-using [Function 0xF3 -- System Get Bank (SYSGETBNK)] 
-
 ### Function 0x14 -- Disk Write (DIOWRITE)
 
 | **Entry Parameters**                   | **Returned Values**                    |
@@ -1241,9 +1245,9 @@ using [Function 0xF3 -- System Get Bank (SYSGETBNK)]
 | E: Sector Count                        |                                        |
 | HL: Buffer Address                     |                                        |
 
-Write Sector Count (E) sectors from the buffer located in Buffer Bank ID (D)
-at Buffer Address (HL) starting at the Current Sector.  The returned 
-Status (A) is a standard HBIOS result code.
+Write Sector Count (E) sectors from the buffer located in Buffer Bank ID
+(D) at Buffer Address (HL) starting at the Current Sector.  The 
+returned Status (A) is a standard HBIOS result code.
 
 The Current Sector is established by a prior DIOSEEK function call; 
 however, multiple read/write/verify function calls can be made after a 
@@ -1252,6 +1256,16 @@ successfully written. On error, the Current Sector will be the sector
 where the error occurred. Sectors Written (E) indicates the number of 
 sectors successfully written.
 
+A Sector Count of zero will result in no sectors being written and a
+status of success.  The buffer will not be modified.
+
+For buffers in the bottom 32KB ram, the Bank ID is used to identify the 
+bank to use for the buffer. If the buffer is located in your current 
+active bank, you will need to provide the current Bank ID, which can be 
+obtained using [Function 0xF3 -- System Get Bank (SYSGETBNK)].  For 
+buffers in the top 32K of memory the Bank ID is not strictly required as
+this memory is always mapped to the common bank. 
+
 Disk data transfers will be faster if the buffer resides in the top 32K 
 of memory because it avoids a double copy.
 
@@ -1430,6 +1444,8 @@ unit.  The table below enumerates these values.
 | RTCDEV_RP5      | 0x05   | Ricoh RPC01A Real-Time Clock w/ NVRAM    | rp5rtc.asm  |
 | RTCDEV_EZ80     | 0x07   | eZ80 on-chip RTC                         | ez80rtc.asm |
 | RTCDEV_PC       | 0x08   | MC146818/DS1285/DS12885 RTC w/ NVRAM     | pcrtc.asm   |
+| RTCDEV_MM       | 0x09   | NS MM58167B RTC (no NVRAM)               | mmrtc.asm   |
+| RTCDEV_DS12     | 0x0A   | DS1288x RTC w/NVRAM                      | ds12rtc.asm   |
 
 The time functions to get and set the time (RTCGTM and RTCSTM) require a
 6 byte date/time buffer in the following format. Each byte is BCD 
@@ -1787,7 +1803,7 @@ below enumerates their values.
 | VDADEV_VGA      | 0x04   | HD6445CP4-based Video Display Controller   | vga.asm    |
 | VDADEV_VRC      | 0x05   | VGARC                                      | vrc.asm    |
 | VDADEV_EF       | 0x06   | EF9345                                     | ef.asm     |
-| VDADEV_FV       | 0x07   | S100 FPGA VGA                              | fv.asm     |
+| VDADEV_TVGA     | 0x07   | S100 TRION FPGA VGA                        | tvga.asm   |
 | VDADEV_XOSERA   | 0x08   | Xosera FPGA-based Video Display Controller | xosera.asm |
 
 Depending on the capabilities of the hardware, the use of colors and
@@ -2594,14 +2610,14 @@ The hardware Platform (L) is identified as follows:
 | PLT_MBC       |     13 | NHYODYNE MULTI-BOARD COMPUTER           |
 | PLT_RPH       |     14 | RHYOPHYRE GRAPHICS SBC                  |
 | PLT_Z80RETRO  |     15 | Z80 RETRO COMPUTER                      |
-| PLT_S100      |     16 | S100 COMPUTERS Z180                     |
+| PLT_SZ180     |     16 | S100 COMPUTERS Z180                     |
 | PLT_DUO       |     17 | DUODYNE Z80 SYSTEM                      |
 | PLT_HEATH     |     18 | HEATHKIT H8 Z80 SYSTEM                  |
 | PLT_EPITX     |     19 | Z180 MINI-ITX                           |
 | PLT_MON       |     20 | MONSPUTER (DEPRECATED)                  |
 | PLT_GMZ180    |     21 | GENESIS Z180 SYSTEM                     |
 | PLT_NABU      |     22 | NABU PC W/ ROMWBW OPTION BOARD          |
-| PLT_FZ80      |     23 | S100 FPGA Z80                           |
+| PLT_SZ80      |     23 | S100 COMPUTERS Z80                      |
 | PLT_RCEZ80    |     24 | RCBUS W/ eZ80                           |
 
 For more information on these platforms see $doc_hardware$
@@ -3134,6 +3150,9 @@ performed.  It includes the Boot Bank ID (L), the Boot Disk Unit (D),
 and the Boot Disk Slice (E).  The returned Status (A) is a standard 
 HBIOS result code.
 
+This information is recorded in the HCB.  HCB_BOOTBID is set to the Boot
+Bank ID (L) and HCB_BOOTVOL is set to the BootDisk Unit/Slice (DE).
+
 #### SYSSET Subfunction 0xF3 -- Set CPU Speed (CPUSPD)
 
 | **Entry Parameters**                   | **Returned Values**                    |

Source/Doc/UserGuide.md

@@ -1794,7 +1794,7 @@ The following table shows the disk images available.
 | xxx_nzcom.img     | NZCOM ZCPR 3.4 Operating System      | Yes      |
 | xxx_qpm.img       | QPM Operating System                 | Yes      |
 | xxx_tpascal.img   | Borland Turbo Pascal Compiler        | No       |
-| xxx_ws4.img       | WordStar v4 & ZDE Applications       | No       |
+| xxx_wp.img        | WordStar v4 & ZDE Applications       | No       |
 | xxx_z80asm.img    | Relocating macro assembler for CP/M  | No       |
 | xxx_zpm3.img      | ZPM3 Operating System                | Yes      |
 | xxx_zsdos.img     | ZCPR-DJ & ZSDOS 1.1 Operating System | Yes      |

Source/EZ512/Build.cmd

@@ -25,7 +25,7 @@ srec_cat temp.dat -binary -exclude 0x1F000 0x20000 ez512_mon.bin -binary -offset
 srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\%1.rom -binary -offset 0x24000 -o temp.dat -binary
 move temp.dat ..\..\Binary\%1_hd1k_prefix.dat
 
-copy /b ..\..\Binary\%1_hd1k_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\%1_hd1k_combo.img || exit /b
+copy /b ..\..\Binary\%1_hd1k_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_wp.img ..\..\Binary\%1_hd1k_combo.img || exit /b
 
 ::
 :: The following lines produce a 64K ROM that can be used in the EaZy80-512.

Source/EZ512/Makefile

@@ -2,7 +2,7 @@ DEST=../../Binary
 OTHERS=*.hex *.upd *.cmp
 
 HD1KIMGS = $(DEST)/hd1k_cpm22.img $(DEST)/hd1k_zsdos.img $(DEST)/hd1k_nzcom.img \
-	$(DEST)/hd1k_cpm3.img $(DEST)/hd1k_zpm3.img $(DEST)/hd1k_ws4.img
+	$(DEST)/hd1k_cpm3.img $(DEST)/hd1k_zpm3.img $(DEST)/hd1k_wp.img
 
 ROMS := $(wildcard $(DEST)/RCZ80_ez512_*.upd)
 ROMS := $(patsubst $(DEST)/%.upd,%,$(ROMS))

Source/HBIOS/Build.cmd

@@ -108,10 +108,10 @@ tasm -t%CPUType% -g3 -fFF -dCPM sysconf.asm sysconf.com sysconf_com.lst || exit
 
 :: Create platform specific hardware monitor
 
-if %Platform%==S100 (
-    zxcc slr180 -s100mon/fh || exit /b
-    zxcc mload25 -s100mon || exit /b
-    set HwMon=s100mon.com
+if %Platform%==SZ180 (
+    zxcc slr180 -sz180mon/fh || exit /b
+    zxcc mload25 -sz180mon || exit /b
+    set HwMon=sz180mon.com
 ) else (
     call :asm hwmon || exit /b
     set HwMon=hwmon.bin
@@ -233,9 +233,11 @@ call Build MBC std || exit /b
 call Build ZETA std || exit /b
 call Build ZETA2 std || exit /b
 call Build N8 std || exit /b
+call Build N8PC std || exit /b
 call Build MK4 std || exit /b
-call Build RCZ80 std || exit /b
+call Build RC2014 std || exit /b
 call Build RCEZ80 std || exit /b
+call Build RCZ80 std || exit /b
 call Build RCZ80 kio_std || exit /b
 call Build EZZ80 easy_std || exit /b
 call Build EZZ80 tiny_std || exit /b
@@ -263,14 +265,14 @@ call Build GMZ180 std || exit /b
 call Build DYNO std || exit /b
 call Build RPH std || exit /b
 call Build Z80RETRO std || exit /b
-call Build S100 std || exit /b
+call Build SZ180 std || exit /b
 call Build DUO std || exit /b
 call Build HEATH std || exit /b
 call Build EPITX std || exit /b
 :: call Build MON std || exit /b
 call Build NABU std || exit /b
 call Build SZ80 std || exit /b
-call Build SZ80 fpga || exit /b
+call Build SZ80 t35 || exit /b
 call Build UNA std || exit /b
 call Build MSX std || exit /b
 

Source/HBIOS/Build.ps1

@@ -27,8 +27,8 @@ $ErrorAction = 'Stop'
 # UNA BIOS is simply imbedded, it is not built here.
 #
 
-$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "EZZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON", "NABU", "SZ80", "RCEZ80", "MSX"
-$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100", "EPITX", "GMZ180"
+$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RC2014", "RCZ80", "EZZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON", "NABU", "SZ80", "RCEZ80", "MSX"
+$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "SZ180", "EPITX", "GMZ180","N8PC"
 $PlatformListZ280 = "RCZ280"
 
 #

Source/HBIOS/Build.sh

@@ -17,7 +17,9 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="ZETA"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="ZETA2"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="N8"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="N8PC"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="MK4"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="RC2014"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="RCEZ80"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="RCZ80"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="RCZ80"; ROM_CONFIG="kio_std"; bash Build.sh
@@ -47,14 +49,14 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="DYNO"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="RPH"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="Z80RETRO"; ROM_CONFIG="std"; bash Build.sh
-	ROM_PLATFORM="S100"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="SZ180"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="DUO"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="HEATH"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="EPITX"; ROM_CONFIG="std"; bash Build.sh
 #	ROM_PLATFORM="MON"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="NABU"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="SZ80"; ROM_CONFIG="std"; bash Build.sh
-	ROM_PLATFORM="SZ80"; ROM_CONFIG="fpga"; bash Build.sh
+	ROM_PLATFORM="SZ80"; ROM_CONFIG="t35"; bash Build.sh
 	ROM_PLATFORM="MSX"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="UNA"; ROM_CONFIG="std"; bash Build.sh
 	exit

Source/HBIOS/Config/N8PC_std.asm

@@ -0,0 +1,94 @@
+;
+;==================================================================================================
+;   ROMWBW DEFAULT BUILD SETTINGS FOR N8PC
+;==================================================================================================
+;
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_MASTER.asm			- MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
+;     |
+;     +-> Config/<plt>_std.asm		- BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
+;         |
+;         +-> Config/<plt>_<cust>.asm	- USER: CUSTOM USER BUILD SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
+;
+#DEFINE AUTO_CMD	""		; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED
+#DEFINE DEFSERCFG	SER_38400_8N1 | SER_RTS		; DEFAULT SERIAL CONFIGURATION
+;
+#INCLUDE "cfg_N8PC.asm"
+;
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_PRETTY	.SET	FALSE		; BOOT WITH PRETTY PLATFORM NAME
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+;
+CPUOSC		.SET	9216000	        ; CPU OSC FREQ IN MHZ
+INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+;
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+;
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+;
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+;
+M6242RTCENABLE	.SET	TRUE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+;
+TMSENABLE	.SET	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+;
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+;
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+;
+AY38910ENABLE	.SET	TRUE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+;
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+PKDENABLE	.SET	TRUE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	N8_PPI0		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	1000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+;
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES

Source/HBIOS/Config/RC2014_std.asm

@@ -0,0 +1,112 @@
+;
+;==================================================================================================
+;   ROMWBW DEFAULT BUILD SETTINGS FOR RC2014 Z80
+;==================================================================================================
+;
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_MASTER.asm			- MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
+;     |
+;     +-> Config/<plt>_std.asm		- BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
+;         |
+;         +-> Config/<plt>_<cust>.asm	- USER: CUSTOM USER BUILD SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
+;
+#DEFINE AUTO_CMD	""		; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED
+#DEFINE DEFSERCFG	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL CONFIGURATION
+;
+#INCLUDE "cfg_RC2014.asm"
+;
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_PRETTY	.SET	FALSE		; BOOT WITH PRETTY PLATFORM NAME
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+;
+CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
+;
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
+;
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+LCDENABLE	.SET	TRUE		; ENABLE LCD DISPLAY
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+;
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ACIAENABLE	.SET	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+;
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|MSXUKY]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+;
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+;
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+;
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_PIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W]
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+;
+CHENABLE	.SET	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
+CHNATIVEENABLE	.SET	FALSE		; CH376: ENABLE CH376 NATIVE USB DRIVER
+CHSCSIENABLE	.SET	FALSE		; CH376: ENABLE CH376 NATIVE MASS STORAGE DEVICES (REQUIRES CHNATIVEENABLE)
+CHUFIENABLE	.SET	FALSE		; CH376: ENABLE CH376 NATIVE UFI FLOPPY DISK DEVICES (REQUIRES CHNATIVEENABLE)
+CHNATIVEFORCE	.SET	FALSE		; CH376: DISABLE AUTO-DETECTION OF MODULE - ASSUME ITS INSTALLED
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+;
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+;
+PPAENABLE	.SET	FALSE		; PPA: ENABLE IOMEGA ZIP DRIVE (PPA) DISK DRIVER (PPA.ASM)
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IOMEGA ZIP PLUS DRIVE (IMM) DISK DRIVER (IMM.ASM)
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM)
+;
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+;
+AY38910ENABLE	.SET	TRUE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AY_FORCE	.SET	TRUE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT

Source/HBIOS/Config/SCZ180_sc140_std.asm

@@ -87,5 +87,5 @@ PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 ;
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AYMODE		.SET	AYMODE_LINC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_LINC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT

Source/HBIOS/Config/SCZ180_sc700_std.asm

@@ -70,7 +70,7 @@ ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 ;
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
@@ -88,5 +88,5 @@ SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT

Source/HBIOS/Config/SZ180_std.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW DEFAULT BUILD SETTINGS FOR S100
+;   ROMWBW DEFAULT BUILD SETTINGS FOR S100 Z180
 ;==================================================================================================
 ;
 ; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -45,7 +45,7 @@
 #DEFINE AUTO_CMD	""		; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED
 #DEFINE DEFSERCFG	SER_57600_8N1 | SER_RTS	; DEFAULT SERIAL CONFIGURATION
 ;
-#INCLUDE "cfg_S100.asm"
+#INCLUDE "cfg_SZ180.asm"
 ;
 BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
 BOOT_PRETTY	.SET	FALSE		; BOOT WITH PRETTY PLATFORM NAME
@@ -57,10 +57,18 @@ Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.SET	1		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	3		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
-DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+MMRTCENABLE	.SET	TRUE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+DS12RTCENABLE	.SET	TRUE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
 ;
 ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+DLPSERENABLE	.SET	TRUE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
+DLPSERCNT	.SET	1		; DLPSER: NUMBER OF DEVICES TO DETECT (1-2)
+DLPSER0STAT	.SET	$AA		; DLPSER1: STATUS PORT ADDRESS
+DLPSER0DATA	.SET	$AC		; DLPSER1: DATA PORT ADDRESS
+SCCENABLE	.SET	TRUE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+SCC0ACFG	.SET	SER_19200_8N1	; SCC 0A: SERIAL LINE CONFIG
+SCC0BCFG	.SET	SER_19200_8N1	; SCC 0B: SERIAL LINE CONFIG
 SCONENABLE	.SET	TRUE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
@@ -74,3 +82,5 @@ SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 ESPSDENABLE	.SET	TRUE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ESPSDCNT	.SET	1		; ESPSD: NUMBER OF BOARDS TO DETECT (1-2), 1-2 DEVICES PER BOARD
 ESPSD0DUAL	.SET	TRUE		; ESPSD 0: DUAL INTERFACE BOARD (DUAL SD)
+;
+SCSIENABLE	.SET	TRUE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)

Source/HBIOS/Config/SZ80_std.asm

@@ -43,20 +43,34 @@
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE AUTO_CMD	""		; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED
-#DEFINE DEFSERCFG	SER_9600_8N1 | SER_RTS	; DEFAULT SERIAL CONFIGURATION
+#DEFINE DEFSERCFG	SER_19200_8N1 | SER_RTS	; DEFAULT SERIAL CONFIGURATION
 ;
 #INCLUDE "cfg_SZ80.asm"
 ;
 CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
-RAMSIZE		.SET	1024		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+RAMSIZE		.SET	896		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	0		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 MEMMGR		.SET	MM_SZ80		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON|EZ512|SZ80]
 ;
 FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
 FPLED_IO	.SET	$05		; FP: PORT ADDRESS FOR FP LEDS
 ;
+MMRTCENABLE	.SET	TRUE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+DS12RTCENABLE	.SET	TRUE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+DLPSERENABLE	.SET	TRUE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
+DLPSERCNT	.SET	2		; DLPSER: NUMBER OF DEVICES TO DETECT (1-2)
+DLPSER0STAT	.SET	$E8		; DLPSER0: STATUS PORT ADDRESS
+DLPSER0DATA	.SET	$E9		; DLPSER0: DATA PORT ADDRESS
+DLPSER1STAT	.SET	$AA		; DLPSER1: STATUS PORT ADDRESS
+DLPSER1DATA	.SET	$AC		; DLPSER1: DATA PORT ADDRESS
+SCCENABLE	.SET	TRUE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+SCONENABLE	.SET	TRUE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+;
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 ;
 ESPSDENABLE	.SET	TRUE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ESPSDCNT	.SET	1		; ESPSD: NUMBER OF BOARDS TO DETECT (1-2), 1-2 DEVICES PER BOARD
 ESPSD0DUAL	.SET	TRUE		; ESPSD 0: DUAL INTERFACE BOARD (DUAL SD)
+;
+SCSIENABLE	.SET	TRUE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)

Source/HBIOS/Config/SZ80_t35.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW DEFAULT BUILD SETTINGS FOR S100 FPGA Z80
+;   ROMWBW DEFAULT BUILD SETTINGS FOR S100 T35 FPGA Z80
 ;==================================================================================================
 ;
 ; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -42,30 +42,34 @@
 ; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
-#DEFINE PLATFORM_NAME	"S100 FPGA Z80", " [", CONFIG, "]"	; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES
+#DEFINE PLATFORM_NAME	"S100 TRION Z80", " [", CONFIG, "]"	; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES
 #DEFINE AUTO_CMD	""		; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED
-#DEFINE DEFSERCFG	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL CONFIGURATION
+#DEFINE DEFSERCFG	SER_19200_8N1 | SER_RTS	; DEFAULT SERIAL CONFIGURATION
 ;
 #INCLUDE "cfg_SZ80.asm"
 ;
 CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	0		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 MEMMGR		.SET	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON|EZ512|SZ80]
 ;
 FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
 ;
 DS5RTCENABLE	.SET	TRUE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+DLPSERENABLE	.SET	TRUE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
+DLPSERCNT	.SET	1		; DLPSER: NUMBER OF DEVICES TO DETECT (1-2)
+DLPSER0STAT	.SET	$AA		; DLPSER1: STATUS PORT ADDRESS
+DLPSER0DATA	.SET	$AC		; DLPSER1: DATA PORT ADDRESS
 TSERENABLE	.SET	TRUE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SCCENABLE	.SET	TRUE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+SCONENABLE	.SET	TRUE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 ;
 LPTENABLE	.SET	TRUE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
-FVENABLE	.SET	TRUE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	TRUE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-;
 PPIDECNT	.SET	3		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
 PPIDE0MODE	.SET	PPIDEMODE_STD	; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
 PPIDE0BASE	.SET	$30		; PPIDE 0: PPI REGISTERS BASE ADR
@@ -79,3 +83,5 @@ SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 ESPSDENABLE	.SET	TRUE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ESPSDCNT	.SET	1		; ESPSD: NUMBER OF BOARDS TO DETECT (1-2), 1-2 DEVICES PER BOARD
 ESPSD0DUAL	.SET	TRUE		; ESPSD 0: DUAL INTERFACE BOARD (DUAL SD)
+;
+SCSIENABLE	.SET	TRUE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)

Source/HBIOS/Makefile

@@ -42,8 +42,8 @@ else
 	BIOS=wbw
 endif
 
-ifeq ($(ROM_PLATFORM),S100)
-	HWMON=s100mon.bin
+ifeq ($(ROM_PLATFORM),SZ180)
+	HWMON=sz180mon.bin
 else
 	HWMON=hwmon.bin
 endif
@@ -108,9 +108,9 @@ sysconf.com:
 	@$(TASM) -dCPM sysconf.asm sysconf.com sysconf_com.lst
 	cp $@ $(DEST)/Apps
 
-s100mon.bin:
-	$(ZXCC) $(CPM)/SLR180 -s100mon/FH
-	$(ZXCC) $(CPM)/MLOAD25 -s100mon.bin=s100mon
+sz180mon.bin:
+	$(ZXCC) $(CPM)/SLR180 -sz180mon/FH
+	$(ZXCC) $(CPM)/MLOAD25 -sz180mon.bin=sz180mon
 
 tastybasic.bin:
 	cp ../TastyBasic/src/$@ .
@@ -139,7 +139,7 @@ eastaegg.bin:	build.inc
 updater.bin:	build.inc
 romfonts.bin:	build.inc
 hwmon.bin:	build.inc
-s100mon.bin:	build.inc
+sz180mon.bin:	build.inc
 
 dumps:
 	for i in $(MOREDIFF) ; do \

Source/HBIOS/Makefile.new

@@ -6,7 +6,7 @@ DIST_OBJECTS := \
 	DUO_std SCZ180_sc126 SCZ180_sc130 SCZ180_sc131 SCZ180_sc140 \
 	SCZ180_sc503 SCZ180_sc700 S100_std UNA_std Z80RETRO_std \
 	ZETA_std ZETA2_std HEATH_std EPITX_std GMZ180_std
-#	RCZ80_mt RCZ80_duart MON_std
+#	RCZ80_mt RCZ80_duart MON_std N8PC_std
 
 OBJECTS := $(DIST_OBJECTS)
 OBJECTS := RCZ80_std
@@ -45,9 +45,9 @@ camel80.bin:
 tastybasic.bin:
 	cp ../TastyBasic/src/$@ .
 
-s100mon.bin:
-	$(ZXCC) $(CPM)/SLR180 -s100mon/FH
-	$(ZXCC) $(CPM)/MLOAD25 -s100mon.bin=s100mon
+sz180mon.bin:
+	$(ZXCC) $(CPM)/SLR180 -sz180mon/FH
+	$(ZXCC) $(CPM)/MLOAD25 -sz180mon.bin=sz180mon
 
 %.build.inc:
 	echo $@
@@ -117,7 +117,7 @@ DUO_%.osimg1.bin: NETBOOT=netboot-duo.mod
 	cat camel80.bin $(*F).nascom.bin tastybasic.bin $(*F).game.bin $(*F).eastaegg.bin $(NETBOOT) $(*F).updater.bin $(*F).sysconf.bin $(*F).usrrom.bin >$@
 	srec_cat $@ -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $@ -Binary
 
-S100_%.imgpad2.bin: s100mon.bin
+S100_%.imgpad2.bin: sz180mon.bin
 	cp $< $@
 	srec_cat $@ -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $@ -Binary
 
@@ -143,4 +143,3 @@ UNA_%.rom: UNA_%.osimg.bin UNA_%.hbios_env.sh
 
 %.upd: %.hbios_rom.bin %.osimg.bin %.osimg1.bin %.imgpad2.bin
 	cat $(*F).hbios_rom.bin $(*F).osimg.bin $(*F).osimg1.bin $(*F).imgpad2.bin >$@
-

Source/HBIOS/acia.asm

@@ -56,6 +56,24 @@ ACIA_ACIA       .EQU    1
 ;
 ACIA_RTSON      .EQU    %10111111       ; BIT MASK TO ASSERT RTS
 ACIA_RTSOFF     .EQU    %01000000       ; BIT MASK TO DEASSERT RTS
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_ACIA	.EQU	$
+;
+	.DW	SIZ_ACIA		; MODULE SIZE
+	.DW	ACIA_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+ACIA_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	JP	Z,ACIA_PREINIT		; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,ACIA_INIT		; DO INIT
+	RET				; DONE
+
 ;
 ;
 ;
@@ -743,3 +761,14 @@ ACIA1_CFG:
 #ENDIF
 ;
 ACIA_CFGCNT     .EQU    ($ - ACIA_CFG) / ACIA_CFGSIZ
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_ACIA	.EQU	$
+SIZ_ACIA	.EQU	END_ACIA - ORG_ACIA
+;	
+	MEMECHO	"ACIA occupies "
+	MEMECHO	SIZ_ACIA
+	MEMECHO	" bytes.\n"

Source/HBIOS/asci.asm

@@ -90,6 +90,23 @@ ASCI1_IVT	.EQU	IVT(INT_SER1)
 ;
 #ENDIF
 ;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_ASCI	.EQU	$
+;
+	.DW	SIZ_ASCI		; MODULE SIZE
+	.DW	ASCI_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+ASCI_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	JP	Z,ASCI_PREINIT		; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,ASCI_INIT		; DO INIT
+	RET				; DONE
+;
 ;
 ;
 ASCI_PREINIT:
@@ -899,3 +916,14 @@ ASCI1_CFG:
 #ENDIF
 ;
 ASCI_CFGCNT	.EQU	($ - ASCI_CFG) / ASCI_CFGSIZ
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_ASCI	.EQU	$
+SIZ_ASCI	.EQU	END_ASCI - ORG_ASCI
+;	
+	MEMECHO	"ASCI occupies "
+	MEMECHO	SIZ_ASCI
+	MEMECHO	" bytes.\n"

Source/HBIOS/ay38910.asm

@@ -47,6 +47,14 @@ AY_RIN		.EQU	AY_RSEL
 AY_ACR		.EQU	N8_ACR
 		DEVECHO	"N8"
 #ENDIF
+
+#IF (AYMODE == AYMODE_N8PC)
+AY_RSEL		.EQU	$A0
+AY_RDAT		.EQU	$A1
+AY_RIN		.EQU	AY_RSEL
+AY_ACR		.EQU	N8_ACR
+		DEVECHO	"N8PC"
+#ENDIF
 ;
 #IF (AYMODE == AYMODE_RCZ80)
 AY_RSEL		.EQU	$D8
@@ -114,6 +122,23 @@ AY_R3CHBP	.EQU	$03
 AY_R7ENAB	.EQU	$07
 AY_R8AVOL	.EQU	$08
 ;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_AY	.EQU	$
+;
+	.DW	SIZ_AY			; MODULE SIZE
+	.DW	AY_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+AY_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	;CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	;JP	Z,AY38910_PREINIT	; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,AY38910_INIT		; DO INIT
+	RET				; DONE
+;
 ;======================================================================
 ;
 ;	DRIVER FUNCTION TABLE AND INSTANCE DATA
@@ -171,6 +196,10 @@ AY38910_INIT:
 	PRTS(" MODE=N8$")
 #ENDIF
 ;
+#IF (AYMODE == AYMODE_N8PC)
+	PRTS(" MODE=N8PC$")
+#ENDIF
+;
 #IF (AYMODE == AYMODE_RCZ80)
 	PRTS(" MODE=RCZ80$")
 #ENDIF
@@ -199,7 +228,7 @@ AY38910_INIT:
 	LD	A,AY_RSEL
 	CALL	PRTHEXBYTE
 ;
-#IF ((AYMODE == AYMODE_SCG) | (AYMODE == AYMODE_N8) | (AYMODE == AYMODE_MBC))
+#IF ((AYMODE == AYMODE_SCG) | (AYMODE == AYMODE_N8) | (AYMODE == AYMODE_MBC) | (AYMODE == AYMODE_N8PC))
 	LD	A,$FF			; ACTIVATE DEVICE BIT 4 IS AY RESET CONTROL, BIT 3 IS ACTIVE LED
 	OUT	(AY_ACR),A		; SET INIT AUX CONTROL REG
 #ENDIF
@@ -635,3 +664,14 @@ AY3NOTETBL:
 	.DW	AY_RATIO / 5579		;
 	.DW	AY_RATIO / 5661		;
 	.DW	AY_RATIO / 5743		;
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_AY	.EQU	$
+SIZ_AY	.EQU	END_AY - ORG_AY
+;	
+	MEMECHO	"AY occupies "
+	MEMECHO	SIZ_AY
+	MEMECHO	" bytes.\n"

Source/HBIOS/bqrtc.asm

@@ -94,6 +94,23 @@ BQRTC_BUFSIZE	.EQU	6		; 6 BYTE BUFFER (YYMMDDHHMMSS)
 		DEVECHO	"BQRTC: IO="
 		DEVECHO	BQRTC_BASE
 		DEVECHO	"\n"
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_BQRTC	.EQU	$
+;
+	.DW	SIZ_BQRTC		; MODULE SIZE
+	.DW	BQRTC_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+BQRTC_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	;CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	;JP	Z,BQRTC_PREINIT		; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,BQRTC_INIT		; DO INIT
+	RET				; DONE
 
 ; RTC Device Initialization Entry
 
@@ -395,3 +412,14 @@ BQRTC_BUF_DAY:	.DB	0		; Day
 BQRTC_BUF_HOUR:	.DB	0		; Hour
 BQRTC_BUF_MIN:	.DB	0		; Minute
 BQRTC_BUF_SEC:	.DB	0		; Second
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_BQRTC	.EQU	$
+SIZ_BQRTC	.EQU	END_BQRTC - ORG_BQRTC
+;	
+	MEMECHO	"BQRTC occupies "
+	MEMECHO	SIZ_BQRTC
+	MEMECHO	" bytes.\n"

Source/HBIOS/cfg_DUO.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_DUO		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_DUO		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -169,6 +170,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -178,8 +187,7 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -229,6 +237,8 @@ SIO0BCLK	.SET	(7372800/4)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7
 SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.SET	1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
@@ -238,7 +248,7 @@ CVDUMODE	.SET	CVDUMODE_MBC	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.SET	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_DUO	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_DUO	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	TRUE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
@@ -246,7 +256,7 @@ VGASIZ		.SET	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -337,7 +347,7 @@ PIO0BASE	.SET	$68		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.SET	$6C		; PIO 1: REGISTERS BASE ADR
 ;
 LPTENABLE	.SET	TRUE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.SET	LPTMODE_SPP	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTMODE		.SET	LPTMODE_SPP	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
 LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 LPT0BASE	.SET	$48		; LPT 0: REGISTERS BASE ADR
@@ -366,6 +376,8 @@ SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.SET	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
@@ -383,7 +395,7 @@ SNMODE		.SET	SNMODE_DUO	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_DUO	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_DUO	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
 ;
 SPKENABLE	.SET	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

Source/HBIOS/cfg_DYNO.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -168,6 +169,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -177,8 +186,7 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -248,20 +256,22 @@ SIO1BCLK	.SET	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372
 SIO1BCFG	.SET	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
 SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -350,6 +360,8 @@ SYQENABLE	.SET	FALSE		; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM)
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -363,7 +375,7 @@ SNMODE		.SET	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

Source/HBIOS/cfg_EPITX.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_EPITX	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_EPITX	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -164,6 +165,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -173,8 +182,7 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -244,20 +252,22 @@ SIO1BCLK	.SET	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372
 SIO1BCFG	.SET	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
 SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -347,7 +357,7 @@ PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
 LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 LPT0BASE	.SET	$0C		; LPT 0: REGISTERS BASE ADR
@@ -376,6 +386,8 @@ SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -389,7 +401,7 @@ SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

Source/HBIOS/cfg_EZZ80.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_EZZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_EZZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -168,6 +169,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -177,8 +186,7 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -253,20 +261,22 @@ SIO1BCLK	.SET	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728
 SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
 SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -356,7 +366,7 @@ PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
 LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 LPT0BASE	.SET	$0C		; LPT 0: REGISTERS BASE ADR
@@ -385,6 +395,8 @@ SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -398,7 +410,7 @@ SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

Source/HBIOS/cfg_GMZ180.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_GMZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_GMZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -163,6 +164,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -172,8 +181,7 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -243,20 +251,22 @@ SIO1BCLK	.SET	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372
 SIO1BCFG	.SET	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
 SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -346,7 +356,7 @@ PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
 LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 LPT0BASE	.SET	$18		; LPT 0: REGISTERS BASE ADR
@@ -375,6 +385,8 @@ SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -388,7 +400,7 @@ SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_HEATH.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_HEATH	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_HEATH	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -168,6 +169,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -177,8 +186,7 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -253,20 +261,22 @@ SIO1BCLK	.SET	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728
 SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
 SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	TRUE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -346,7 +356,7 @@ PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
 LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 LPT0BASE	.SET	$0C		; LPT 0: REGISTERS BASE ADR
@@ -375,6 +385,8 @@ SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -388,7 +400,7 @@ SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	TRUE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_MSX	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_MSX	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;

Source/HBIOS/cfg_MASTER.asm

@@ -49,8 +49,10 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_NONE	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.EQU	PLT_NONE	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.EQU	CPU_NONE	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.EQU	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
+TURBOZ80DISPRT	.EQU	$00		; DUMMY I/O PORT ADDRESS TO READ FROM, TO DISABLE TURBO BOOST FOR NEXT 31 CLOCK TICKS
 NMOSCPU		.EQU	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.EQU	BIOS_NONE	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -207,6 +209,14 @@ DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 PCRTCENABLE	.EQU	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
 PCRTC_BASE	.EQU	$C0		; Default port for PCRTC, like DSRTC.
 ;
+MMRTCENABLE	.EQU	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.EQU	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+DS12RTC_BASE	.EQU	$70		; DS12RTC: I/O BASE ADDRESS
+;
+M6242RTCENABLE	.EQU	TRUE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+M6242RTC_BASE	.EQU	$A0		; M6242RTC: I/O BASE ADDRESS
+;
 SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
@@ -216,8 +226,12 @@ SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.EQU	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.EQU	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.EQU	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
+DLPSERCNT	.EQU	1		; DLPSER: NUMBER OF DEVICES TO DETECT (1-2)
+DLPSER0STAT	.EQU	$FF		; DLPSER0: STATUS PORT ADDRESS
+DLPSER0DATA	.EQU	$FF		; DLPSER0: DATA PORT ADDRESS
+DLPSER1STAT	.EQU	$FF		; DLPSER1: STATUS PORT ADDRESS
+DLPSER1DATA	.EQU	$FF		; DLPSER1: DATA PORT ADDRESS
 ;
 TSERENABLE	.EQU	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.EQU	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -302,6 +316,28 @@ SIO1BCLK	.EQU	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728
 SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
 SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.EQU	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+SCCDEBUG	.EQU	FALSE		; SCC: ENABLE DEBUG OUTPUT
+SCCBOOT		.EQU	0		; SCC: REBOOT ON RCV CHAR (0=DISABLED)
+SCCCNT		.EQU	2		; SCC: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SCCINTS		.EQU	FALSE		; SCC: INCLUDE SCC INTERRUPT SUPPORT UNDER IM1/2/3
+SCC0MODE	.EQU	SCCMODE_SZ80	; SCC 0: CHIP TYPE: SCCMODE_[STD|SZ80]
+SCC0BASE	.EQU	$FF		; SCC 0: REGISTERS BASE ADR
+SCC0ACLK	.EQU	4915200		; SCC 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC0ACFG	.EQU	DEFSERCFG	; SCC 0A: SERIAL LINE CONFIG
+SCC0ACTCC	.EQU	-1		; SCC 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SCC0BCLK	.EQU	4915200		; SCC 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC0BCFG	.EQU	DEFSERCFG	; SCC 0B: SERIAL LINE CONFIG
+SCC0BCTCC	.EQU	-1		; SCC 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SCC1MODE	.EQU	SCCMODE_SZ80	; SCC 1: CHIP TYPE: SIOMODE_[STD|SZ80]
+SCC1BASE	.EQU	$FF		; SCC 1: REGISTERS BASE ADR
+SCC1ACLK	.EQU	4915200		; SCC 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC1ACFG	.EQU	DEFSERCFG	; SCC 1A: SERIAL LINE CONFIG
+SCC1ACTCC	.EQU	-1		; SCC 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SCC1BCLK	.EQU	4915200		; SCC 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC1BCFG	.EQU	DEFSERCFG	; SCC 1B: SERIAL LINE CONFIG
+SCC1BCTCC	.EQU	-1		; SCC 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
 XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
@@ -313,7 +349,7 @@ GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 GDCMODE		.EQU	GDCMODE_RPH	; GDC: GDC MODE: GDCMODE_[NONE|ECB|RPH]
 GDCMON		.EQU	GDCMON_EGA      ; GDC: GDC MONITOR SETUP: GDCMON_[NONE|CGA|EGA]
 TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
@@ -321,7 +357,7 @@ VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.EQU	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 XOSENABLE	.EQU	FALSE		; XOSERA: ENABLE XOSERA VIDEO DRIVERS (XOSERA.ASM)
 XOS_BASE	.EQU	$20		; XOSERA: I/O BASE ADDRESS (REQUIRES 32 BYTES)
 XOSSIZ		.EQU	V80X30		; XOSERA: DISPLAY FORMAT [V80X30|V80X60]
@@ -425,7 +461,7 @@ PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
 ;
 LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.EQU	LPTMODE_NONE	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTMODE		.EQU	LPTMODE_NONE	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
 LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 LPT0BASE	.EQU	$E8		; LPT 0: REGISTERS BASE ADR
@@ -461,6 +497,13 @@ ESPSD0DUAL	.EQU	TRUE		; ESPSD 0: DUAL INTERFACE BOARD (DUAL SD)
 ESPSD1BASE	.EQU	$82		; ESPSD 1: ESP32 INTERFACE IO BASE ADR
 ESPSD1DUAL	.EQU	TRUE		; ESPSD 1: DUAL INTERFACE BOARD (DUAL SD)
 ;
+SCSIENABLE	.EQU	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+SCSITRACE	.EQU	1		; SCSI: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SCSICNT		.EQU	2		; SCSI: NUMBER OF TARGET DEVICES (1-2)
+SCSI_TID	.EQU	0		; SCSI: TARGET DEVICE ID (0-6)
+SCSI0_LUN	.EQU	0		; SCSI 0: TARGET LUN
+SCSI1_LUN	.EQU	1		; SCSI 1: TARGET LUN
+;
 PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
@@ -479,7 +522,7 @@ SNMODE		.EQU	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 AY_FORCE	.EQU	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
 ;
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
@@ -533,4 +576,3 @@ CHNATIVEEZ80	.EQU	FALSE		; CH376: DELEGATE USB DRIVERS TO EZ80'S FIRMWARE
 _CH376_DATA_PORT	.EQU	$FF88	; CH376: DATA PORT
 _CH376_COMMAND_PORT	.EQU	$FF89	; CH376: COMMAND PORT
 _USB_MODULE_LEDS	.EQU	$FF8A	; CH376: LED CONTROL PORT
-

Source/HBIOS/cfg_MBC.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -162,6 +163,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -171,8 +180,7 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -222,6 +230,8 @@ SIO0BCLK	.SET	(4915200/8)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7
 SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
@@ -231,7 +241,7 @@ CVDUMODE	.SET	CVDUMODE_MBC	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.SET	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_MBC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_MBC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	TRUE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
@@ -239,7 +249,7 @@ VGASIZ		.SET	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -325,7 +335,7 @@ PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.SET	LPTMODE_SPP	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTMODE		.SET	LPTMODE_SPP	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
 LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 LPT0BASE	.SET	$E8		; LPT 0: REGISTERS BASE ADR
@@ -354,6 +364,8 @@ SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.SET	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
@@ -371,7 +383,7 @@ SNMODE		.SET	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_MBC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_MBC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 ;
 SPKENABLE	.SET	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 SPKPORT		.SET	RTCIO		; SPK: THE PORT WITH THE SPEAKER IO BIT

Source/HBIOS/cfg_MK4.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -168,6 +169,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -177,8 +186,7 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -233,6 +241,8 @@ SIO0BCLK	.SET	(4915200/8)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7
 SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
@@ -242,7 +252,7 @@ CVDUMODE	.SET	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.SET	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
@@ -250,7 +260,7 @@ VGASIZ		.SET	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -347,6 +357,8 @@ SYQENABLE	.SET	FALSE		; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM)
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.SET	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
@@ -365,7 +377,7 @@ SNMODE		.SET	SNMODE_VGM	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

Source/HBIOS/cfg_MON.asm

@@ -51,8 +51,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_MON		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_MON		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -165,6 +166,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -174,8 +183,7 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -250,20 +258,22 @@ SIO1BCLK	.SET	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728
 SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
 SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -353,7 +363,7 @@ PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
 LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 LPT0BASE	.SET	$0C		; LPT 0: REGISTERS BASE ADR
@@ -382,6 +392,8 @@ SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -395,7 +407,7 @@ SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

Source/HBIOS/cfg_MSX.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_MSX		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80|MSX]
+PLATFORM	.SET	PLT_MSX		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80|MSX|N8PC]
 CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	TRUE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -171,6 +172,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -180,8 +189,7 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -256,20 +264,22 @@ SIO1BCLK	.SET	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728
 SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
 SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_MSXMKY	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_MSXMKY	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	TRUE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9938/V9958
 TMSTIMENABLE	.SET	TRUE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	FALSE		; MD: ENABLE ROM DISK
@@ -360,7 +370,7 @@ PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
 LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 LPT0BASE	.SET	$90		; LPT 0: REGISTERS BASE ADR
@@ -389,6 +399,8 @@ SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -402,7 +414,7 @@ SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	TRUE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_MSX	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_MSX	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

Source/HBIOS/cfg_N8.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -168,7 +169,15 @@ SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
 DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
-DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
 ;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
@@ -179,8 +188,7 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -235,6 +243,8 @@ SIO0BCLK	.SET	(4915200/8)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7
 SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
@@ -244,7 +254,7 @@ CVDUMODE	.SET	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.SET	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
@@ -252,7 +262,7 @@ VGASIZ		.SET	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -349,6 +359,8 @@ SYQENABLE	.SET	FALSE		; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM)
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.SET	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
@@ -367,7 +379,7 @@ SNMODE		.SET	SNMODE_VGM	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

Source/HBIOS/cfg_N8PC.asm

@@ -0,0 +1,391 @@
+;
+;==================================================================================================
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: N8PC
+;==================================================================================================
+;
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_MASTER.asm			- MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
+;     |
+;     +-> Config/<plt>_std.asm		- BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
+;         |
+;         +-> Config/<plt>_<cust>.asm	- USER: CUSTOM USER BUILD SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
+;
+#DEFINE PLATFORM_NAME	"N8PC", " [", CONFIG, "]"	; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE
+#DEFINE AUTO_CMD	""		; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED
+#DEFINE DEFSERCFG	SER_38400_8N1 | SER_RTS		; DEFAULT SERIAL CONFIGURATION
+;
+#INCLUDE "cfg_MASTER.asm"
+;
+PLATFORM	.SET	PLT_N8PC	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
+CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
+NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	FALSE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+BOOT_PRETTY	.SET	FALSE		; BOOT WITH PRETTY PLATFORM NAME
+BT_REC_TYPE	.SET	BT_REC_NONE	; BOOT RECOVERY METHOD TO USE: BT_REC_[NONE|FORCE|SBCB0|SBC1B|SBCRI|DUORI]
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+STRICTPART	.SET	TRUE		; ENFORCE STRICT PARTITION TABLE VALIDATION
+;
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	9216000		; CPU OSC FREQ IN MHZ
+INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+;
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMFONTS	.SET	FALSE		; LOAD FONTS FROM ROM
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON|EZ512]
+RAMBIAS		.SET	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+;
+Z180_BASE	.SET	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.SET	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
+;
+N8_PPI0		.SET	$84		; N8: FIRST PARALLEL PORT REGISTERS BASE ADR
+N8_ACR		.SET	$94		; N8: AUXILLARY CONTROL REGISTER (ACR) ADR
+N8_RMAP		.SET	$96		; N8: ROM PAGE REGISTER ADR
+N8_DEFACR	.SET	$1B		; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
+;
+RTCIO		.SET	$88		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$B0		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
+;
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+;
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$88		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	TRUE		; FP: SWITCH BITS ARE INVERTED
+;
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
+LEDENABLE	.SET	TRUE 		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	N8_ACR		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	N8_PPI0		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	N8_PPI0		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+GM7303ENABLE	.SET	FALSE		; ENABLES THE GM7303 BOARD WITH 16X2 LCD
+;
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDINTS		.SET	FALSE		; ENABLE KBD (PS2) KEYBOARD INTERRUPTS
+;
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
+;
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	TRUE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+M6242RTC_BASE	.SET	$B0		; M6242RTC: I/O BASE ADDRESS
+;
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+;
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	5		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	TRUE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$80		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$C0		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$C8		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$D0		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$D8		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+;
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.SET	FALSE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+ASCISWAP	.SET	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.SET	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
+ASCI0CFG	.SET	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
+ASCI1CFG	.SET	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
+;
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+;
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$B0		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	(4915200/8)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+VDUSIZ		.SET	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+CVDUMODE	.SET	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
+CVDUMON		.SET	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_N8PC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
+TMS80COLS	.SET	TRUE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VGASIZ		.SET	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
+;
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_N8	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFCNT		.SET	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
+;
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_DIO	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE0BASE	.SET	$20		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$20		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$28		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	FALSE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	FALSE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+;
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0MODE	.SET	PPIDEMODE_STD	; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
+PPIDE0BASE	.SET	N8_PPI0		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1MODE	.SET	PPIDEMODE_STD	; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
+PPIDE1BASE	.SET	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2MODE	.SET	PPIDEMODE_STD	; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
+PPIDE2BASE	.SET	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 2B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
+SDPPIBASE	.SET	N8_PPI0		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+;
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+;
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPBASE		.SET	N8_PPI0		; PPP: PPI REGISTERS BASE ADDRESS
+PPPSDENABLE	.SET	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
+PPPSDTRACE	.SET	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPPCONENABLE	.SET	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
+;
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
+;
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+;
+PPAENABLE	.SET	FALSE		; PPA: ENABLE IOMEGA ZIP DRIVE (PPA) DISK DRIVER (PPA.ASM)
+;
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IOMEGA ZIP PLUS DRIVE (IMM) DISK DRIVER (IMM.ASM)
+;
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM)
+;
+ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
+;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO4BASE	.SET	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIOZBASE	.SET	$88		; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIOSBASE	.SET	N8_PPI0		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
+;
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFBASE		.SET	$0C		; UF: REGISTERS BASE ADR
+;
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.SET	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_VGM	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
+;
+AY38910ENABLE	.SET	TRUE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	3579545		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_N8PC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
+AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
+;
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+;
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_NABU.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_NABU	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_NABU	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -168,6 +169,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -177,8 +186,7 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -253,20 +261,22 @@ SIO1BCLK	.SET	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728
 SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
 SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_NABU	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_NABU	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	TRUE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	TRUE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -356,7 +366,7 @@ PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
 LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 LPT0BASE	.SET	$0C		; LPT 0: REGISTERS BASE ADR
@@ -385,6 +395,8 @@ SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -398,7 +410,7 @@ SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	TRUE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_NABU	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_NABU	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

Source/HBIOS/cfg_RC2014.asm

@@ -0,0 +1,426 @@
+;
+;==================================================================================================
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: RC2014
+;==================================================================================================
+;
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_MASTER.asm			- MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
+;     |
+;     +-> Config/<plt>_std.asm		- BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
+;         |
+;         +-> Config/<plt>_<cust>.asm	- USER: CUSTOM USER BUILD SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
+;
+#DEFINE PLATFORM_NAME	"RC2014", " [", CONFIG, "]"	; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE
+#DEFINE AUTO_CMD	""		; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED
+#DEFINE DEFSERCFG	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL CONFIGURATION
+;
+#INCLUDE "cfg_MASTER.asm"
+;
+PLATFORM	.SET	PLT_RC2014	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
+NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+BOOT_PRETTY	.SET	FALSE		; BOOT WITH PRETTY PLATFORM NAME
+BT_REC_TYPE	.SET	BT_REC_NONE	; BOOT RECOVERY METHOD TO USE: BT_REC_[NONE|FORCE|SBCB0|SBC1B|SBCRI|DUORI]
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+STRICTPART	.SET	TRUE		; ENFORCE STRICT PARTITION TABLE VALIDATION
+;
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
+INTMODE		.SET	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+;
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMFONTS	.SET	TRUE		; LOAD FONTS FROM ROM
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON|EZ512]
+MPGSEL_0	.SET	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.SET	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.SET	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.SET	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.SET	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+;
+RTCIO		.SET	$C0		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.SET	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.SET	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.SET	2		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
+CTCOSC		.SET	CPUOSC		; CTC CLOCK FREQUENCY
+;
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
+PCFCLK		.SET	PCFCLK_8	; PCF CLOCK BASE: PCFCLK_[3|443|6|8|12]
+PCFTRNS		.SET	PCFTRNS_90	; PCF TRANSFER SPEED: PCFTRNS_[90|45|11|15]
+;
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZDIV		.SET	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
+;
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGIO		.SET	$6F		; WATCHDOG REGISTER ADR
+;
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
+;
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+GM7303ENABLE	.SET	FALSE		; ENABLES THE GM7303 BOARD WITH 16X2 LCD
+;
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDINTS		.SET	FALSE		; ENABLE KBD (PS2) KEYBOARD INTERRUPTS
+;
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
+;
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.SET	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.SET	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.SET	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.SET	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.SET	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+;
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$80		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$88		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$A0		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$A8		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+;
+ASCIENABLE	.SET	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+;
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIADEBUG	.SET	FALSE		; ACIA: ENABLE DEBUG OUTPUT
+ACIACNT		.SET	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
+ACIA0BASE	.SET	$80		; ACIA 0: REGISTERS BASE ADR
+ACIA0CLK	.SET	CPUOSC		; ACIA 0: OSC FREQ IN HZ
+ACIA0DIV	.SET	1		; ACIA 0: SERIAL CLOCK DIVIDER
+ACIA0CFG	.SET	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIA1BASE	.SET	$40		; ACIA 1: REGISTERS BASE ADR
+ACIA1CLK	.SET	CPUOSC		; ACIA 1: OSC FREQ IN HZ
+ACIA1DIV	.SET	1		; ACIA 1: SERIAL CLOCK DIVIDER
+ACIA1CFG	.SET	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
+;
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.SET	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.SET	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.SET	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.SET	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.SET	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.SET	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
+;
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+;
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE0BASE	.SET	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_RC	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE1BASE	.SET	$18		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_RC	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE2BASE	.SET	$20		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+;
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0MODE	.SET	PPIDEMODE_STD	; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
+PPIDE0BASE	.SET	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1MODE	.SET	PPIDEMODE_STD	; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
+PPIDE1BASE	.SET	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2MODE	.SET	PPIDEMODE_STD	; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
+PPIDE2BASE	.SET	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 2B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_PIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+;
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.SET	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.SET	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.SET	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.SET	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.SET	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.SET	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.SET	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.SET	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.SET	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.SET	FALSE		; CH 1: ENABLE SD DISK
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+;
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+;
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+;
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
+;
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
+LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.SET	$0C		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.SET	$00		; LPT 1: REGISTERS BASE ADR
+;
+PPAENABLE	.SET	FALSE		; PPA: ENABLE IOMEGA ZIP DRIVE (PPA) DISK DRIVER (PPA.ASM)
+PPACNT		.SET	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.SET	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.SET	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.SET	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.SET	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+;
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IOMEGA ZIP PLUS DRIVE (IMM) DISK DRIVER (IMM.ASM)
+IMMCNT		.SET	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.SET	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.SET	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.SET	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.SET	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+;
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM)
+SYQCNT		.SET	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.SET	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.SET	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.SET	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+;
+ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
+;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+;
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
+;
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
+AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
+;
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+;
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_RCEZ80.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_RCEZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_RCEZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_EZ80	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -166,6 +167,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -175,8 +184,7 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -251,20 +259,22 @@ SIO1BCLK	.SET	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728
 SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
 SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|MSXUKY]
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|MSXUKY|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -357,7 +367,7 @@ PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
 LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 LPT0BASE	.SET	$0C		; LPT 0: REGISTERS BASE ADR
@@ -386,6 +396,8 @@ SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -399,7 +411,7 @@ SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.SET	CPUOSC/4	; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

Source/HBIOS/cfg_RCZ180.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -146,7 +147,7 @@ KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 KBDINTS		.SET	FALSE		; ENABLE KBD (PS2) KEYBOARD INTERRUPTS
 ;
-DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W]
 DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
@@ -168,6 +169,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -177,8 +186,7 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -248,20 +256,22 @@ SIO1BCLK	.SET	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372
 SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
 SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -354,7 +364,7 @@ PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
 LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 LPT0BASE	.SET	$0C		; LPT 0: REGISTERS BASE ADR
@@ -383,6 +393,8 @@ SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -396,7 +408,7 @@ SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

Source/HBIOS/cfg_RCZ280.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z280	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -168,6 +169,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -177,8 +186,7 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -258,20 +266,22 @@ SIO1BCLK	.SET	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372
 SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
 SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -364,7 +374,7 @@ PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
 LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 LPT0BASE	.SET	$0C		; LPT 0: REGISTERS BASE ADR
@@ -393,6 +403,8 @@ SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -406,7 +418,7 @@ SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

Source/HBIOS/cfg_RCZ80.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -149,7 +150,7 @@ KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 KBDINTS		.SET	FALSE		; ENABLE KBD (PS2) KEYBOARD INTERRUPTS
 ;
-DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W]
 DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
@@ -171,6 +172,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -180,8 +189,7 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -256,20 +264,22 @@ SIO1BCLK	.SET	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728
 SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
 SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -359,7 +369,7 @@ PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
 LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 LPT0BASE	.SET	$0C		; LPT 0: REGISTERS BASE ADR
@@ -388,6 +398,8 @@ SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -401,7 +413,7 @@ SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

Source/HBIOS/cfg_RPH.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -168,6 +169,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -177,8 +186,7 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -221,6 +229,8 @@ ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
 SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
@@ -232,7 +242,7 @@ GDCENABLE	.SET	TRUE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 GDCMODE		.SET	GDCMODE_RPH	; GDC: GDC MODE: GDCMODE_[NONE|ECB|RPH]
 GDCMON		.SET	GDCMON_EGA      ; GDC: GDC MONITOR SETUP: GDCMON_[NONE|CGA|EGA]
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
@@ -240,7 +250,7 @@ VGASIZ		.SET	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -330,6 +340,8 @@ SYQENABLE	.SET	FALSE		; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM)
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.SET	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
@@ -348,7 +360,7 @@ SNMODE		.SET	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

Source/HBIOS/cfg_SBC.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -163,6 +164,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -172,8 +181,7 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -223,6 +231,8 @@ SIO0BCLK	.SET	(4915200/8)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7
 SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
@@ -232,7 +242,7 @@ CVDUMODE	.SET	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
 CVDUMON		.SET	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
@@ -240,7 +250,7 @@ VGASIZ		.SET	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -338,6 +348,8 @@ SYQENABLE	.SET	FALSE		; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM)
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO4BASE	.SET	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
@@ -356,7 +368,7 @@ SNMODE		.SET	SNMODE_VGM	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

Source/HBIOS/cfg_SCZ180.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -168,6 +169,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -177,8 +186,7 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -248,20 +256,22 @@ SIO1BCLK	.SET	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372
 SIO1BCFG	.SET	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
 SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -351,7 +361,7 @@ PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
 LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 LPT0BASE	.SET	$18		; LPT 0: REGISTERS BASE ADR
@@ -380,6 +390,8 @@ SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -394,7 +406,7 @@ SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
 AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

Source/HBIOS/cfg_SZ180.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: S100
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: S100 Z180
 ;==================================================================================================
 ;
 ; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -42,15 +42,16 @@
 ; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
 ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
-#DEFINE PLATFORM_NAME	"S100", " [", CONFIG, "]"	; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES
+#DEFINE PLATFORM_NAME	"S100 Z180", " [", CONFIG, "]"	; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE
 #DEFINE AUTO_CMD	""		; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED
 #DEFINE DEFSERCFG	SER_57600_8N1 | SER_RTS	; DEFAULT SERIAL CONFIGURATION
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_S100	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_SZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -94,9 +95,6 @@ KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
 KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
 CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
-CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
 ;
@@ -107,17 +105,17 @@ SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
 FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_IO	.SET	$FF		; FP: PORT ADDRESS FOR FP LEDS
 FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
 FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
 FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_IO		.SET	$FF		; FP: PORT ADDRESS FOR FP SWITCHES
 FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
 DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
 LEDENABLE	.SET	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.SET	LEDMODE_SC	; LEDMODE_[STD|SC|RTC|NABU]
+LEDMODE		.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
 LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
 LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
@@ -146,7 +144,7 @@ KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 KBDINTS		.SET	FALSE		; ENABLE KBD (PS2) KEYBOARD INTERRUPTS
 ;
-DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W]
 DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
@@ -168,17 +166,22 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
-SSERDATA	.SET	$FF		; SSER: DATA PORT
-SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
 ;
-PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+;
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
+DLPSERCNT	.SET	1		; DLPSER: NUMBER OF DEVICES TO DETECT (1-2)
+DLPSER0STAT	.SET	$FF		; DLPSER0: STATUS PORT ADDRESS
+DLPSER0DATA	.SET	$FF		; DLPSER0: DATA PORT ADDRESS
+DLPSER1STAT	.SET	$FF		; DLPSER1: STATUS PORT ADDRESS
+DLPSER1DATA	.SET	$FF		; DLPSER1: DATA PORT ADDRESS
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -227,26 +230,28 @@ Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
 SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.SET	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.SET	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.SET	$80		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.SET	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.SET	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.SET	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.SET	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.SET	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO1BASE	.SET	$84		; SIO 1: REGISTERS BASE ADR
-SIO1ACLK	.SET	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1ACFG	.SET	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
-SIO1ACTCC	.SET	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1BCLK	.SET	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1BCFG	.SET	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
-SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+SCCDEBUG	.SET	FALSE		; SCC: ENABLE DEBUG OUTPUT
+SCCBOOT		.SET	0		; SCC: REBOOT ON RCV CHAR (0=DISABLED)
+SCCCNT		.SET	1		; SCC: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SCCINTS		.SET	FALSE		; SCC: INCLUDE SCC INTERRUPT SUPPORT UNDER IM1/2/3
+SCC0MODE	.SET	SCCMODE_SZ80	; SCC 0: CHIP TYPE: SCCMODE_[STD|SZ80]
+SCC0BASE	.SET	$A0		; SCC 0: REGISTERS BASE ADR
+SCC0ACLK	.SET	4915200		; SCC 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC0ACFG	.SET	DEFSERCFG	; SCC 0A: SERIAL LINE CONFIG
+SCC0ACTCC	.SET	-1		; SCC 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SCC0BCLK	.SET	4915200		; SCC 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC0BCFG	.SET	DEFSERCFG	; SCC 0B: SERIAL LINE CONFIG
+SCC0BCTCC	.SET	-1		; SCC 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SCC1MODE	.SET	SCCMODE_SZ80	; SCC 1: CHIP TYPE: SIOMODE_[STD|SZ80]
+SCC1BASE	.SET	$FF		; SCC 1: REGISTERS BASE ADR
+SCC1ACLK	.SET	4915200		; SCC 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC1ACFG	.SET	DEFSERCFG	; SCC 1A: SERIAL LINE CONFIG
+SCC1ACTCC	.SET	-1		; SCC 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SCC1BCLK	.SET	4915200		; SCC 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC1BCFG	.SET	DEFSERCFG	; SCC 1B: SERIAL LINE CONFIG
+SCC1BCTCC	.SET	-1		; SCC 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
@@ -254,14 +259,14 @@ VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -317,7 +322,7 @@ PPIDE2BASE	.SET	$00		; PPIDE 2: PPI REGISTERS BASE ADR
 PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.SET	FALSE		; PPIDE 2B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDMODE		.SET	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
 SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
@@ -341,7 +346,7 @@ PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTMODE		.SET	LPTMODE_SPP	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
 LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 LPT0BASE	.SET	$18		; LPT 0: REGISTERS BASE ADR
@@ -377,6 +382,13 @@ ESPSD0DUAL	.SET	TRUE		; ESPSD 0: DUAL INTERFACE BOARD (DUAL SD)
 ESPSD1BASE	.SET	$82		; ESPSD 1: ESP32 INTERFACE IO BASE ADR
 ESPSD1DUAL	.SET	TRUE		; ESPSD 1: DUAL INTERFACE BOARD (DUAL SD)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+SCSITRACE	.SET	1		; SCSI: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SCSICNT		.SET	2		; SCSI: NUMBER OF TARGET DEVICES (1-2)
+SCSI_TID	.SET	0		; SCSI: TARGET DEVICE ID (0-6)
+SCSI0_LUN	.SET	0		; SCSI 0: TARGET LUN
+SCSI1_LUN	.SET	1		; SCSI 1: TARGET LUN
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -384,15 +396,8 @@ PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-SN76489CHNOUT	.SET	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
-AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
-AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
@@ -401,4 +406,3 @@ DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
 DMAMODE		.SET	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_SZ80.asm

@@ -45,12 +45,13 @@
 #DEFINE PLATFORM_NAME	"S100 Z80", " [", CONFIG, "]"	; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE
 #DEFINE AUTO_CMD	""		; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED
-#DEFINE DEFSERCFG	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL CONFIGURATION
+#DEFINE DEFSERCFG	SER_19200_8N1 | SER_RTS	; DEFAULT SERIAL CONFIGURATION
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_SZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_SZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -87,31 +88,21 @@ KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
 KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
 CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
-CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
-CTCMODE		.SET	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
-CTCPRE		.SET	256		; PRESCALE CONSTANT (1-256)
-CTCPRECH	.SET	2		; PRESCALE CHANNEL (0-3)
-CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
-CTCOSC		.SET	CPUOSC		; CTC CLOCK FREQUENCY
 ;
 PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
 ;
 EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
-SKZDIV		.SET	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
 ;
 WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
-WDOGIO		.SET	$6E		; WATCHDOG REGISTER ADR
 ;
 FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
 FPLED_IO	.SET	$FF		; FP: PORT ADDRESS FOR FP LEDS
 FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
 FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
 FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_IO		.SET	$FF		; FP: PORT ADDRESS FOR FP SWITCHES
 FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
 DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
@@ -168,17 +159,23 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.SET	$34		; SSER: STATUS PORT
-SSERDATA	.SET	$35		; SSER: DATA PORT
-SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.SET	TRUE		; SSER: OUTPUT READY BIT INVERTED
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
 ;
-PLDSERENABLE	.SET	TRUE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
-PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+DS12RTC_BASE	.SET	$70		; DS12RTC: I/O BASE ADDRESS
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+;
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
+DLPSERCNT	.SET	1		; DLPSER: NUMBER OF DEVICES TO DETECT (1-2)
+DLPSER0STAT	.SET	$FF		; DLPSER0: STATUS PORT ADDRESS
+DLPSER0DATA	.SET	$FF		; DLPSER0: DATA PORT ADDRESS
+DLPSER1STAT	.SET	$FF		; DLPSER1: STATUS PORT ADDRESS
+DLPSER1DATA	.SET	$FF		; DLPSER1: DATA PORT ADDRESS
 ;
 TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
 TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
@@ -220,38 +217,30 @@ ASCIENABLE	.SET	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
 ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
-ACIADEBUG	.SET	FALSE		; ACIA: ENABLE DEBUG OUTPUT
-ACIACNT		.SET	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
-ACIA0BASE	.SET	$80		; ACIA 0: REGISTERS BASE ADR
-ACIA0CLK	.SET	CPUOSC		; ACIA 0: OSC FREQ IN HZ
-ACIA0DIV	.SET	1		; ACIA 0: SERIAL CLOCK DIVIDER
-ACIA0CFG	.SET	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
-ACIA1BASE	.SET	$40		; ACIA 1: REGISTERS BASE ADR
-ACIA1CLK	.SET	CPUOSC		; ACIA 1: OSC FREQ IN HZ
-ACIA1DIV	.SET	1		; ACIA 1: SERIAL CLOCK DIVIDER
-ACIA1CFG	.SET	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
 ;
 SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.SET	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.SET	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.SET	$80		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.SET	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.SET	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.SET	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.SET	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO1BASE	.SET	$84		; SIO 1: REGISTERS BASE ADR
-SIO1ACLK	.SET	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1ACFG	.SET	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
-SIO1ACTCC	.SET	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1BCLK	.SET	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
-SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+SCCDEBUG	.SET	FALSE		; SCC: ENABLE DEBUG OUTPUT
+SCCBOOT		.SET	0		; SCC: REBOOT ON RCV CHAR (0=DISABLED)
+SCCCNT		.SET	1		; SCC: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SCCINTS		.SET	FALSE		; SCC: INCLUDE SCC INTERRUPT SUPPORT UNDER IM1/2/3
+SCC0MODE	.SET	SCCMODE_SZ80	; SCC 0: CHIP TYPE: SCCMODE_[STD|SZ80]
+SCC0BASE	.SET	$A0		; SCC 0: REGISTERS BASE ADR
+SCC0ACLK	.SET	4915200		; SCC 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC0ACFG	.SET	DEFSERCFG	; SCC 0A: SERIAL LINE CONFIG
+SCC0ACTCC	.SET	-1		; SCC 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SCC0BCLK	.SET	4915200		; SCC 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC0BCFG	.SET	DEFSERCFG	; SCC 0B: SERIAL LINE CONFIG
+SCC0BCTCC	.SET	-1		; SCC 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SCC1MODE	.SET	SCCMODE_SZ80	; SCC 1: CHIP TYPE: SIOMODE_[STD|SZ80]
+SCC1BASE	.SET	$FF		; SCC 1: REGISTERS BASE ADR
+SCC1ACLK	.SET	4915200		; SCC 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC1ACFG	.SET	DEFSERCFG	; SCC 1A: SERIAL LINE CONFIG
+SCC1ACTCC	.SET	-1		; SCC 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SCC1BCLK	.SET	4915200		; SCC 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC1BCFG	.SET	DEFSERCFG	; SCC 1B: SERIAL LINE CONFIG
+SCC1BCTCC	.SET	-1		; SCC 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
@@ -259,14 +248,14 @@ VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.SET	TRUE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	FALSE		; MD: ENABLE ROM DISK
@@ -331,16 +320,6 @@ SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
 SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
 CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
-CHTRACE		.SET	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHUSBTRACE	.SET	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHSDTRACE	.SET	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.SET	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.SET	$3E		; CH 0: BASE I/O ADDRESS
-CH0USBENABLE	.SET	TRUE		; CH 0: ENABLE USB DISK
-CH0SDENABLE	.SET	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.SET	$3C		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.SET	TRUE		; CH 1: ENABLE USB DISK
-CH1SDENABLE	.SET	FALSE		; CH 1: ENABLE SD DISK
 ;
 PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 ;
@@ -356,7 +335,7 @@ PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
 PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
 LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.SET	LPTMODE_S100	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTMODE		.SET	LPTMODE_T35	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
 LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
 LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 LPT0BASE	.SET	$C7		; LPT 0: REGISTERS BASE ADR
@@ -385,13 +364,20 @@ SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
 ESPSDENABLE	.SET	TRUE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ESPSDTRACE	.SET	1		; ESPSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-ESPSDCNT	.SET	1		; ESPSD: NUMBER OF BOARDS TO DETECT (1-2), 1-2 DEVICES PER BOARD
 ESPSD_USECD	.SET	TRUE		; ESPSD: ENABLE CARD DETECT SIGNAL USAGE
+ESPSDCNT	.SET	1		; ESPSD: NUMBER OF BOARDS TO DETECT (1-2), 1-2 DEVICES PER BOARD
 ESPSD0BASE	.SET	$80		; ESPSD 0: ESP32 INTERFACE IO BASE ADR
 ESPSD0DUAL	.SET	TRUE		; ESPSD 0: DUAL INTERFACE BOARD (DUAL SD)
 ESPSD1BASE	.SET	$82		; ESPSD 1: ESP32 INTERFACE IO BASE ADR
 ESPSD1DUAL	.SET	TRUE		; ESPSD 1: DUAL INTERFACE BOARD (DUAL SD)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+SCSITRACE	.SET	1		; SCSI: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SCSICNT		.SET	2		; SCSI: NUMBER OF TARGET DEVICES (1-2)
+SCSI_TID	.SET	0		; SCSI: TARGET DEVICE ID (0-6)
+SCSI0_LUN	.SET	0		; SCSI 0: TARGET LUN
+SCSI1_LUN	.SET	1		; SCSI 1: TARGET LUN
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
@@ -399,20 +385,11 @@ PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
 SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
 AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
-AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
 ;
 SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.SET	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_TEMPLATE.asm

@@ -0,0 +1,526 @@
+;
+;==================================================================================================
+;   ROMWBW GLOBAL MASTER CONFIGURATION FILE
+;==================================================================================================
+;
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_MASTER.asm			- MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM
+;     |
+;     +-> Config/<plt>_std.asm		- BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD
+;         |
+;         +-> Config/<plt>_<cust>.asm	- USER: CUSTOM USER BUILD SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
+;
+#DEFINE PLATFORM_NAME	"RomWBW", " [", CONFIG, "]"	; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE
+#DEFINE AUTO_CMD	""		; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED
+#DEFINE DEFSERCFG	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL CONFIGURATION
+;
+#INCLUDE "cfg_MASTER.asm"
+;
+PLATFORM	.SET	PLT_NONE	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
+CPUFAM		.SET	CPU_NONE	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	FALSE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+BOOT_PRETTY	.SET	FALSE		; BOOT WITH PRETTY PLATFORM NAME
+BT_REC_TYPE	.SET	BT_REC_NONE	; BOOT RECOVERY METHOD TO USE: BT_REC_[NONE|FORCE|SBCB0|SBC1B|SBCRI|DUORI]
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+STRICTPART	.SET	TRUE		; ENFORCE STRICT PARTITION TABLE VALIDATION
+;
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	1000000		; CPU OSC FREQ IN MHZ
+INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+;
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMFONTS	.SET	TRUE		; LOAD FONTS FROM ROM
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_NONE		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON|EZ512]
+RAMBIAS		.SET	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+MPCL_RAM	.SET	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
+MPCL_ROM	.SET	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
+MPGSEL_0	.SET	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.SET	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.SET	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.SET	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.SET	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+;
+Z180_BASE	.SET	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.SET	FALSE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
+;
+Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
+Z280_MEMHIWAIT	.SET	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
+Z280_IOWAIT	.SET	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z280_INTWAIT	.SET	0		; Z280: INT ACK WAIT STATUS (0-3)
+Z280_TIMER	.SET	FALSE		; Z280: ENABLE INTERNAL Z280 SYSTEM PERIODIC TIMER
+;
+N8_PPI0		.SET	$80		; N8: FIRST PARALLEL PORT REGISTERS BASE ADR
+N8_PPI1		.SET	$84		; N8: SECOND PARALLEL PORT REGISTERS BASE ADR
+N8_RTC		.SET	$88		; N8: RTC LATCH REGISTER ADR
+N8_ACR		.SET	$94		; N8: AUXILLARY CONTROL REGISTER (ACR) ADR
+N8_RMAP		.SET	$96		; N8: ROM PAGE REGISTER ADR
+N8_DEFACR	.SET	$1B		; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
+;
+RPH_PPI0	.SET	$88		; RPH: FIRST PARALLEL PORT REGISTERS BASE ADR
+RPH_RTC		.SET	$84		; RPH: RTC LATCH REGISTER ADR
+RPH_ACR		.SET	$80		; RPH: AUXILLARY CONTROL REGISTER (ACR) ADR
+RPH_DEFACR	.SET	$00		; RPH: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
+;
+MK4_IDE		.SET	$80		; MK4: IDE REGISTERS BASE ADR
+MK4_XAR		.SET	$88		; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR
+MK4_SD		.SET	$89		; MK4: SD CARD CONTROL REGISTER ADR
+MK4_RTC		.SET	$8A		; MK4: RTC LATCH REGISTER ADR
+;
+RTCIO		.SET	$70		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$B0		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.SET	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.SET	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.SET	2		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
+CTCOSC		.SET	614400		; CTC CLOCK FREQUENCY
+;
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+;
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZDIV		.SET	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
+;
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGIO		.SET	$6F		; WATCHDOG REGISTER ADR
+;
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
+;
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	FALSE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	FALSE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+GM7303ENABLE	.SET	FALSE		; ENABLES THE GM7303 BOARD WITH 16X2 LCD
+GM7303BASE	.SET	$30		; BASE ADDRESS FOR GM3703 BOARD  
+;
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDINTS		.SET	FALSE		; ENABLE KBD (PS2) KEYBOARD INTERRUPTS
+;
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
+;
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+PCRTC_BASE	.SET	$C0		; Default port for PCRTC, like DSRTC.
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+DS12RTC_BASE	.SET	$70		; DS12RTC: I/O BASE ADDRESS
+;
+M6242RTCENABLE	.SET	TRUE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+M6242RTC_BASE	.SET	$A0		; M6242RTC: I/O BASE ADDRESS
+;
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
+;
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
+;
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.SET	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.SET	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.SET	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.SET	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.SET	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+;
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$FF		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+;
+ASCIENABLE	.SET	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.SET	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+ASCISWAP	.SET	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.SET	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
+ASCI0CFG	.SET	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
+ASCI1CFG	.SET	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
+;
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UOSC		.SET	1843200		; Z2U: OSC FREQUENCY IN MHZ
+Z2UOSCEXT	.SET	TRUE		; Z2U: USE EXTERNAL OSCILLATOR
+Z2U0BASE	.SET	$10		; Z2U 0: BASE I/O ADDRESS
+Z2U0CFG		.SET	DEFSERCFG	; Z2U 0: SERIAL LINE CONFIG
+Z2U0HFC		.SET	FALSE		; Z2U 0: ENABLE HARDWARE FLOW CONTROL
+;
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIADEBUG	.SET	FALSE		; ACIA: ENABLE DEBUG OUTPUT
+ACIACNT		.SET	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
+ACIA0BASE	.SET	$80		; ACIA 0: REGISTERS BASE ADR
+ACIA0CLK	.SET	CPUOSC		; ACIA 0: OSC FREQ IN HZ
+ACIA0DIV	.SET	1		; ACIA 0: SERIAL CLOCK DIVIDER
+ACIA0CFG	.SET	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIA1BASE	.SET	$40		; ACIA 1: REGISTERS BASE ADR
+ACIA1CLK	.SET	CPUOSC		; ACIA 1: OSC FREQ IN HZ
+ACIA1DIV	.SET	1		; ACIA 1: SERIAL CLOCK DIVIDER
+ACIA1CFG	.SET	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
+;
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.SET	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.SET	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.SET	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.SET	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.SET	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.SET	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+VDUSIZ		.SET	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+CVDUMODE	.SET	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
+CVDUMON		.SET	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+GDCMODE		.SET	GDCMODE_RPH	; GDC: GDC MODE: GDCMODE_[NONE|ECB|RPH]
+GDCMON		.SET	GDCMON_EGA      ; GDC: GDC MONITOR SETUP: GDCMON_[NONE|CGA|EGA]
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VGASIZ		.SET	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
+;
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_NONE	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFCNT		.SET	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
+;
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_NONE	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE0BASE	.SET	$20		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+;
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0MODE	.SET	PPIDEMODE_NONE	; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
+PPIDE0BASE	.SET	$60		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1MODE	.SET	PPIDEMODE_NONE	; PPIDE 1: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
+PPIDE1BASE	.SET	$20		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 1B (SLAVE): 8 BIT XFER
+PPIDE2MODE	.SET	PPIDEMODE_NONE	; PPIDE 2: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
+PPIDE2BASE	.SET	$14		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 2B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_NONE	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+;
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.SET	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.SET	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.SET	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.SET	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.SET	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.SET	FALSE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.SET	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.SET	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.SET	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.SET	FALSE		; CH 1: ENABLE SD DISK
+;
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	FALSE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	FALSE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+;
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPBASE		.SET	$60		; PPP: PPI REGISTERS BASE ADDRESS
+PPPSDENABLE	.SET	FALSE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
+PPPSDTRACE	.SET	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPPCONENABLE	.SET	FALSE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
+;
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPCONENABLE	.SET	FALSE		; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
+;
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKTRACE	.SET	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+;
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
+;
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.SET	LPTMODE_NONE	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
+LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.SET	$E8		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.SET	$EC		; LPT 1: REGISTERS BASE ADR
+;
+PPAENABLE	.SET	FALSE		; PPA: ENABLE IOMEGA ZIP DRIVE (PPA) DISK DRIVER (PPA.ASM)
+PPACNT		.SET	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.SET	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.SET	PPAMODE_NONE	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.SET	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.SET	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+;
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IOMEGA ZIP PLUS DRIVE (IMM) DISK DRIVER (IMM.ASM)
+IMMCNT		.SET	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.SET	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.SET	IMMMODE_NONE	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.SET	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.SET	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+;
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM)
+SYQCNT		.SET	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.SET	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.SET	IMMMODE_NONE	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.SET	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+;
+ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
+;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+SCSITRACE	.SET	1		; SCSI: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SCSICNT		.SET	2		; SCSI: NUMBER OF TARGET DEVICES (1-2)
+SCSI_TID	.SET	0		; SCSI: TARGET DEVICE ID (0-6)
+SCSI0_LUN	.SET	0		; SCSI0: TARGET LUN
+SCSI1_LUN	.SET	1		; SCSI1: TARGET LUN
+;
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO4BASE	.SET	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIOZBASE	.SET	$88		; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIOSBASE	.SET	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
+;
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFBASE		.SET	$0C		; UF: REGISTERS BASE ADR
+;
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+SN76489CHNOUT	.SET	SNCHAN_BOTH	; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
+;
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC]
+AY_FORCE	.SET	FALSE		; AY: BYPASS AUTO-DETECT, FORCED PRESENT
+;
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SPKPORT		.SET	RTCIO		; SPK: THE PORT WITH THE SPEAKER IO BIT
+SPKSHADOW	.SET	HB_RTCVAL	; SPK: THE SHADOW VALUE FOR THE PORT THAT HAS TO BE MAINTAINED
+SPKMASK		.SET	00000100b	; SPK: THE BIT MASK TO ACTUALLY TOGGLE
+;
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+;
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+;
+; EZ80 SETTINGS
+;
+EZ80TMR_NONE	.SET	0		; DO NOT USE ON-BOARD TIMER TO GENERATE TICKS
+EZ80TMR_INT	.SET	1		; MARSHALL TIMER TICK INTERRUPTS FROM EZ80 TO HBIOS
+EZ80TMR_FIRM	.SET	2		; DELEGATE SYS TIMER HBIOS CALL TO EZ80 FIRMWARE (TIMER TICK INTS DISABLED)
+;
+EZ80UARTENABLE	.SET	FALSE		; EZ80 UART: ENABLE EZ80 UART0 DRIVER (EZ80UART.ASM)
+EZ80RTCENABLE	.SET	FALSE		; EZ80 ON CHIP RTC
+EZ80TIMER	.SET	EZ80TMR_FIRM	; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM]
+EZ80IOBASE	.SET	$FF		; EZ80 I/O BASE ADDRESS FOR EXTERNAL IO
+;
+; BUS TIMING FOR PAGED MEMORY ACCESS (CS3)
+EZ80_MEM_CYCLES	.SET	3		; MEMORY BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES
+EZ80_MEM_MIN_NS	.SET	100		; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
+EZ80_MEM_WS	.SET	5		; MEMORY WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT
+EZ80_MEM_MIN_WS	.SET	0		; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
+;
+; BUS TIMING FOR EXTERNAL I/O ACCESS (CS2)
+EZ80_IO_CYCLES	.SET	4		; IO BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES
+EZ80_IO_WS	.SET	5		; IO WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT
+EZ80_IO_MIN_NS	.SET	320		; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
+EZ80_IO_MIN_WS	.SET	6		; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
+;
+; APPLY CYCLES, W/S OR CALCULATE CYCLES BASED ON DESIRED PERIOD
+EZ80_WSMD_TYP	.SET	EZ80WSMD_CALC	; BUS WAIT STATE CONFIG: EZ80WSMD_[CALC|CYCLES|WAIT]
+;
+; BUS TIMING FOR ON CHIP ROM
+;
+EZ80_FLSH_WS		.SET	1		; WAIT STATES FOR ON CHIP FLASH (0-7)
+EZ80_FLSH_MIN_NS	.SET	60		; MINIMUM WAIT STATES TO APPLY TO ON-CHIP FLASH, IF EZ80_WSMD_TYP = EZ80WSMD_CALC
+EZ80_FWSMD_TYP		.SET	EZ80WSMD_CALC	; WAIT STATE TYPE: EZ80RMMD_[CALC|WAIT] (CYCLES NOT ALLOWED)

Source/HBIOS/cfg_UNA.asm

@@ -15,8 +15,9 @@
 ;
 #INCLUDE "../UBIOS/ubios.inc"
 ;
-;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.EQU	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 BIOS		.EQU	BIOS_UNA	; HARDWARE BIOS: BIOS_[WBW|UNA]
 ;
 FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES

Source/HBIOS/cfg_Z80RETRO.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -166,6 +167,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -175,6 +184,8 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
@@ -228,20 +239,22 @@ SIO1BCLK	.SET	CPUOSC/2	; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372
 SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
 SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -302,6 +315,8 @@ SYQENABLE	.SET	FALSE		; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM)
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP

Source/HBIOS/cfg_ZETA.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -155,6 +156,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -164,6 +173,8 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
@@ -197,20 +208,22 @@ ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
 SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -272,6 +285,8 @@ SYQENABLE	.SET	FALSE		; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM)
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP

Source/HBIOS/cfg_ZETA2.asm

@@ -49,8 +49,9 @@
 ;
 #INCLUDE "cfg_MASTER.asm"
 ;
-PLATFORM	.SET	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80]
+PLATFORM	.SET	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC]
 CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+TURBOZ80	.SET	FALSE		; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ
 NMOSCPU		.SET	FALSE		; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND)
 BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -166,6 +167,14 @@ DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
 ;
 DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
+PCRTCENABLE	.SET	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
+;
+MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
+M6242RTCENABLE	.SET	FALSE		; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
@@ -175,6 +184,8 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+DLPSERENABLE	.SET	FALSE		; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
@@ -208,20 +219,22 @@ ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
 SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 ;
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
 VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
 CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
 GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.SET	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMSMODE		.SET	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC]
 TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
 VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
 SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
 EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+TVGAENABLE	.SET	FALSE		; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM)
 ;
 MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
 MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
@@ -283,6 +296,8 @@ SYQENABLE	.SET	FALSE		; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM)
 ;
 ESPSDENABLE	.SET	FALSE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
 ;
+SCSIENABLE	.SET	FALSE		; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
+;
 PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
 PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
 PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP

Source/HBIOS/ch.asm

@@ -79,6 +79,23 @@ CHSD_CFG0	.EQU	0		; DUMMY ENTRY
 CHSD_CFG1	.EQU	0		; DUMMY ENTRY
 #ENDIF
 ;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_CH	.EQU	$
+;
+	.DW	SIZ_CH		; MODULE SIZE
+	.DW	CH_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+CH_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	;CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	;JP	Z,CH_PREINIT		; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,CH_INIT		; DO INIT
+	RET				; DONE
+;
 ; CH DEVICE CONFIGURATION
 ;
 CH_CFGSIZ	.EQU	9		; SIZE OF CFG TBL ENTRIES
@@ -470,3 +487,14 @@ CH_STR_376	.TEXT	"CH376$"
   #INCLUDE "chsd.asm"
 #ENDIF
 ;
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_CH	.EQU	$
+SIZ_CH	.EQU	END_CH - ORG_CH
+;	
+	MEMECHO	"CH occupies "
+	MEMECHO	SIZ_CH
+	MEMECHO	" bytes.\n"

Source/HBIOS/ch376-native/readme.md

@@ -102,7 +102,7 @@ Example configuration, combined with the TMS VDP module driver.
 
 ```
 TMSENABLE    .SET   TRUE              ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE      .SET   TMSMODE_MSXUKY    ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|MSXUKY]
+TMSMODE      .SET   TMSMODE_MSXUKY    ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|MSXUKY|N8PC]
 TMS80COLS    .SET   FALSE             ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
 TMSTIMENABLE .SET   TRUE              ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
 ```

Source/HBIOS/ch376.asm

@@ -3,6 +3,23 @@
 ; CH376 NATIVE USB DRIVER
 ;==================================================================================================
 ;
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_CHNATIVE	.EQU	$
+;
+	.DW	SIZ_CHNATIVE		; MODULE SIZE
+	.DW	CHNATIVE_INITPHASE	; ADR OF INIT PHASE HANDLER
+;
+CHNATIVE_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	;CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	;JP	Z,CHNATIVE_PREINIT	; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,CHNATIVE_INIT		; DO INIT
+	RET				; DONE
 
 #DEFINE DEFM	.DB
 #DEFINE DEFB	.DB
@@ -63,3 +80,14 @@ _delay_medium	.EQU	LDELAY
 CHNATIVE_INIT	.EQU	_chnative_init
 CHNATIVE_INITF	.EQU	_chnative_init_force
 
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_CHNATIVE	.EQU	$
+SIZ_CHNATIVE	.EQU	END_CHNATIVE - ORG_CHNATIVE
+;	
+	MEMECHO	"CHNATIVE occupies "
+	MEMECHO	SIZ_CHNATIVE
+	MEMECHO	" bytes.\n"

Source/HBIOS/ch376kyb.asm

@@ -5,6 +5,26 @@
 ;
 ; This driver is designed to work within the TMS video driver for a CRT solution.
 
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_CHUKB	.EQU	$
+;
+	.DW	SIZ_CHUKB		; MODULE SIZE
+	.DW	CHUKB_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+; WARNING: KEYBOARD DRIVERS ARE INITIALIZED BY VDA DRIVERS
+; AND SHOULD NOT BE INITIALIZED BY INITPHASE CALLS.
+;
+CHUKB_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	;CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	;JP	Z,CHUKB_PREINIT		; DO PREINIT
+	;CP	HB_PHASE_INIT		; INIT PHASE?
+	;JP	Z,CHUKB_INIT		; DO INIT
+	RET				; DONE
 
 #IF (!CHNATIVEENABLE)
 	.ECHO	"*** TMSMODE: TMSMODE_MSXUKY REQUIRES CHNATIVEENABLE***\n"
@@ -149,3 +169,14 @@ UKY_READ:
 	LD	E, L
 	XOR	A
 	RET
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_CHUKB	.EQU	$
+SIZ_CHUKB	.EQU	END_CHUKB - ORG_CHUKB
+;	
+	MEMECHO	"CHUKB occupies "
+	MEMECHO	SIZ_CHUKB
+	MEMECHO	" bytes.\n"

Source/HBIOS/ch376scsi.asm

@@ -3,6 +3,23 @@
 ; CH376 NATIVE MASS STORAGE DRIVER
 ;==================================================================================================
 ;
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_CHSCSI	.EQU	$
+;
+	.DW	SIZ_CHSCSI		; MODULE SIZE
+	.DW	CHSCSI_INITPHASE	; ADR OF INIT PHASE HANDLER
+;
+CHSCSI_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	;CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	;JP	Z,CHSCSI_PREINIT	; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,CHSCSI_INIT		; DO INIT
+	RET				; DONE
 
 #include "./ch376-native/scsi-drv.s"
 
@@ -316,3 +333,14 @@ CH_SCSI_GEOM:
 	LD	D,16 | $80		; HEADS / CYL = 16, SET LBA CAPABILITY BIT
 	LD	E,16			; SECTORS / TRACK = 16
 	RET				; DONE, A STILL HAS CHUSB_CAP STATUS
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_CHSCSI	.EQU	$
+SIZ_CHSCSI	.EQU	END_CHSCSI - ORG_CHSCSI
+;	
+	MEMECHO	"CHSCSI occupies "
+	MEMECHO	SIZ_CHSCSI
+	MEMECHO	" bytes.\n"

Source/HBIOS/ch376ufi.asm

@@ -4,6 +4,25 @@
 ;==================================================================================================
 ;
 
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_CHUFI	.EQU	$
+;
+	.DW	SIZ_CHUFI		; MODULE SIZE
+	.DW	CHUFI_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+CHUFI_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	;CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	;JP	Z,CHUFI_PREINIT		; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,CHUFI_INIT		; DO INIT
+	RET				; DONE
+
+
 #include "./ch376-native/ufi-drv.s"
 _ufi_seek	.EQU	_usb_scsi_seek
 
@@ -321,3 +340,14 @@ CH_UFI_GEOM:
 	LD	A, $FF
 	OR	A
 	RET
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_CHUFI	.EQU	$
+SIZ_CHUFI	.EQU	END_CHUFI - ORG_CHUFI
+;	
+	MEMECHO	"CHUFI occupies "
+	MEMECHO	SIZ_CHUFI
+	MEMECHO	" bytes.\n"

Source/HBIOS/ctc.asm

@@ -150,6 +150,23 @@ CTCTIVT		.EQU	INT_CTC0A + CTCTIMCH
 ;
 	DEVECHO "\n"
 ;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_CTC	.EQU	$
+;
+	.DW	SIZ_CTC			; MODULE SIZE
+	.DW	CTC_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+CTC_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	JP	Z,CTC_PREINIT		; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,CTC_INIT		; DO INIT
+	RET				; DONE
+;
 ;==================================================================================================
 ; CTC PRE-INITIALIZATION
 ;
@@ -303,3 +320,14 @@ CTC_NO:
 ; CTC DRIVER DATA STORAGE
 ;
 CTC_EXIST	.DB	$FF		; SET TO ZERO IF EXISTS
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_CTC	.EQU	$
+SIZ_CTC	.EQU	END_CTC - ORG_CTC
+;	
+	MEMECHO	"CTC occupies "
+	MEMECHO	SIZ_CTC
+	MEMECHO	" bytes.\n"

Source/HBIOS/cvdu.asm

@@ -62,6 +62,23 @@ CVDU_FONTID	.EQU	FONTID_8X16
 TERMENABLE	.SET	TRUE		; INCLUDE TERMINAL PSEUDODEVICE DRIVER
 KBDENABLE	.SET	TRUE		; INCLUDE KBD KEYBOARD SUPPORT
 ;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_CVDU	.EQU	$
+;
+	.DW	SIZ_CVDU		; MODULE SIZE
+	.DW	CVDU_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+CVDU_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	JP	Z,CVDU_PREINIT		; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,CVDU_INIT		; DO INIT
+	RET				; DONE
+;
 ;======================================================================
 ; CVDU DRIVER - INITIALIZATION
 ;======================================================================
@@ -987,3 +1004,14 @@ CVDU_IDAT:
 	.DB	KBDMODE_PS2	; PS/2 8242 KEYBOARD CONTROLLER
 	.DB	CVDU_KBDST
 	.DB	CVDU_KBDDATA
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_CVDU	.EQU	$
+SIZ_CVDU	.EQU	END_CVDU - ORG_CVDU
+;	
+	MEMECHO	"CVDU occupies "
+	MEMECHO	SIZ_CVDU
+	MEMECHO	" bytes.\n"

Source/HBIOS/dbgmon.asm

@@ -18,6 +18,25 @@
 ;_____________________________________________________________________________
 ;
 #INCLUDE "std.asm"
+;;;;
+;;;;======================================================================
+;;;; ROM Application Header
+;;;;======================================================================
+;;;;
+;;;	.DW	RAHDR_SIG		; SIGNATURE
+;;;	.DB	'M'			; KEYBOARD INVOCATION KEY
+;;;	.DB	KY_CL			; DSKY INVOCATION KEY
+;;;	.DB	%00000000		; ATTRIBUTES
+;;;	.DB	$00			; SOURCE BANK (FILLED IN BY ROMLDR)
+;;;	.DW	$0000			; SOURCE ADR (FILLED IN BY ROMLDR)
+;;;	.DW	MON_LOC			; TARGET LOAD ADDRESS
+;;;	.DW	MON_LEN			; PAYLOAD LENGTH
+;;;	.DW	MON_LOC			; ENTRY ADDRESS
+;;;	.DW	$0000			; CHECKSUM (FUTURE USE)
+;;;	.TEXT	"Monitor"		; APPLICATION DESCRIPTION
+;;;	.FILL	RAHDR_LEN-$,$00		; FILL WITH NULLS
+;
+;======================================================================
 ;
 BUFLEN	.EQU	40			; INPUT LINE LENGTH
 ;

Source/HBIOS/dlpser.asm

@@ -0,0 +1,305 @@
+;
+;==================================================================================================
+; DLP-USB SERIAL DRIVER
+;==================================================================================================
+;
+; THIS SERIAL DRIVER SUPPORTS THE DLP-USB DEVICE ON THE S100 SERIAL-IO
+; BOARD.  NOTE THAT THE DLP USB DEVICE IS CONNECTED IN PARALLEL TO THE
+; S100 SYSTEM.  IT DOES NOT ACTUALLY USE A TRUE SERIAL DATA STREAM
+; EVEN THOUGH IT APPEARS AS SUCH TO THE USB-CONNECTED COMPUTER.
+;
+; STATUS BITS:				IDLE
+;   7: 0=CHAR PENDING			1
+;   6: 0=XMIT HOLDING REGISTER EMPTY	0
+;   5-0: UNDEFINED
+;
+DLPSER_NONE	.EQU	0
+DLPSER_DLP	.EQU	1
+;
+DLPSERCFG	.EQU	SER_9600_8N1	; DLPSER: SERIAL LINE CONFIG
+;
+; ACCORDING TO THE S100 SERIAL-IO BOARD CONVENTIONS, THE PPI IS
+; CONFIGURED FOR MODE 0 WITH A=INPUT, B=OUTPUT, C0-3=OUTPUT,
+; C4-7=INPUT
+;
+DLPSER_PPICTL	.EQU	$AB
+DLPSER_PPICFG	.EQU	%10011000
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_DLPSER	.EQU	$
+;
+	.DW	SIZ_DLPSER		; MODULE SIZE
+	.DW	DLPSER_INITPHASE	; ADR OF INIT PHASE HANDLER
+;
+DLPSER_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	JP	Z,DLPSER_PREINIT	; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,DLPSER_INIT		; DO INIT
+	RET				; DONE
+
+
+;
+DLPSER_PREINIT:
+;
+; SETUP THE DISPATCH TABLE ENTRIES
+;
+	LD	B,DLPSERCNT		; LOOP CONTROL
+	XOR	A			; ZERO TO ACCUM
+	LD	(DLPSER_DEV),A		; CURRENT DEVICE NUMBER
+	LD	IY,DLPSER_CFG		; POINT TO START OF CFG TABLE
+DLPSER_PREINIT0:
+	PUSH	BC			; SAVE LOOP CONTROL
+	CALL	DLPSER_INITUNIT		; HAND OFF TO GENERIC INIT CODE
+	POP	BC			; RESTORE LOOP CONTROL
+;
+	OR	$FF			; $FF TO ACCUME
+	LD	(IY+2),A		; CLEAR HBIOS UNIT ASSIGNMENT
+	LD	A,(IY+1)		; GET THE DLPSER TYPE DETECTED
+	OR	A			; SET FLAGS
+	JR	Z,DLPSER_PREINIT2	; SKIP IT IF NOTHING FOUND
+;	
+	PUSH	BC			; SAVE LOOP CONTROL
+	PUSH	IY			; CFG ENTRY ADDRESS
+	POP	DE			; ... TO DE
+	LD	BC,DLPSER_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	CALL	NZ,CIO_ADDENT		; ADD ENTRY IF DLPSER FOUND
+	LD	(IY+2),A		; RECORD OUT HBIOS UNIT NUMBER
+	POP	BC			; RESTORE LOOP CONTROL
+;
+DLPSER_PREINIT2:
+	LD	DE,DLPSER_CFGSIZ	; SIZE OF CFG ENTRY
+	ADD	IY,DE			; BUMP IY TO NEXT ENTRY
+	DJNZ	DLPSER_PREINIT0		; LOOP UNTIL DONE
+;	
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+; DLPSER UNIT INITIALIZATION ROUTINE
+;
+DLPSER_INITUNIT:
+	CALL	DLPSER_DETECT		; DETECT IT
+	LD	(IY+1),A		; SAVE IN CONFIG TABLE
+	OR	A			; SET FLAGS
+	RET	Z			; ABORT IF NOTHING THERE
+;
+	; UPDATE WORKING DLPSER DEVICE NUM
+	LD	HL,DLPSER_DEV		; POINT TO CURRENT UART DEVICE NUM
+	LD	A,(HL)			; PUT IN ACCUM
+	INC	(HL)			; INCREMENT IT (FOR NEXT LOOP)
+	LD	(IY),A			; UPDATE UNIT NUM
+;	
+	JP	DLPSER_INITDEV		; INIT DEVICE AND RETURN
+;
+;
+;
+DLPSER_INIT:
+	LD	B,DLPSERCNT		; COUNT OF POSSIBLE DLPSER UNITS
+	LD	IY,DLPSER_CFG		; POINT TO START OF CFG TABLE
+DLPSER_INIT1:
+	PUSH	BC			; SAVE LOOP CONTROL
+	LD	A,(IY+1)		; GET DLPSER TYPE
+	OR	A			; SET FLAGS
+	CALL	NZ,DLPSER_PRTCFG	; PRINT IF NOT ZERO
+	POP	BC			; RESTORE LOOP CONTROL
+	LD	DE,DLPSER_CFGSIZ	; SIZE OF CFG ENTRY
+	ADD	IY,DE			; BUMP IY TO NEXT ENTRY
+	DJNZ	DLPSER_INIT1		; LOOP TILL DONE
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+; DRIVER FUNCTION TABLE
+;
+DLPSER_FNTBL:
+	.DW	DLPSER_IN
+	.DW	DLPSER_OUT
+	.DW	DLPSER_IST
+	.DW	DLPSER_OST
+	.DW	DLPSER_INITDEV
+	.DW	DLPSER_QUERY
+	.DW	DLPSER_DEVICE
+#IF (($ - DLPSER_FNTBL) != (CIO_FNCNT * 2))
+	.ECHO	"*** INVALID DLPSER FUNCTION TABLE ***\n"
+#ENDIF
+;
+;
+;
+DLPSER_IN:
+	CALL	DLPSER_IST		; CHECK FOR CHAR PENDING
+	JR	Z,DLPSER_IN		; WAIT FOR IT IF NECESSARY
+	;IN	A,(DLPSER_DATA)		; READ THE CHAR
+	LD	C,(IY+4)		; DATA PORT
+	IN	E,(C)			; GET BYTE
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+;
+;
+DLPSER_IST:
+	;IN	A,(DLPSER_STAT)		; READ LINE STATUS REGISTER
+	LD	C,(IY+3)		; STATUS PORT
+	IN	A,(C)			; GET STATUS
+	CPL
+	AND	%10000000		; ISOLATE DATA READY
+	JP	Z,CIO_IDLE		; RETURN VIA IDLE PROCESSING
+	OR	$FF			; SET A=$FF TO SIGNAL READY
+	RET				; RETURN
+;
+;
+;
+DLPSER_OUT:
+	CALL	DLPSER_OST		; CHECK FOR OUTPUT READY
+	JR	Z,DLPSER_OUT		; WAIT IF NECESSARY
+	;LD	A,E			; RECOVER THE CHAR TO WRITE
+	;OUT	(DLPSER_DATA),A		; WRITE THE CHAR
+	LD	C,(IY+4)		; DATA PORT
+	OUT	(C),E			; SEND BYTE
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+;
+;
+DLPSER_OST:
+	;IN	A,(DLPSER_STAT)		; READ LINE STATUS REGISTER
+	LD	C,(IY+3)		; STATUS PORT
+	IN	A,(C)			; GET STATUS
+	CPL
+	AND	%01000000 		; ISOLATE OUTPUT RDY
+	JP	Z,CIO_IDLE		; RETURN VIA IDLE PROCESSING
+	OR	$FF			; SET A=$FF TO SIGNAL READY
+	RET				; RETURN
+;
+;
+;
+DLPSER_INITDEV:
+#IF (PLATFORM == PLT_SZ80)
+	LD	A,(IY+4)		; GET THE DATA PORT
+	CP	$AA			; IS THIS THE SERIAL I/O BOARD DLP DEVICE?
+	JR	NZ,DLPSER_INITDEV1	; IF NOT, SKIP
+	LD	A,DLPSER_PPICFG		; CONFIG 8255 PORTS
+	OUT	(DLPSER_PPICTL),A	; WRITE CONTROL WORD
+#ENDIF
+DLPSER_INITDEV1:
+	XOR	A			; NOTHING TO DO
+	RET
+;
+;
+;
+DLPSER_QUERY:
+	LD	DE,DLPSERCFG
+	XOR	A
+	RET
+;
+;
+;
+DLPSER_DEVICE:
+	LD	D,CIODEV_DLPSER		; D := DEVICE TYPE
+	LD	E,(IY)			; E := DEVICE NUM, ALWAYS 0
+	LD	C,$00			; C := DEVICE TYPE, 0x00 IS RS-232
+	LD	H,0			; H := 0, DRIVER HAS NO MODES
+	LD	L,(IY+4)		; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; TEST FOR HARDWARE PRESENCE.
+; THIS DEVICE IS VERY HARD TO DETECT.  WE USE THE PRESENCE OF
+; THE STATUS PORT.  RETURN DEVICE TYPE.
+;
+DLPSER_DETECT:
+	LD	A,(IY+3)		; STATUS PORT
+	LD	C,A			; COPY TO C
+	LD	($+4),A			; MODIFY CODE
+DLPSER_DETECT1
+	IN	A,($FF)			; READ PORT DIRECT
+	IN	B,(C)			; READ PORT VIA C
+	CP	B			; A==B MEANS PORT EXISTS
+	LD	A,DLPSER_NONE		; ASSUME NOTHING THERE
+	RET	NZ			; IF NZ, NOTHING
+	LD	A,DLPSER_DLP		; ELSE TYPE IS DLP
+	RET
+;
+;
+;
+DLPSER_PRTCFG:
+	; ANNOUNCE PORT
+	CALL	NEWLINE			; FORMATTING
+	PRTS("DLPSER$")			; FORMATTING
+	LD	A,(IY)			; DEVICE NUM
+	CALL	PRTDECB			; PRINT DEVICE NUM
+	PRTS(": IO=0x$")		; FORMATTING
+	LD	A,(IY+4)		; GET DATA PORT
+	CALL	PRTHEXBYTE		; PRINT DATA PORT
+;
+	; PRINT THE DLPSER TYPE
+	CALL	PC_SPACE		; FORMATTING
+	LD	A,(IY+1)		; GET DLPSER TYPE BYTE
+	RLCA				; MAKE IT A WORD OFFSET
+	LD	HL,DLPSER_TYPE_MAP	; POINT HL TO TYPE MAP TABLE
+	CALL	ADDHLA			; HL := ENTRY
+	LD	E,(HL)			; DEREFERENCE
+	INC	HL			; ...
+	LD	D,(HL)			; ... TO GET STRING POINTER
+	CALL	WRITESTR		; PRINT IT
+;
+	XOR	A
+	RET
+;
+;
+;
+DLPSER_TYPE_MAP:
+	.DW	DLPSER_STR_NONE
+	.DW	DLPSER_STR_DLP
+
+DLPSER_STR_NONE	.DB	"<NOT PRESENT>$"
+DLPSER_STR_DLP	.DB	"DLP-USB$"
+;
+; UART PORT TABLE
+;
+DLPSER_CFG:
+;
+DLPSER0_CFG:
+	.DB	0				; DEVICE NUMBER (SET DURING INIT)	; +0
+	.DB	0				; DLPSER TYPE (SET DURING INIT)		; +1
+	.DB	$FF				; HBIOS CHARACTER UNIT ASSIGNED		; +2
+	.DB	DLPSER0STAT			; STATUS PORT				; +3
+	.DB	DLPSER0DATA			; DATA PORT				; +4
+;
+	DEVECHO	"DLPSER: IO="
+	DEVECHO	DLPSER0DATA
+	DEVECHO	"\n"
+;
+;
+DLPSER_CFGSIZ	.EQU	$ - DLPSER_CFG		; SIZE OF ONE CFG TABLE ENTRY
+;
+#IF (DLPSERCNT >= 1)
+DLPSER1_CFG:
+	.DB	0				; DEVICE NUMBER (SET DURING INIT)	; +0
+	.DB	0				; DLPSER TYPE (SET DURING INIT)		; +1
+	.DB	$FF				; HBIOS CHARACTER UNIT ASSIGNED		; +2
+	.DB	DLPSER1STAT			; STATUS PORT				; +3
+	.DB	DLPSER1DATA			; DATA PORT				; +4
+;
+	DEVECHO	"DLPSER: IO="
+	DEVECHO	DLPSER1DATA
+	DEVECHO	"\n"
+#ENDIF
+;
+; WORKING VARIABLES
+;
+DLPSER_DEV		.DB	0		; DEVICE NUM USED DURING INIT
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_DLPSER	.EQU	$
+SIZ_DLPSER	.EQU	END_DLPSER - ORG_DLPSER
+;	
+	MEMECHO	"DLPSER occupies "
+	MEMECHO	SIZ_DLPSER
+	MEMECHO	" bytes.\n"

Source/HBIOS/dma.asm

@@ -23,7 +23,7 @@ DMA_CTL		.EQU	DMABASE + 3
 DMA_USEHALF	.EQU	FALSE
 	DEVECHO	"DUO"
 #ENDIF
-;S
+;
 	DEVECHO	", IO="
 	DEVECHO	DMA_IO
 	DEVECHO	"\n"
@@ -70,6 +70,23 @@ DMA_FORCE			.EQU	0
   #DEFINE DMAIOFULL \;
 #ENDIF
 ;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_DMA	.EQU	$
+;
+	.DW	SIZ_DMA			; MODULE SIZE
+	.DW	DMA_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+DMA_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	;CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	;JP	Z,DMA_PREINIT		; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,DMA_INIT		; DO INIT
+	RET				; DONE
+;
 ;==================================================================================================
 ; DMA INITIALIZATION CODE
 ;==================================================================================================
@@ -360,3 +377,14 @@ DMARegDump:
 	call	NEWLINE
 	ret
 #ENDIF
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_DMA	.EQU	$
+SIZ_DMA	.EQU	END_DMA - ORG_DMA
+;	
+	MEMECHO	"DMA occupies "
+	MEMECHO	SIZ_DMA
+	MEMECHO	" bytes.\n"

Source/HBIOS/ds12rtc.asm

@@ -0,0 +1,438 @@
+;
+;==================================================================================================
+; DALLAS SEMICONDUCTOR DS1288X REAL TIME CLOCK
+;==================================================================================================
+;
+; THIS DRIVER IS FOR THE DS1288X REAL-TIME CLOCK AND NVRAM.
+; THE INTERFACE IS ASSUMED TO BE LIKE AN IBM PC AT PORT 0X70.
+;
+; TODO:
+;   CHECK CONTROL REG A, BIT 7 (VALID RAM/TIME) AND NOTIFY
+;   USER IF BATTERY IS DISCHARGED.
+;
+;  REGISTER ADDRESSES (HEX / BCD):
+;
+;  +---------+----------------------------------------------+--------+
+;  | REG     | FUNCTION                                     | RANGE  |
+;  +---------+----------------------------------------------+--------+
+;  | $00     | SECONDS                                      | 0-59   |
+;  | $01     | SECONDS ALARM                                | 0-59   |
+;  | $02     | MINUTES                                      | 0-59   |
+;  | $03     | MINUTES ALARM                                | 0-59   |
+;  | $04     | HOURS                                        | 00-23  |
+;  | $05     | HOURS ALARM                                  | 00-23  |
+;  | $06     | DAY                                          | 01-07  |
+;  | $07     | DATE                                         | 01-31  |
+;  | $08     | MONTH                                        | 01-12  |
+;  | $09     | YEAR                                         | 00-99  |
+;  | $0A     | CONTROL (SEE BELOW)                          | --     |
+;  | $0B     | CONTROL (SEE BELOW)                          | --     |
+;  | $0C     | CONTROL (SEE BELOW)                          | --     |
+;  | $0D     | CONTROL (SEE BELOW)                          | --     |
+;  | $0E-$31 | RAM                                          | --     |
+;  | $32     | CENTURY                                      | 00-99  |
+;  | $33-$7F | RAM                                          | --     |
+;  +---------+----------------------------------------------+--------+
+;
+;  +-----+-------+-------+-------+-------+-------+-------+-------+-------+
+;  | REG | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
+;  +-----+-------+-------+-------+-------+-------+-------+-------+-------+
+;  | $0A | UIP   | DV2   | DV1   | DV0   | RS3   | RS2   | RS1   | RS0   |
+;  | $0B | SET   | PIE   | AIE   | UIE   | SQWE  | DM    | 24/12 | DSE   |
+;  | $0C | IRQF  | PF    | AF    | UF    | 0     | 0     | 0     | 0     |
+;  | $0D | VRT   | 0     | 0     | 0     | 0     | 0     | 0     | 0     |
+;  +-----+-------+-------+-------+-------+-------+-------+-------+-------+
+;
+; NOTE: THE IBM PC CMOS USES REGISTER ADDRESSES UP TO $5F.  THIS RTC
+; IS SOMETIMES USED IN SYSTEMS THAT HAVE A X86 BOARD, SO WE AVOID ANY
+; CONFLICT BY OFFSETTING OUR REGISTER INDEXES BY $60.  THIS MEANS WE
+; MAP REQUESTS FOR $00-$1F TO NVRAM REGISTERS $60-$7F.
+;
+DS12RTC_SEL	.EQU	DS12RTC_BASE + 0
+DS12RTC_DATA	.EQU	DS12RTC_BASE + 1
+;
+DS12RTC_NVBASE	.EQU	$10
+DS12RTC_NVSIZE	.EQU	$30
+;
+	DEVECHO	"DS12RTC:"
+;
+	DEVECHO	" IO="
+	DEVECHO	DS12RTC_BASE
+	DEVECHO	"\n"
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_DS12RTC	.EQU	$
+;
+	.DW	SIZ_DS12RTC		; MODULE SIZE
+	.DW	DS12RTC_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+DS12RTC_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	;CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	;JP	Z,DS12RTC_PREINIT		; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,DS12RTC_INIT		; DO INIT
+	RET				; DONE
+;
+; RTC DEVICE PRE-INITIALIZATION ENTRY
+;
+DS12RTC_PREINIT:
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+; RTC DEVICE INITIALIZATION ENTRY
+;
+DS12RTC_INIT:
+	CALL	NEWLINE			; FORMATTING
+	PRTS("DS12RTC:$")
+;
+	; PRINT RTC PORT ADDRESS
+	PRTS(" IO=0x$")			; LABEL FOR IO ADDRESS
+	LD	A,DS12RTC_BASE		; GET IO ADDRESS
+	CALL	PRTHEXBYTE		; PRINT IT
+;
+	CALL	DS12RTC_DETECT		; HARDWARE DETECTION
+	JR	Z,DS12RTC_INIT1		; CONTINUE IF FOUND
+;
+	; HANDLE HARDWARE MISSING
+	PRTS(" NOT PRESENT$")		; NOT ZERO, H/W NOT PRESENT
+	OR	$FF			; SIGNAL FAILURE
+	RET				; BAIL OUT
+;
+DS12RTC_INIT1:
+	; INITIALIZE RTC
+	CALL	DS12RTC_INITDEV
+;
+	; DISPLAY CURRENT TIME
+	CALL	PC_SPACE
+	LD	HL,DS12RTC_TIMBUF
+	CALL	DS12RTC_RDCLK
+	LD	HL,DS12RTC_TIMBUF
+	CALL	PRTDT
+;
+	; REGISTER THE RTC
+	LD	BC,DS12RTC_DISPATCH
+	CALL	RTC_SETDISP
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; RTC DEVICE FUNCTION DISPATCH ENTRY
+;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
+;   B: FUNCTION (IN)
+;
+DS12RTC_DISPATCH:
+	LD	A,B		; GET REQUESTED FUNCTION
+	AND	$0F		; ISOLATE SUB-FUNCTION
+	JP	Z,DS12RTC_GETTIM	; GET TIME
+	DEC	A
+	JP	Z,DS12RTC_SETTIM	; SET TIME
+	DEC	A
+	JP	Z,DS12RTC_GETBYT	; GET NVRAM BYTE VALUE
+	DEC	A
+	JP	Z,DS12RTC_SETBYT	; SET NVRAM BYTE VALUE
+	DEC	A
+	JP	Z,DS12RTC_GETBLK	; GET NVRAM DATA BLOCK VALUES
+	DEC	A
+	JP	Z,DS12RTC_SETBLK	; SET NVRAM DATA BLOCK VALUES
+	DEC	A
+	JP	Z,DS12RTC_GETALM	; GET ALARM
+	DEC	A
+	JP	Z,DS12RTC_SETALM	; SET ALARM
+	DEC	A
+	JP	Z,DS12RTC_DEVICE	; REPORT RTC DEVICE INFO
+;
+	SYSCHKERR(ERR_NOFUNC)
+	RET
+;
+; ALARM FUNCTIONALITY NOT IMPLEMENTED
+;
+DS12RTC_GETBLK:
+DS12RTC_SETBLK:
+DS12RTC_GETALM:
+DS12RTC_SETALM:
+	SYSCHKERR(ERR_NOTIMPL)
+	RET
+;
+; RTC GET TIME
+; BUFFER FORMAT IS BCD: YYMMDDHHMMSS
+; 24 HOUR TIME FORMAT IS ASSUMED
+;
+DS12RTC_GETTIM:
+	PUSH	HL			; SAVE ADR OF OUTPUT BUF
+;
+	LD	HL,DS12RTC_TIMBUF	; POINTER TO CLK DATA
+	CALL	DS12RTC_RDCLK		; READ IT
+;
+	; NOW COPY TO REAL DESTINATION (INTERBANK SAFE)
+	LD	A,BID_BIOS		; COPY FROM BIOS BANK
+	LD	(HB_SRCBNK),A           ; SET IT
+	LD	A,(HB_INVBNK)		; COPY TO CURRENT USER BANK
+	LD	(HB_DSTBNK),A           ; SET IT
+	LD	HL,DS12RTC_TIMBUF		; SOURCE ADR
+	POP	DE			; DEST ADR
+	LD	BC,6			; LENGTH IS 6 BYTES
+#IF (INTMODE == 1)
+	DI
+#ENDIF
+	CALL	HB_BNKCPY		; COPY THE CLOCK DATA
+#IF (INTMODE == 1)
+	EI
+#ENDIF
+;
+	; CLEAN UP AND RETURN
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+;
+; RTC SET TIME
+; BUFFER FORMAT IS BCD: YYMMDDHHMMSS
+; 24 HOUR TIME FORMAT IS ASSUMED
+;
+DS12RTC_SETTIM:
+	; COPY INCOMING TIME DATA TO OUR TIME BUFFER
+	LD	A,(HB_INVBNK)		; COPY FROM CURRENT USER BANK
+	LD	(HB_SRCBNK),A		; SET IT
+	LD	A,BID_BIOS		; COPY TO BIOS BANK
+	LD	(HB_DSTBNK),A		; SET IT
+	LD	DE,DS12RTC_TIMBUF		; DEST ADR
+	LD	BC,6			; LENGTH IS 6 BYTES
+#IF (INTMODE == 1)
+	DI
+#ENDIF
+	CALL	HB_BNKCPY		; COPY THE CLOCK DATA
+#IF (INTMODE == 1)
+	EI
+#ENDIF
+;
+	; WRITE TO CLOCK
+	LD	HL,DS12RTC_TIMBUF	; POINTER TO CLK DATA
+	CALL	DS12RTC_WRCLK		; WRITE TO THE CLOCK
+;
+	; CLEAN UP AND RETURN
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+;
+; RTC GET NVRAM BYTE
+;   C: INDEX
+;   E: VALUE (OUTPUT)
+;
+DS12RTC_GETBYT:
+	LD	A,C			; INDEX TO ACCUM
+	CP	DS12RTC_NVSIZE		; COMPARE TO MAX
+	JR	NC,DS12RTC_BADIDX	; HANDLE RANGE ERROR
+;
+	ADD	A,DS12RTC_NVBASE	; OFFSET TO START OF NVRAM
+	LD	C,A			; INDEX BACK TO C
+	CALL	DS12RTC_RDREG		; GET THE VALUE
+	LD	E,A			; PUT IN E TO RETURN
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+; RTC SET NVRAM BYTE
+;   C: INDEX
+;   E: VALUE
+;
+DS12RTC_SETBYT:
+	LD	A,C			; INDEX TO ACCUM
+	CP	DS12RTC_NVSIZE		; COMPARE TO MAX
+	JR	NC,DS12RTC_BADIDX	; HANDLE RANGE ERROR
+;
+	ADD	A,DS12RTC_NVBASE	; OFFSET TO START OF NVRAM
+	LD	C,A			; INDEX BACK TO C
+	LD	A,E			; PUT VALUE IN A
+	CALL	DS12RTC_WRREG		; WRITE IT
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+; HANDLE RANGE ERROR
+;
+DS12RTC_BADIDX:
+	LD	A,ERR_RANGE
+	OR	A
+	RET
+;
+; REPORT RTC DEVICE INFO
+;
+DS12RTC_DEVICE:
+	LD	D,RTCDEV_DS12		; D := DEVICE TYPE
+	LD	E,0			; E := PHYSICAL DEVICE NUMBER
+	LD	H,0			; H := MODE
+	LD	L,DS12RTC_BASE		; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; DETECT RTC HARDWARE PRESENCE
+; RETURN Z IF PRESENT
+;
+DS12RTC_DETECT:
+	LD	C,$7F			; USE LAST RAM BYTE FOR TESTING
+	CALL	DS12RTC_RDREG		; GET CURRENT VALUE
+	LD	B,A			; SAVE IT
+	LD	A,$A5			; TEST VALUE
+	CALL	DS12RTC_WRREG		; WRITE IT
+	CALL	DS12RTC_RDREG		; READ IT BACK
+	CP	$A5			; COMPARE TO TEST VALUE
+	PUSH	AF			; SAVE RESULTS
+	LD	A,B			; RECOVER ORIGINAL VALUE
+	CALL	DS12RTC_WRREG		; RESTORE IT
+	POP	AF			; RECOVER RESULT
+	RET				; AND RETURN
+;
+; READ CLOCK DATA INTO BUFFER AT HL (YYMMDDHHMMSS)
+;
+DS12RTC_RDCLK:
+	LD	E,0			; CLEAR UIP FLAG
+	PUSH	HL			; SAVE IN CASE OF RESTART
+	LD	C,$09			; START WITH YEAR REG
+	CALL	DS12RTC_RDCLK1		; DO YEAR (REG $09)
+	CALL	DS12RTC_RDCLK1		; DO MONTH (REG $08)
+	CALL	DS12RTC_RDCLK1		; DO DAY OF MONTH (REG $07)
+	DEC	C			; SKIP DAY OF WEEK (REG $06)
+	DEC	C			; SKIP HOURS ALARM (REG $05)
+	CALL	DS12RTC_RDCLK1		; DO HOUR (REG $04)
+	DEC	C			; SKIP MINUTES ALARM (REG $03)
+	CALL	DS12RTC_RDCLK1		; DO MINUTES (REG $02)
+	DEC	C			; SKIP SECONDS ALARM (REG $01)
+	CALL	DS12RTC_RDCLK1		; DO SECONDS (REG $00)
+	POP	HL			; RESTORE BUF PTR
+	LD	A,E			; UIP FLAG TO ACCUM
+	OR	A			; TEST IT
+	JR	NZ,DS12RTC_RDCLK	; IF UIP WAS FLAGGED, TRY AGAIN
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;	
+DS12RTC_RDCLK1:
+	CALL	DS12RTC_UIP		; CHECK FOR UPDATE IN PROGRESS
+	JR	Z,DS12RTC_RDCLK2	; IF NO UIP, SKIP AHEAD
+	INC	E			; FLAG UIP OCCURRED
+DS12RTC_RDCLK2:
+	CALL	DS12RTC_RDREG		; GET IT
+	LD	(HL),A			; STORE IN BUF
+	INC	HL			; BUMP BUF PTR
+	DEC	C			; DEC REGISTER
+	RET
+;
+; WRITE CLOCK DATA FROM BUFFER AT HL
+;
+DS12RTC_WRCLK:
+	LD	E,0			; CLEAR UIP FLAG
+	PUSH	HL			; SAVE IN CASE OF RESTART
+	LD	C,$09			; START WITH YEAR REG
+	CALL	DS12RTC_WRCLK1		; DO YEAR (REG $09)
+	CALL	DS12RTC_WRCLK1		; DO MONTH (REG $08)
+	CALL	DS12RTC_WRCLK1		; DO DAY OF MONTH (REG $07)
+	DEC	C			; SKIP DAY OF WEEK (REG $06)
+	DEC	C			; SKIP HOURS ALARM (REG $05)
+	CALL	DS12RTC_WRCLK1		; DO HOUR (REG $04)
+	DEC	C			; SKIP MINUTES ALARM (REG $03)
+	CALL	DS12RTC_WRCLK1		; DO MINUTES (REG $02)
+	DEC	C			; SKIP SECONDS ALARM (REG $01)
+	CALL	DS12RTC_WRCLK1		; DO SECONDS (REG $00)
+	POP	HL			; RESTORE BUF PTR
+	LD	A,E			; UIP FLAG TO ACCUM
+	OR	A			; TEST IT
+	JR	NZ,DS12RTC_WRCLK	; IF UIP WAS FLAGGED, TRY AGAIN
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;	
+DS12RTC_WRCLK1:
+	CALL	DS12RTC_UIP		; CHECK FOR UPDATE IN PROGRESS
+	JR	Z,DS12RTC_WRCLK2	; IF NO UIP, SKIP AHEAD
+	INC	E			; FLAG UIP OCCURRED
+DS12RTC_WRCLK2:
+	LD	A,(HL)			; GET VALUE
+	CALL	DS12RTC_WRREG		; WRITE IT
+	INC	HL			; BUMP BUF PTR
+	DEC	C			; DEC REGISTER
+	JR	DS12RTC_UIP		; RETURN VIA CHECK FOR UPDATE IN PROGRESS
+;
+; INITIALIZE RTC
+;
+DS12RTC_INITDEV:
+;
+	; GET CLOCK STATUS
+	LD	C,$0A			; CONTROL REGISTER A
+	CALL	DS12RTC_RDREG		; READ IT
+	PUSH	AF			; SAVE IT
+;
+	; SET THE CONTROL REGISTERS
+	LD	C,$0A			; CONTROL REGISTER A
+	LD	A,%00100110		; START CLOCK, 1.024KHZ SQUARE WAVE OUTPOUT
+	CALL	DS12RTC_WRREG		; SEND IT
+	INC	C			; CONTROL REGISTER B
+	LD	A,%00000010		; NO INTS, NO ALM, NO SQW, BCD, 24HR, NO DS
+	CALL	DS12RTC_WRREG		; SEND IT
+;
+	POP	AF			; RECOVER ORIGINAL STATUS
+	AND	%01110000		; ISOLATE DV BITS
+	CP	%00100000		; NORMAL RUNNING VALUE?
+	RET	Z			; IF SO, DONE
+;
+	; PROGRAM DEFAULT DATE/TIME
+	LD	HL,DS12RTC_TIMDEF	; POINT TO DEFAULT DATE/TIME BUF
+	CALL	DS12RTC_WRCLK		; WRITE TO THE CLOCK
+	RET				; DONE
+;
+; READ REGSITER
+;   C=REGISTER
+;   A=VALUE
+;
+DS12RTC_RDREG:
+	HB_DI				; NO INTS BETWEEN REG SEL AND DATA
+	LD	A,C			; REGSITER TO A
+	OUT	(DS12RTC_SEL),A		; SELECT IT
+	IN	A,(DS12RTC_DATA)	; GET REG VALUE
+	HB_EI				; RESTORE INTS
+	RET				; DONE
+;
+; WRITE REGSITER
+;   C=REGSITER
+;   A=VALUE
+;
+DS12RTC_WRREG:
+	HB_DI				; NO INTS BETWEEN REG SEL AND DATA
+	PUSH	AF			; SAVE VALUE TO WRITE
+	LD	A,C			; REGSITER TO A
+	OUT	(DS12RTC_SEL),A		; SELECT IT
+	POP	AF			; RECOVER VALUE TO WRITE
+	OUT	(DS12RTC_DATA),A	; GET REG VALUE
+	HB_EI				; RESTORE INTS
+	RET				; DONE
+;
+; CHECK FOR UPDATE IN PROGRESS
+; RETURN NZ IF SO, RETURN Z IF CLEAR TO PROCEED
+; ASSUMES THAT RTC EXISTS AND IS FUNCTIONING
+;
+; UIP BIT WILL BE SET 244US BEFORE AN UPDATE BEGINS.
+; THE UIP BIT MAY NEED TO BE CHECKED REPEATEDLY DURING
+; MULTIPLE BYTE READS/WRITES IF THE PROCESSING MAY
+; TAKE MORE THAN 240US.
+;
+DS12RTC_UIP:
+	PUSH	BC
+	LD	C,$0A
+	CALL	DS12RTC_RDREG		; GET CONTROL REG $0A
+	AND	$80			; ISOLATE UIP BIT
+	POP	BC
+	RET
+;
+; DS12RTC_TIMBUF IS DRIVER'S INTERNAL CLOCK DATA BUFFER
+;
+DS12RTC_TIMBUF	.FILL	6,0		; 6 BYTES FOR GETTIM, YYMMDDHHMMSS
+DS12RTC_TIMDEF	.DB	$00,$01,$01,$00,$00,$00	; DEFAULT DATE/TIME
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_DS12RTC	.EQU	$
+SIZ_DS12RTC	.EQU	END_DS12RTC - ORG_DS12RTC
+;	
+	MEMECHO	"DS12RTC occupies "
+	MEMECHO	SIZ_DS12RTC
+	MEMECHO	" bytes.\n"

Source/HBIOS/ds1501rtc.asm

@@ -117,16 +117,35 @@ DS1501RTC_BUFSIZE	.EQU	6		; 6 BYTE BUFFER (YYMMDDHHMMSS)
 	DEVECHO	DS1501NVM_BASE
 	DEVECHO	"\n"
 ;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_DS1501RTC	.EQU	$
+;
+	.DW	SIZ_DS1501RTC		; MODULE SIZE
+	.DW	DS1501RTC_INITPHASE	; ADR OF INIT PHASE HANDLER
+;
+DS1501RTC_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	;CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	;JP	Z,DS1501RTC_PREINIT	; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,DS1501RTC_INIT	; DO INIT
+	RET				; DONE
+;
 ; RTC Device Initialization Entry
 ;
 DS1501RTC_INIT:
 	CALL	NEWLINE				; Formatting
-	PRTS("DS1501RTC: IO=0x$")
+	PRTS("DS1501RTC: $")
+	PRTS("IO=0x$")
 	LD	A, DS1501RTC_BASE
 	CALL	PRTHEXBYTE
 ;
 	CALL	NEWLINE				; Formatting
-	PRTS("DS1501NVM: IO=0x$")
+	PRTS("DS1501NVM: $")
+	PRTS("IO=0x$")
 	LD	A, DS1501NVM_BASE
 	CALL	PRTHEXBYTE
 ;
@@ -491,3 +510,14 @@ DS1501RTC_BUF_DAY:	.DB	0		; Day
 DS1501RTC_BUF_HOUR:	.DB	0		; Hour
 DS1501RTC_BUF_MIN:	.DB	0		; Minute
 DS1501RTC_BUF_SEC:	.DB	0		; Second
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_DS1501RTC	.EQU	$
+SIZ_DS1501RTC	.EQU	END_DS1501RTC - ORG_DS1501RTC
+;	
+	MEMECHO	"DS1501RTC occupies "
+	MEMECHO	SIZ_DS1501RTC
+	MEMECHO	" bytes.\n"

Source/HBIOS/ds5rtc.asm

@@ -116,6 +116,23 @@ DS5RTC_BUFSIZE	.EQU	6		; 6 BYTE BUFFER (YYMMDDHHMMSS)
 	DEVECHO	DS5RTC_BASE
 	DEVECHO	"\n"
 ;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_DS5RTC	.EQU	$
+;
+	.DW	SIZ_DS5RTC		; MODULE SIZE
+	.DW	DS5RTC_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+DS5RTC_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	;CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	;JP	Z,DS5RTC_PREINIT		; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,DS5RTC_INIT		; DO INIT
+	RET				; DONE
+;
 ; RTC DEVICE INITIALIZATION ENTRY
 ;
 DS5RTC_INIT:
@@ -264,10 +281,10 @@ DS5RTC_SETBYT:
 	LD	A,C			; INDEX TO A
 	ADD	A,$20			; NVRAM STARTS AT REG $20
 	LD	C,A			; BACK TO REG C
+	LD	A,E			; VALUE TO A
 	CALL	DS5RTC_WPOFF		; DISABLE WRITE PROTECT
 	CALL	DS5RTC_PUT		; DO IT
 	CALL	DS5RTC_WPOFF		; ENABLE WRITE PROTECT
-	LD	E,A			; MOVE RESULT TO E
 	XOR	A			; SIGNAL SUCCESS
 	RET				; DONE
 ;
@@ -564,3 +581,14 @@ DS5RTC_TIMBUF	.FILL	6,0		; 6 BYTES FOR GETTIM
 DS5RTC_TIMDEF:	; DEFAULT TIME VALUE TO INIT CLOCK
 		.DB	$00,$01,$01	; 2000-01-01
 		.DB	$00,$00,$00	; 00:00:00
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_DS5RTC	.EQU	$
+SIZ_DS5RTC	.EQU	END_DS5RTC - ORG_DS5RTC
+;	
+	MEMECHO	"DS5RTC occupies "
+	MEMECHO	SIZ_DS5RTC
+	MEMECHO	" bytes.\n"

Source/HBIOS/ds7rtc.asm

@@ -25,6 +25,23 @@ DS7_CTL		.EQU	(DS7_OUT | DS7_SQWE | DS7_RATE)
 ;
 		DEVECHO	"DS1307: ENABLED\n"
 ;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_DS7	.EQU	$
+;
+	.DW	SIZ_DS7		; MODULE SIZE
+	.DW	DS7_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+DS7_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	;CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	;JP	Z,DS7RTC_PREINIT	; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,DS7RTC_INIT		; DO INIT
+	RET				; DONE
+;
 ;-----------------------------------------------------------------------------
 ; DS1307 INITIALIZATION
 ;
@@ -447,3 +464,14 @@ DS7_BCD:PUSH	HL
 DS7_BUF:	.FILL	8,0				; BUFFER FOR TIME, DATE AND CONTROL
 ;DS7_COLD	.DB	$80,$00,$00,$01,$01,$01,$00	; COLD START RTC SETTINGS
 ;
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_DS7	.EQU	$
+SIZ_DS7	.EQU	END_DS7 - ORG_DS7
+;	
+	MEMECHO	"DS7 occupies "
+	MEMECHO	SIZ_DS7
+	MEMECHO	" bytes.\n"

Source/HBIOS/dsrtc.asm

@@ -162,6 +162,23 @@ DS2d8k		.EQU	%10101011	; 2 DIODES 8K RESISTOR
 ;
 DSRTC_BUFSIZ	.EQU	7		; 7 BYTE BUFFER (YYMMDDHHMMSSWW)
 ;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_DSRTC	.EQU	$
+;
+	.DW	SIZ_DSRTC		; MODULE SIZE
+	.DW	DSRTC_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+DSRTC_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	JP	Z,DSRTC_PREINIT		; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,DSRTC_INIT		; DO INIT
+	RET				; DONE
+;
 ; RTC DEVICE PRE-INITIALIZATION ENTRY
 ;
 DSRTC_PREINIT:
@@ -765,3 +782,14 @@ DSRTC_TIMBUF	.FILL	6,0		; 6 BYTES FOR GETTIM
 DSRTC_TIMDEF:	; DEFAULT TIME VALUE TO INIT CLOCK
 		.DB	$00,$01,$01	; 2000-01-01
 		.DB	$00,$00,$00	; 00:00:00
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_DSRTC	.EQU	$
+SIZ_DSRTC	.EQU	END_DSRTC - ORG_DSRTC
+;	
+	MEMECHO	"DSRTC occupies "
+	MEMECHO	SIZ_DSRTC
+	MEMECHO	" bytes.\n"

Source/HBIOS/duart.asm

@@ -169,6 +169,23 @@ DUART_MR2_STOP2		.EQU	%00001111	; 2 STOP BITS (2.5 IF 5 BITS/CHAR)
 #DEFINE	DUART_INP(RID)	CALL DUART_INP_IMP \ .DB RID
 #DEFINE	DUART_OUTP(RID)	CALL DUART_OUTP_IMP \ .DB RID
 ;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_DUART	.EQU	$
+;
+	.DW	SIZ_DUART		; MODULE SIZE
+	.DW	DUART_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+DUART_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	JP	Z,DUART_PREINIT		; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,DUART_INIT		; DO INIT
+	RET				; DONE
+;
 ;
 ;
 DUART_PREINIT:
@@ -879,3 +896,14 @@ DUART1B_CFG:
 #ENDIF
 ;
 DUART_CFGCNT	.EQU    ($ - DUART_CFG) / DUART_CFGSIZ
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_DUART	.EQU	$
+SIZ_DUART	.EQU	END_DUART - ORG_DUART
+;	
+	MEMECHO	"DUART occupies "
+	MEMECHO	SIZ_DUART
+	MEMECHO	" bytes.\n"

Source/HBIOS/ef.asm

@@ -158,6 +158,23 @@ EF_SCREENSIZE	.EQU	EF_DROWS * EF_DLINES
 	DEVECHO	EF_BASE
 	DEVECHO	"\n"
 ;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_EF	.EQU	$
+;
+	.DW	SIZ_EF			; MODULE SIZE
+	.DW	EF_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+EF_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	;CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	;JP	Z,EF_PREINIT		; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,EF_INIT		; DO INIT
+	RET				; DONE
+;
 ;======================================================================
 ; VDU DRIVER - INITIALIZATION
 ;======================================================================
@@ -1087,3 +1104,14 @@ EF_BUF:
 #IF (EF_SIZE = V40X24)
 	.FILL 2*EF_DLINES*EF_DROWS	;512,0
 #ENDIF
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_EF	.EQU	$
+SIZ_EF	.EQU	END_EF - ORG_EF
+;	
+	MEMECHO	"EF occupies "
+	MEMECHO	SIZ_EF
+	MEMECHO	" bytes.\n"

Source/HBIOS/esp.asm

@@ -58,6 +58,23 @@ ESP_CFG_BSYMSK	.EQU	4		; ESP BUSY MASK
 	DEVECHO	ESP_IOBASE
 	DEVECHO	"\n"
 ;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_ESP	.EQU	$
+;
+	.DW	SIZ_ESP		; MODULE SIZE
+	.DW	ESP_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+ESP_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	;CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	;JP	Z,ESP_PREINIT		; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,ESP_INIT		; DO INIT
+	RET				; DONE
+;
 ; GLOBAL ESP INITIALIZATION
 ;
 ESP_INIT:
@@ -708,3 +725,14 @@ ESPSER1_CFG:
 ;
 ;
 ESPSER_DEVCNT	.DB	0			; ESPSER DEVICES COUNT
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_ESP	.EQU	$
+SIZ_ESP	.EQU	END_ESP - ORG_ESP
+;	
+	MEMECHO	"ESP occupies "
+	MEMECHO	SIZ_ESP
+	MEMECHO	" bytes.\n"

Source/HBIOS/espsd.asm

@@ -123,6 +123,23 @@ ESPSD_IOBASE		.EQU	2	; IO BASE ADDRESS (BYTE)
 ESPSD_STAT		.EQU	3	; LAST STATUS (BYTE)
 ESPSD_MEDCAP		.EQU	4	; MEDIA CAPACITY (DWORD)
 ESPSD_LBA		.EQU	8	; OFFSET OF LBA (DWORD)
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_ESPSD	.EQU	$
+;
+	.DW	SIZ_ESPSD		; MODULE SIZE
+	.DW	ESPSD_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+ESPSD_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	;CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	;JP	Z,ESPSD_PREINIT		; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,ESPSD_INIT		; DO INIT
+	RET				; DONE
 ;                                       
 ESPSD_CFGSIZ		.EQU	12	; SIZE OF CFG TBL ENTRIES
 ;
@@ -288,8 +305,9 @@ ESPSD_INIT5:
 	CALL	ESPSD_INITDEV		; INITIALIZE DEVICE
 #IF (ESPSDTRACE < 2)
 	JP	NZ,ESPSD_PRTSTAT
-#ENDIF
+#ELSE
 	RET	NZ
+#ENDIF
 ;
 	CALL	ESPSD_PRTPREFIX		; TAG FOR ACTIVE DEVICE
 ;
@@ -345,7 +363,7 @@ ESPSD_READ:
 	;;;LD	A,'R'
 	;;;CALL	COUT
 	;;;CALL	PRTHEXWORDHL
-	LD	A,ESPSD_CMD_READ	; SETUP FOR BLOCK READ CMD
+	LD	E,ESPSD_CMD_READ	; SETUP FOR BLOCK READ CMD
 	JP	ESPSD_IO		; CONTINUE TO GENERIC IO ROUTINE
 ;
 ;
@@ -356,7 +374,7 @@ ESPSD_WRITE:
 	;;;LD	A,'W'
 	;;;CALL	COUT
 	;;;CALL	PRTHEXWORDHL
-	LD	A,ESPSD_CMD_WRITE	; SETUP FOR BLOCK WRITE CMD
+	LD	E,ESPSD_CMD_WRITE	; SETUP FOR BLOCK WRITE CMD
 	JP	ESPSD_IO		; CONTINUE TO GENERIC IO ROUTINE
 ;
 ;
@@ -501,15 +519,23 @@ ESPSD_INITDEV1:
 ; COMMON SECTOR I/O
 ;
 ESPSD_IO:
-	LD	(ESPSD_CMDVAL),A	; SAVE THE COMMAND
-	LD	(ESPSD_DSKBUF),HL	; SAVE DISK BUFFER ADDRESS
-;
-	; CHECK FOR ERROR STATUS AND REINIT?
 ;
 #IF (ESPSDTRACE == 1)
-	LD	HL,ESPSD_PRTERR		; SET UP SD_PRTERR
-	PUSH	HL			; ... TO FILTER ALL EXITS
+	PUSH	HL
+	LD	HL,ESPSD_PRTERR		; SET UP ESPSD_PRTERR
+	EX	(SP),HL			; ... TO FILTER ALL EXITS
 #ENDIF
+;
+	PUSH	DE
+	PUSH	HL
+	CALL	ESPSD_CHKERR		; CHECK FOR ERR STATUS AND RESET IF SO
+	POP	HL
+	POP	DE
+	RET	NZ			; BAIL OUT ON ERROR
+;
+	LD	A,E			; COMMAND TO ACCUM
+	LD	(ESPSD_CMDVAL),A	; SAVE THE COMMAND
+	LD	(ESPSD_DSKBUF),HL	; SAVE DISK BUFFER ADDRESS
 ;
 	; SELECT PRI/SEC DEVICE
 	CALL	ESPSD_SELECT		; SELECT DEVICE
@@ -532,7 +558,7 @@ ESPSD_IO:
 ESPSD_IO2:
 	CALL	ESPSD_BLKWRITE		; DO THE WRITE
 ESPSD_IO3:
-	JP	NZ,ESPSD_ERR		; ON ERROR, RECORD AND BAIL OUT
+	JR	NZ,ESPSD_IO4		; IF ERROR, SKIP INCREMENT
 ;
 	; INCREMENT LBA
 	LD	A,ESPSD_LBA		; LBA OFFSET
@@ -544,11 +570,24 @@ ESPSD_IO3:
 	INC	(HL)			; BUMP DMA BY
 	INC	(HL)			; ... 512 BYTES
 ;
-	; CLEAN UP
-	LD	HL,(ESPSD_DSKBUF)	; CURRENT DMA TO HL
 	XOR	A			; SIGNAL SUCCESS
+ESPSD_IO4:
+	LD	HL,(ESPSD_DSKBUF)	; CURRENT DMA TO HL
+	OR	A			; SET FLAGS
+	RET	Z			; DONE IF NO ERROR
+	LD	A,ERR_IO		; SIGNAL IO ERROR
+	OR	A			; SET FLAGS
 	RET				; AND DONE
 ;
+; CHECK CURRENT DEVICE FOR ERROR STATUS AND ATTEMPT TO RECOVER
+; VIA RESET IF DEVICE IS IN ERROR.
+;
+ESPSD_CHKERR:
+	LD	A,(IY+ESPSD_STAT)	; GET STATUS
+	OR	A			; SET FLAGS
+	CALL	NZ,ESPSD_RESET		; IF ERROR STATUS, RESET BUS
+	RET
+;
 ;=============================================================================
 ; COMMAND PROCESSING
 ;=============================================================================
@@ -568,11 +607,9 @@ ESPSD_INITCARD:
 ;
 	; GET CAPACITY
 	LD	E,ESPSD_CMD_CAP		; GET CAPACITY COMMAND
-	CALL	ESPSD_CMD_SLOW		; SEND IT
+	CALL	ESPSD_CMD		; SEND IT
 	RET	NZ			; HANDLE ERROR
 ;
-
-
 	LD	A,ESPSD_MEDCAP		; OFFSET TO CAPACITY FIELD
 	CALL	LDHLIYA			; HL := IY + A, REG A TRASHED
 	LD	A,4			; START AT END FOR LITTLE ENDIAN
@@ -582,7 +619,7 @@ ESPSD_INITCARD:
 ESPSD_INITCARD1:
 	DEC	HL			; DEC POINTER
 	PUSH	BC			; SAVE LOOP CONTROL
-	CALL	ESPSD_GETBYTE_SLOW	; FIRST BYTE (MSB)
+	CALL	ESPSD_GETBYTE		; FIRST BYTE (MSB)
 	POP	BC			; RESTORE LOOP CONTROL
 	RET	NZ			; HANDLE ERROR
 	LD	(HL),E			; SAVE IT
@@ -594,18 +631,18 @@ ESPSD_INITCARD1:
 ;
 ESPSD_FWVER:
 	LD	E,ESPSD_CMD_FWVER	; FWVER COMMAND
-	CALL	ESPSD_CMD_SLOW		; SEND IT
+	CALL	ESPSD_CMD		; SEND IT
 	RET	NZ			; HANDLE ERROR
-	CALL	ESPSD_GETBYTE_SLOW	; GET BOARD ID
+	CALL	ESPSD_GETBYTE		; GET BOARD ID
 	RET	NZ			; HANDLE ERROR
 	LD	D,E			; SAVE IN D
-	CALL	ESPSD_GETBYTE_SLOW	; GET VER MAJOR
+	CALL	ESPSD_GETBYTE		; GET VER MAJOR
 	RET	NZ			; HANDLE ERROR
 	LD	H,E			; PUT IN H
-	CALL	ESPSD_GETBYTE_SLOW	; GET VER MINOR
+	CALL	ESPSD_GETBYTE		; GET VER MINOR
 	RET	NZ			; HANDLE ERROR
 	LD	L,E			; PUT IN H
-	CALL	ESPSD_GETBYTE_SLOW	; GET RESULT
+	CALL	ESPSD_GETBYTE		; GET RESULT
 	RET	NZ			; HANDLE ERROR
 	LD	A,E			; RESULT TO ACCUM
 	LD	E,D			; BOARD ID BACK TO E
@@ -626,10 +663,10 @@ ESPSD_SELECT:
 ;
 ESPSD_RUNCMD:
 	LD	E,A			; PUT IN E
-	CALL	ESPSD_CMD_SLOW		; SEND COMMAND
+	CALL	ESPSD_CMD		; SEND COMMAND
 	RET	NZ			; HANDLE ERROR
 ESPSD_GETRESULT:
-	CALL	ESPSD_GETBYTE_SLOW	; GET RESULT
+	CALL	ESPSD_GETBYTE		; GET RESULT
 	RET	NZ			; HANDLE ERROR
 	LD	A,E			; RESULT TO ACCUM
 	OR	A			; SET FLAGS
@@ -644,7 +681,7 @@ ESPSD_GETRESULT:
 ;
 ESPSD_SETLBA:
 	LD	E,ESPSD_CMD_SETLBA	; SETLBA COMMAND
-	CALL	ESPSD_CMD_SLOW		; SEND IT
+	CALL	ESPSD_CMD		; SEND IT
 	RET	NZ			; HANDLE ERROR
 	LD	A,4			; LITTLE ENDIAN
 	CALL	ADDHLA			; BUMP TO END OF LBA BYTES
@@ -654,12 +691,12 @@ ESPSD_SETLBA1:
 	DEC	HL			; DEC POINTER
 	LD	E,(HL)			; GET NEXT BYTE TO SEND
 	PUSH	BC			; SAVE LOOP CONTROL
-	CALL	ESPSD_PUTBYTE_SLOW	; SEND BYTE
+	CALL	ESPSD_PUTBYTE		; SEND BYTE
 	POP	BC			; RESTORE LOOP CONTROL
 	RET	NZ			; HANDLE ERROR
 	DJNZ	ESPSD_SETLBA1		; LOOP AS NEEDED
 ;
-	CALL	ESPSD_GETBYTE_SLOW	; GET RESULT
+	CALL	ESPSD_GETBYTE		; GET RESULT
 	RET	NZ			; HANDLE ERROR
 	LD	A,E			; RESULT TO ACCUM
 	OR	A			; SET FLAGS
@@ -672,7 +709,7 @@ ESPSD_SETLBA1:
 ;
 ESPSD_BLKREAD:
 	LD	E,ESPSD_CMD_READ
-	CALL	ESPSD_CMD_SLOW
+	CALL	ESPSD_CMD
 	RET	NZ
 ;
 	LD	B,0			; LOOP COUNTER
@@ -680,13 +717,13 @@ ESPSD_BLKREAD:
 #IF FALSE
 ESPSD_BLKREAD1:
 	PUSH	BC
-	CALL	ESPSD_GETBYTE_SLOW
+	CALL	ESPSD_GETBYTE
 	POP	BC
 	RET	NZ
 	LD	(HL),E
 	INC	HL
 	PUSH	BC
-	CALL	ESPSD_GETBYTE_SLOW
+	CALL	ESPSD_GETBYTE
 	POP	BC
 	RET	NZ
 	LD	(HL),E
@@ -699,21 +736,20 @@ ESPSD_BLKREAD1:
 	CALL	ESPSD_BLKREAD2		; DO SECOND 256 BYTES
 #ENDIF
 ;
-	CALL	ESPSD_GETBYTE_SLOW	; GET RESULT
+	CALL	ESPSD_GETBYTE		; GET RESULT
 	RET	NZ			; HANDLE ERROR
 	LD	A,E			; RESULT TO ACCUM
 	OR	A			; SET FLAGS
-	RET	Z			; GOOD RETURN
-	LD	A,ESPSD_STIOERR		; CALL THIS AN IO ERROR
-	OR	A			; SET FLAGS
-	RET				; DONE
+	JP	NZ,ESPSD_IOERR		; HANDLE AS IO ERROR
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND DONE
 ;
 ESPSD_BLKREAD2:
 	; READ BYTES FAST (NO TIMEOUT CHECK)
 	DEC	C			; BACK TO STATUS PORT
 ESPSD_BLKREAD2A:
-#IF (PLATFORM == PLT_S100)
-	IN	A,(C)			; EXTRA READ FOR S100 STABILITY
+#IF (PLATFORM == PLT_SZ180)
+	IN	A,(C)			; EXTRA READ FOR Z180 STABILITY
 #ENDIF
 	IN	A,(C)			; GET STATUS
 	JP	P,ESPSD_BLKREAD2A	; LOOP TILL DATA READY
@@ -726,7 +762,7 @@ ESPSD_BLKREAD2A:
 ;
 ESPSD_BLKWRITE:
 	LD	E,ESPSD_CMD_WRITE
-	CALL	ESPSD_CMD_SLOW
+	CALL	ESPSD_CMD
 	RET	NZ
 ;
 	LD	B,0			; LOOP COUNTER
@@ -736,13 +772,13 @@ ESPSD_BLKWRITE1:
 	LD	E,(HL)
 	INC	HL
 	PUSH	BC
-	CALL	ESPSD_PUTBYTE_SLOW
+	CALL	ESPSD_PUTBYTE
 	POP	BC
 	RET	NZ
 	LD	E,(HL)
 	INC	HL
 	PUSH	BC
-	CALL	ESPSD_PUTBYTE_SLOW
+	CALL	ESPSD_PUTBYTE
 	POP	BC
 	RET	NZ
 	DJNZ	ESPSD_BLKWRITE1
@@ -753,21 +789,20 @@ ESPSD_BLKWRITE1:
 	CALL	ESPSD_BLKWRITE2		; DO SECOND 256 BYTES
 #ENDIF
 ;
-	CALL	ESPSD_GETBYTE_SLOW	; GET RESULT
+	CALL	ESPSD_GETBYTE		; GET RESULT
 	RET	NZ			; HANDLE ERROR
 	LD	A,E			; RESULT TO ACCUM
 	OR	A			; SET FLAGS
-	RET	Z			; GOOD RETURN
-	LD	A,ESPSD_STIOERR		; CALL THIS AN IO ERROR
-	OR	A			; SET FLAGS
-	RET				; DONE
+	JP	NZ,ESPSD_IOERR		; HANDLE AS IO ERROR
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND DONE
 ;
 ESPSD_BLKWRITE2:
 	; WRITE BYTES FAST (NO TIMEOUT CHECK)
 	DEC	C			; BACK TO STATUS PORT
 ESPSD_BLKWRITE2A:
-#IF (PLATFORM == PLT_S100)
-	IN	A,(C)			; EXTRA READ FOR S100 STABILITY
+#IF (PLATFORM == PLT_SZ180)
+	IN	A,(C)			; EXTRA READ FOR Z180 STABILITY
 #ENDIF
 	IN	A,(C)			; GET STATUS
 	RRA				; SEND RDY BIT TO CF
@@ -791,126 +826,103 @@ ESPSD_CMD:
 	RET	NZ
 	JR	ESPSD_PUTBYTE
 ;
-; SEND COMMAND BYTE IN E TO ESP32
-;
-ESPSD_CMD_SLOW:
-	PUSH	DE
-	LD	E,$33			; COMMAND PREFIX BYTE
-	CALL	ESPSD_PUTBYTE_SLOW
-	POP	DE
-	RET	NZ
-	JR	ESPSD_PUTBYTE_SLOW
-;
 ; WRITE BYTE IN E TO ESP32
 ; RETURN STATUS IN A (0=SUCCESS)
+; BC IS DESTROYED
 ;
 ESPSD_PUTBYTE:
 #IF (ESPSDTRACE >= 3)
 	CALL	PC_GT
 #ENDIF
-	LD	B,0
+
+	PUSH	HL			; PRESERVE HL
 	LD	C,(IY+ESPSD_IOBASE)
-ESPSD_PUTBYTE1:
-#IF (PLATFORM == PLT_S100)
-	IN	A,(C)			; EXTRA READ FOR S100 STABILITY
+	LD	HL,100 * CPUMHZ		; SETUP OUTER LOOP COUNTER
+;
+ESPSD_PUTBYTE1:	; OUTER LOOP
+	LD	B,0			; SETUP INNER LOOP COUNTER
+;
+ESPSD_PUTBYTE2:	; INNER LOOP
+#IF (PLATFORM == PLT_SZ180)
+	IN	A,(C)			; EXTRA READ FOR Z180 STABILITY
 #ENDIF
-	IN	A,(C)
-	BIT	0,A
-	JR	Z,ESPSD_PUTBYTE2
-	DJNZ	ESPSD_PUTBYTE1
-	LD	A,ESPSD_STTO
-	OR	A
-	RET
-ESPSD_PUTBYTE2:
-	; NOPS NEEDED FOR RELIABILITY
+	IN	A,(C)			; READ STATUS
+	BIT	0,A			; ISOLATE SENDACT (TXF)
+	JR	Z,ESPSD_PUTBYTE3	; IF NOT ACTIVE, GO TO SEND BYTE
+	DJNZ	ESPSD_PUTBYTE2		; LOOP SOME MORE
+;
+	DEC	HL			; DEC OUTER LOOP COUNTER
+	LD	A,H			; TEST COUNTER
+	OR	L			; ... FOR ZERO
+	JR	NZ,ESPSD_PUTBYTE1	; IF NOT ZERO, LOOP MORE
+;
+	; HANDLE TIMEOUT
+	POP	HL			; RECOVER HL
+	JP	ESPSD_TO		; RETURN VIA ERROR HANDLER
+;
+ESPSD_PUTBYTE3:
+	POP	HL			; RECOVER HL
+	; SEND THE DATA BYTE
+	; NOPS NEEDED FOR RELIABILITY???
 	;NOP \ NOP \ NOP \ NOP \ NOP \ NOP
-	INC	C
-	OUT	(C),E
+	INC	C			; BUMP TO DATA PORT
+	OUT	(C),E			; SEND IT
 ;
 #IF (ESPSDTRACE >= 3)
 	LD	A,E
 	CALL	PRTHEXBYTE
 #ENDIF
 ;	
-	XOR	A
-	RET
-;
-; WRITE BYTE TO ESP32 FROM E WITH EXTRA LONG TIMEOUT
-;
-ESPSD_PUTBYTE_SLOW:
-	PUSH	HL
-	LD	HL,100 * CPUMHZ		; CPU SPEED SCALED TIMEOUT
-ESPSD_PUTBYTE_SLOW1:
-	PUSH	HL
-	CALL	ESPSD_PUTBYTE
-	POP	HL
-	JR	Z,ESPSD_PUTBYTE_SLOW_Z
-	DEC	HL
-	LD	A,H
-	OR	L
-	JR	NZ,ESPSD_PUTBYTE_SLOW1
-	LD	A,ESPSD_STTO
-ESPSD_PUTBYTE_SLOW_Z:
-	;CALL	PC_SPACE		; *DEBUG*
-	;CALL	PRTHEXWORDHL		; *DEBUG*
-	POP	HL
-	OR	A			; SET FLAGS
-	RET
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
 ;
 ; READ BYTE FROM ESP32 INTO E
 ; RETURN STATUS IN A (0=SUCCESS)
+; BC IS DESTROYED
 ;
 ESPSD_GETBYTE:
 #IF (ESPSDTRACE >= 3)
 	CALL	PC_LT
 #ENDIF
-	LD	B,0
+
+	PUSH	HL			; PRESERVE HL
 	LD	C,(IY+ESPSD_IOBASE)
-ESPSD_GETBYTE1:
-#IF (PLATFORM == PLT_S100)
-	IN	A,(C)			; EXTRA READ FOR S100 STABILITY
+	LD	HL,100 * CPUMHZ		; SETUP OUTER LOOP COUNTER
+;
+ESPSD_GETBYTE1:	; OUTER LOOP
+	LD	B,0			; SETUP INNER LOOP COUNTER
+;
+ESPSD_GETBYTE2:	; INNER LOOP
+#IF (PLATFORM == PLT_SZ180)
+	IN	A,(C)			; EXTRA READ FOR Z180 STABILITY
 #ENDIF
-	IN	A,(C)
-	JP	M,ESPSD_GETBYTE2
-	DJNZ	ESPSD_GETBYTE1
-	LD	A,ESPSD_STTO
-	OR	A
-	RET
-ESPSD_GETBYTE2:
-	; NOPS NEEDED FOR RELIABILITY
+	IN	A,(C)			; READ STATUS
+	JP	M,ESPSD_GETBYTE3	; IF RCV READY, GO TO GET BYTE
+	DJNZ	ESPSD_GETBYTE2		; LOOP SOME MORE
+;
+	DEC	HL			; DEC OUTER LOOP COUNTER
+	LD	A,H			; TEST COUNTER
+	OR	L			; ... FOR ZERO
+	JR	NZ,ESPSD_GETBYTE1	; IF NOT ZERO, LOOP MORE
+;
+	; HANDLE TIMEOUT
+	POP	HL			; RECOVER HL
+	JP	ESPSD_TO		; RETURN VIA ERROR HANDLER
+;
+ESPSD_GETBYTE3:
+	POP	HL			; RECOVER HL
+	; NOPS NEEDED FOR RELIABILITY???
 	;NOP \ NOP \ NOP \ NOP \ NOP \ NOP
-	INC	C
-	IN	E,(C)
+	INC	C			; BUMP TO DATA PORT
+	IN	E,(C)			; GET DATA BYTE
 ;
 #IF (ESPSDTRACE >= 3)
 	LD	A,E
 	CALL	PRTHEXBYTE
 #ENDIF
 ;	
-	XOR	A
-	RET
-;
-; READ BYTE FROM ESP32 INTO E WITH EXTRA LONG TIMEOUT
-;
-ESPSD_GETBYTE_SLOW:
-	PUSH	HL
-	LD	HL,100 * CPUMHZ		; CPU SPEED SCALED TIMEOUT
-ESPSD_GETBYTE_SLOW1:
-	PUSH	HL
-	CALL	ESPSD_GETBYTE
-	POP	HL
-	JR	Z,ESPSD_GETBYTE_SLOW_Z
-	DEC	HL
-	LD	A,H
-	OR	L
-	JR	NZ,ESPSD_GETBYTE_SLOW1
-	LD	A,ESPSD_STTO
-ESPSD_GETBYTE_SLOW_Z:
-	;CALL	PC_SPACE		; *DEBUG*
-	;CALL	PRTHEXWORDHL		; *DEBUG*
-	POP	HL
-	OR	A			; SET FLAGS
-	RET
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
 ;
 ;=============================================================================
 ; ERROR HANDLING AND DIAGNOSTICS
@@ -1035,3 +1047,14 @@ ESPSD_CMDVAL	.DB	0		; PENDING COMMAND FOR IO FUCNTIONS
 ESPSD_DSKBUF	.DW	0		; ACTIVE DISK BUFFER
 ;
 ESPSD_DEVNUM	.DB	0		; TEMP DEVICE NUM USED DURING INIT
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_ESPSD	.EQU	$
+SIZ_ESPSD	.EQU	END_ESPSD - ORG_ESPSD
+;	
+	MEMECHO	"ESPSD occupies "
+	MEMECHO	SIZ_ESPSD
+	MEMECHO	" bytes.\n"

Source/HBIOS/ez80cpu.asm

@@ -25,6 +25,24 @@
 ; 4. Set Timer Tick Frequency
 ;
 
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_EZ80CPU	.EQU	$
+;
+	.DW	SIZ_EZ80CPU		; MODULE SIZE
+	.DW	EZ80CPU_INITPHASE	; ADR OF INIT PHASE HANDLER
+;
+EZ80CPU_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	JP	Z,EZ80_PREINIT		; DO PREINIT
+	;CP	HB_PHASE_INIT		; INIT PHASE?
+	;JP	Z,EZ80_INIT		; DO INIT
+	RET				; DONE
+
 EZ80_PREINIT:
 	EZ80_TMR_INT_DISABLE()
 
@@ -330,3 +348,15 @@ _EZ80_EXTN_IY_TO_MB_IY:
 	.DB	$5B, $FD, $77, $02			; LD.LIL	(IY+2), A
 	.DB	$49, $FD, $E1				; POP.L		IY
 	RET
+
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_EZ80CPU	.EQU	$
+SIZ_EZ80CPU	.EQU	END_EZ80CPU - ORG_EZ80CPU
+;	
+	MEMECHO	"EZ80CPU occupies "
+	MEMECHO	SIZ_EZ80CPU
+	MEMECHO	" bytes.\n"

Source/HBIOS/ez80rtc.asm

@@ -7,6 +7,24 @@ EZ80RTC_BUFSIZ	.EQU	6	; SIX BYTE BUFFER (YYMMDDHHMMSS)
 ;
 ; RTC DEVICE INITIALIZATION ENTRY
 
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_EZ80RTC	.EQU	$
+;
+	.DW	SIZ_EZ80RTC		; MODULE SIZE
+	.DW	EZ80RTC_INITPHASE	; ADR OF INIT PHASE HANDLER
+;
+EZ80RTC_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	;CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	;JP	Z,EZ80RTC_PREINIT	; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,EZ80RTC_INIT		; DO INIT
+	RET				; DONE
+
 EZ80RTC_INIT:
 	; display driver install message
 	; delegate init function to firmware
@@ -171,3 +189,14 @@ EZ80RTC_DT	.DB	01
 EZ80RTC_HH	.DB	00
 EZ80RTC_MM	.DB	00
 EZ80RTC_SS	.DB	00
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_EZ80RTC	.EQU	$
+SIZ_EZ80RTC	.EQU	END_EZ80RTC - ORG_EZ80RTC
+;	
+	MEMECHO	"EZ80RTC occupies "
+	MEMECHO	SIZ_EZ80RTC
+	MEMECHO	" bytes.\n"

Source/HBIOS/ez80tmr.asm

@@ -11,6 +11,24 @@
 ;	 HBIOS System calls SYS_GETTIMER, SYS_GETSECS, SYS_SETTIMER, SYS_SETSECS are implemented within HBIOS
 ;
 
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_EZ80TMR	.EQU	$
+;
+	.DW	SIZ_EZ80TMR		; MODULE SIZE
+	.DW	EZ80TMR_INITPHASE	; ADR OF INIT PHASE HANDLER
+;
+EZ80TMR_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	;CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	;JP	Z,EZ80_TMR_PREINIT	; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,EZ80_TMR_INIT		; DO INIT
+	RET				; DONE
+
 #IF (EZ80TIMER == EZ80TMR_INT)
 EZ80_TMR_INIT:
 	CALL	NEWLINE			; FORMATTING
@@ -86,3 +104,14 @@ SYS_SETSECS:
 EZ80_TMR_INIT:
 	RET
 #ENDIF
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_EZ80TMR	.EQU	$
+SIZ_EZ80TMR	.EQU	END_EZ80TMR - ORG_EZ80TMR
+;	
+	MEMECHO	"EZ80TMR occupies "
+	MEMECHO	SIZ_EZ80TMR
+	MEMECHO	" bytes.\n"

Source/HBIOS/ez80uart.asm

@@ -34,6 +34,24 @@ UART0_RBR	.EQU	$C0
 LSR_THRE	.EQU	$20
 LSR_DR		.EQU	$01
 
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_EZ80UART	.EQU	$
+;
+	.DW	SIZ_EZ80UART		; MODULE SIZE
+	.DW	EZ80UART_INITPHASE	; ADR OF INIT PHASE HANDLER
+;
+EZ80UART_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	JP	Z,EZUART_PREINIT	; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,EZUART_INIT		; DO INIT
+	RET				; DONE
+
 EZUART_PREINIT:
 	LD	BC, EZUART_FNTBL
 	LD	DE, EZUART_CFG		
@@ -322,3 +340,14 @@ EZUART_FNTBL:
 #IF (($ - EZUART_FNTBL) != (CIO_FNCNT * 2))
 	.ECHO	"*** INVALID EZUART FUNCTION TABLE ***\n"
 #ENDIF
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_EZ80UART	.EQU	$
+SIZ_EZ80UART	.EQU	END_EZ80UART - ORG_EZ80UART
+;	
+	MEMECHO	"EZ80UART occupies "
+	MEMECHO	SIZ_EZ80UART
+	MEMECHO	" bytes.\n"

Source/HBIOS/fd.asm

@@ -124,6 +124,23 @@ FRC_TOGETRES	.EQU	-13H		; ED
 FRC_TOEXEC	.EQU	-14H		; EC
 FRC_TOSEEKWT	.EQU	-15H		; EB
 ;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_FD	.EQU	$
+;
+	.DW	SIZ_FD		; MODULE SIZE
+	.DW	FD_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+FD_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	;CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	;JP	Z,FD_PREINIT		; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,FD_INIT		; DO INIT
+	RET				; DONE
+;
 ; FD DEVICE CONFIGURATION
 ;
 FD_DEVCNT	.EQU	FDCNT		; 2 DEVICES SUPPORTED
@@ -1120,23 +1137,14 @@ FD_WRITE:
 ;
 FD_RW:
 	LD	(FCD_DOP),A		; SAVE REQUESTED DISK OPERATION
-	LD	A,E			; BLOCK COUNT TO A
-	OR	A			; SET FLAGS
-	RET	Z			; ZERO SECTOR I/O, RETURN W/ E=0 & A=0
-	LD	B,A			; INIT SECTOR DOWNCOUNTER
-	LD	C,0			; INIT SECTOR READ/WRITE COUNT
-
-	PUSH	BC			; SAVE COUNTERS
 	CALL	FD_GEOM			; E := SPT, D := HDS
-	POP	BC			; RESTORE COUNTERS
 	JR	NZ,FD_RW4		; BAIL OUT ON ERROR
 	RES	7,D			; MAKE SURE LBA BIT IS CLEARED
 	LD	(FD_CURGEOM),DE		; SAVE AS FD_CURSPT & FD_CURHDS
 
 FD_RW1:
-	PUSH	BC			; SAVE COUNTERS
 	CALL	FD_RUN			; PERFORM SECTOR READ/WRITE
-	JR	NZ,FD_RW3		; IF ERROR, SKIP INCREMENT
+	JR	NZ,FD_RW4		; IF ERROR, SKIP INCREMENT
 
 	; INCREMENT SECTOR AND CHECK FOR TRACK OVERFLOW
 	LD	A,FD_HSTSEC		; HST SECTOR OFFSET IN CFG
@@ -1166,13 +1174,7 @@ FD_RW2:
 	INC	(HL)			; BUMP DMA BY
 	INC	(HL)			; ... 512 BYTES
 	XOR	A			; SIGNAL SUCCESS
-FD_RW3:
-	POP	BC			; RECOVER COUNTERS
-	JR	NZ,FD_RW4		; IF ERROR, BAIL OUT
-	INC	C			; BUMP COUNT OF SECTORS READ
-	DJNZ	FD_RW1			; LOOP AS NEEDED
 FD_RW4:
-	LD	E,C			; SECTOR READ COUNT TO E
 	LD	HL,(FD_DSKBUF)		; CURRENT DMA TO HL
 	OR	A			; SET FLAGS BASED ON RETURN CODE
 	RET				; AND RETURN, A HAS RETURN CODE
@@ -2239,3 +2241,14 @@ FD_DSKBUF	.DW	0
 FD_CURGEOM	.EQU	$		; TWO BYTES BELOW
 FD_CURSPT	.DB	0		; CURRENT SECTORS PER TRACK
 FD_CURHDS	.DB	0		; CURRENT HEADS
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_FD	.EQU	$
+SIZ_FD	.EQU	END_FD - ORG_FD
+;	
+	MEMECHO	"FD occupies "
+	MEMECHO	SIZ_FD
+	MEMECHO	" bytes.\n"

Source/HBIOS/gdc.asm

@@ -67,6 +67,23 @@ GDC_COLS	.EQU	80
 TERMENABLE	.SET	TRUE		; INCLUDE TERMINAL PSEUDODEVICE DRIVER
 KBDENABLE	.SET	TRUE		; INCLUDE KBD KEYBOARD SUPPORT
 ;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_GDC	.EQU	$
+;
+	.DW	SIZ_GDC			; MODULE SIZE
+	.DW	GDC_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+GDC_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	JP	Z,GDC_PREINIT		; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,GDC_INIT		; DO INIT
+	RET				; DONE
+;
 ;======================================================================
 ; GDC DRIVER - INITIALIZATION
 ;======================================================================
@@ -355,3 +372,14 @@ GDC_IDAT:
 	.DB	KBDMODE_PS2	; PS/2 8242 KEYBOARD CONTROLLER
 	.DB	GDC_KBDST
 	.DB	GDC_KBDDATA
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_GDC	.EQU	$
+SIZ_GDC	.EQU	END_GDC - ORG_GDC
+;	
+	MEMECHO	"GDC occupies "
+	MEMECHO	SIZ_GDC
+	MEMECHO	" bytes.\n"

Source/HBIOS/gm7303.asm

@@ -58,6 +58,23 @@ GM7303_FUNC_DDADR	.EQU	$80		; SET DDRAM ADDRESS
 	DEVECHO	GM7303BASE
 	DEVECHO	"\n"
 ;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE HEADER
+;--------------------------------------------------------------------------------------------------
+;
+ORG_GM7303	.EQU	$
+;
+	.DW	SIZ_GM7303		; MODULE SIZE
+	.DW	GM7303_INITPHASE		; ADR OF INIT PHASE HANDLER
+;
+GM7303_INITPHASE:
+	; INIT PHASE HANDLER, A=PHASE
+	CP	HB_PHASE_PREINIT	; PREINIT PHASE?
+	JP	Z,GM7303_PREINIT		; DO PREINIT
+	CP	HB_PHASE_INIT		; INIT PHASE?
+	JP	Z,GM7303_INIT		; DO INIT
+	RET				; DONE
+;
 ; HARDWARE RESET PRIOR TO ROMWBW CONSOLE INITIALIZATION
 ;
 GM7303_PREINIT:
@@ -639,3 +656,14 @@ GM7303_MSG_LDR_LOAD	.DB	"Load...",0
 GM7303_MSG_LDR_GO	.DB	"Go...",0
 GM7303_MSG_MON_RDY	.DB	"-CPU UP-",0
 GM7303_MSG_MON_BOOT	.DB	"Boot!",0
+;
+;--------------------------------------------------------------------------------------------------
+;   HBIOS MODULE TRAILER
+;--------------------------------------------------------------------------------------------------
+;
+END_GM7303	.EQU	$
+SIZ_GM7303	.EQU	END_GM7303 - ORG_GM7303
+;	
+	MEMECHO	"GM7303 occupies "
+	MEMECHO	SIZ_GM7303
+	MEMECHO	" bytes.\n"