Z280 Cleanup

Binary/RomList.txt

@@ -177,44 +177,28 @@ RCZ180 (RCZ180_nat.rom & RCZ180_ext.rom):
  - Support for Scott Baker floppy controllers (SMC & WDC) may
    be enabled in config
  - Support for J.B. Lang TMS9918 video card may be enabled in config
- - You must pick the _nat or _ext variant depending on which
-   memory module you are using:
-   - RCZ180_nat.rom uses the built-in Z180 memory manager
-     for use with memory modules allow direct physical
-     addressing of memory, such as the SC119
+ - You must pick the variant (_ext or _nat) depending
+   on which memory module you are using:
    - RCZ180_ext.rom uses external bank management to access
      memory, such as the 512K RAM/ROM module.
+   - RCZ180_nat.rom uses the built-in Z180 memory manager
+     for use with memory modules using direct physical
+     addressing of memory, such as the SC119.
  - Support for PropIO V2 may be enabled in config (PRPENABLE).  If
    enabled, will auto-detect and install associated
    video, keyboard and SD Card support if present.
 
-RCZ280 (RCZ280_ext.rom):
+RCZ280 (RCZ280_ext.rom, RCZ280_nat.rom, RCZ280_nat_zz.rom):
  - Assumes CPU oscillator of 24 MHz
- - Bus clock will be 6 MHz, so does not match RC2014 standard!!!
- - Requires 512K RAM/ROM module
+ - Bus clock will be 6 MHz or 12 MHz, so does not match RC2014 standard!!!
+ - Requires 512K RAM/ROM module (unless using ZZ80MB)
  - Auto detects Serial I/O Module (ACIA), Dual Serial
-   Module (SIO/2), and EP Dual UART.
+   Module (SIO), EP Dual UART (DUART), and built-in Z280 UART (Z2U).
+ - ACIA module is only supported on _ext variant.
+ - Built-in Z280 UART (Z2U) is buffered and interrupt driven only
+   on _nat and _nat_zz variants.  It uses polling I/O on _ext.
  - Console on whichever serial module is installed,
-   order of priority is UART, SIO, then ACIA.
- - Baud rate is determined by hardware, but normally 115200.
- - Auto support for RC2014 Compact Flash Module
- - Auto support for RC2014 PPIDE Module
- - Support for Scott Baker SIO board may be enabled in config
- - Support for Scott Baker floppy controllers (SMC & WDC) may
-   be enabled in config
- - Support for J.B. Lang TMS9918 video card may be enabled in config
- - Support for PropIO V2 may be enabled in config (PRPENABLE).  If
-   enabled, will auto-detect and install associated
-   video, keyboard and SD Card support if present.
-
-RCZ280 (RCZ280_nat.rom):
- - Assumes CPU oscillator of 24 MHz
- - Bus clock will be 6 MHz, so does not match RC2014 standard!!!
- - Requires native RAM/ROM module (linear memory)
- - Interrupt Mode 3 only (no ACIA support possible)
- - Auto detects Dual Serial Module (SIO/2), and EP Dual UART.
- - Console on whichever serial module is installed,
-   order of priority is UART, then SIO.
+   order of priority is UART, SIO, DUART, ACIA, Z2U
  - Baud rate is determined by hardware, but normally 115200.
  - Auto support for RC2014 Compact Flash Module
  - Auto support for RC2014 PPIDE Module
@@ -222,6 +206,15 @@ RCZ280 (RCZ280_nat.rom):
  - Support for Scott Baker floppy controllers (SMC & WDC) may
    be enabled in config
  - Support for J.B. Lang TMS9918 video card may be enabled in config
+ - You must pick the variant (_ext, _nat, or _nat_zz) depending
+   on which platform or memory module you are using:
+   - RCZ280_ext.rom uses external bank management to access
+     memory, such as the 512K RAM/ROM module.
+   - RCZ280_nat.rom uses the built-in Z280 memory manager
+     for use with memory modules using direct physical
+     addressing of memory, such as the SC119.
+   - RCZ280_nat_zz.rom is specifically for the ZZ80MB platform
+     which has both CPU and memory onboard.
  - Support for PropIO V2 may be enabled in config (PRPENABLE).  If
    enabled, will auto-detect and install associated
    video, keyboard and SD Card support if present.

Source/HBIOS/Config/RCZ280_ext.asm

@@ -32,7 +32,8 @@ CPUOSC		.SET	24000000	; CPU OSC FREQ IN MHZ
 ;
 INTMODE		.SET	1
 ;
-Z280_MEMWAIT	.SET	0		; Z280: MEMORY WAIT STATES (0-3)
+Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
+Z280_MEMHIWAIT	.SET	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
 Z280_IOWAIT	.SET	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 Z280_INTWAIT	.SET	0		; Z280: INT ACK WAIT STATUS (0-3)
 ;

Source/HBIOS/Config/RCZ280_nat.asm

@@ -30,11 +30,12 @@ CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
 CPUOSC		.SET	24000000	; CPU OSC FREQ IN MHZ
 ;
-MEMMGR		.SET	MM_Z280RC	; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.SET	MM_Z280		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 ;
 INTMODE		.SET	3
 ;
-Z280_MEMWAIT	.SET	0		; Z280: MEMORY WAIT STATES (0-3)
+Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
+Z280_MEMHIWAIT	.SET	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
 Z280_IOWAIT	.SET	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 Z280_INTWAIT	.SET	0		; Z280: INT ACK WAIT STATUS (0-3)
 ;

Source/HBIOS/Config/RCZ280_nat_zz.asm

@@ -26,4 +26,4 @@
 ;
 #include "Config/RCZ280_nat.asm"
 ;
-MEMMGR		.SET	MM_Z280ZZ	; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+RAMLOC		.SET	23		; START OF RAM AS POWER OF 2 (2^N)

Source/HBIOS/cfg_dyno.asm

@@ -28,8 +28,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_ezz80.asm

@@ -28,7 +28,7 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_master.asm

@@ -25,8 +25,9 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.SET	MM_NONE		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.SET	MM_NONE		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
@@ -40,7 +41,8 @@ Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
-Z280_MEMWAIT	.EQU	0		; Z280: MEMORY WAIT STATES (0-3)
+Z280_MEMLOWAIT	.EQU	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
+Z280_MEMHIWAIT	.EQU	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
 Z280_IOWAIT	.EQU	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 Z280_INTWAIT	.EQU	0		; Z280: INT ACK WAIT STATUS (0-3)
 ;

Source/HBIOS/cfg_mk4.asm

@@ -28,8 +28,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2

Source/HBIOS/cfg_n8.asm

@@ -28,8 +28,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMLOC		.EQU	0		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2

Source/HBIOS/cfg_rcz180.asm

@@ -28,8 +28,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_rcz280.asm

@@ -28,14 +28,17 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
+RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
 MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
-Z280_MEMWAIT	.EQU	0		; Z280: MEMORY WAIT STATES (0-3)
+Z280_MEMLOWAIT	.EQU	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
+Z280_MEMHIWAIT	.EQU	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
 Z280_IOWAIT	.EQU	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 Z280_INTWAIT	.EQU	0		; Z280: INT ACK WAIT STATUS (0-3)
 ;

Source/HBIOS/cfg_rcz80.asm

@@ -28,7 +28,7 @@ INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_sbc.asm

@@ -28,7 +28,7 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;

Source/HBIOS/cfg_scz180.asm

@@ -28,8 +28,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2

Source/HBIOS/cfg_zeta.asm

@@ -28,7 +28,7 @@ INTMODE		.EQU	0		; INTERRUPT MODE: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;

Source/HBIOS/cfg_zeta2.asm

@@ -28,7 +28,7 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280RC|Z280ZZ]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/std.asm

@@ -82,9 +82,8 @@ MM_SBC		.EQU	1		; ORIGINAL N8VEM/RBC Z80 SBC BANKED MEMORY
 MM_Z2		.EQU	2		; 16K X 4 BANKED MEMORY INTRODUCED ON ZETA2
 MM_N8		.EQU	3		; Z180 CUSTOMIZED FOR N8 MEMORY EXTENSIONS
 MM_Z180		.EQU	4		; Z180 NATIVE MEMORY MANAGER
-MM_Z280RC	.EQU	5		; Z280 NATIVE MEMORY MANAGER (RC STYLE)
-MM_Z280ZZ	.EQU	6		; Z280 NATIVE MEMORY MANAGER (ZZ80MB STYLE)
-MM_ZRC		.EQU	7		; ZRC BANK SWITCHING
+MM_Z280		.EQU	5		; Z280 NATIVE MEMORY MANAGER
+MM_ZRC		.EQU	6		; ZRC BANK SWITCHING
 ;
 ; BOOT STYLE
 ;

Source/HBIOS/z280.inc

@@ -57,7 +57,6 @@ Z280_UARTXCTL	.EQU	$12	; UART TRANSMIT CONTROL/STATUS REG
 Z280_UARTRCTL	.EQU	$14	; UART RECEIVE CONTROL/STATUS REG
 Z280_UARTRECV	.EQU	$16	; UART RECEIVE DATA REG
 Z280_UARTXMIT	.EQU	$18	; UART TRANSMIT DATA REG
-
 ;
 Z280_CT0_CFG	.EQU	$E0	; COUNTER/TIMER 0 CONFIG REG
 Z280_CT0_CMDST	.EQU	$E1	; COUNTER/TIMER 0 COMMAND/STATUS REG
@@ -73,4 +72,16 @@ Z280_CT2_CFG	.EQU	$F8	; COUNTER/TIMER 2 CONFIG REG
 Z280_CT2_CMDST	.EQU	$F9	; COUNTER/TIMER 2 COMMAND/STATUS REG
 Z280_CT2_TC	.EQU	$FA	; COUNTER/TIMER 2 TIME CONSTANT
 Z280_CT2_CT	.EQU	$FB	; COUNTER/TIMER 2 COUNT TIME
-
+;
+; Z280 INSTRUCTIONS (INCOMPLETE, JUST THE ONES USED)
+;
+.ADDINSTR	PCACHE	""	65ED	2 NOP 1
+.ADDINSTR	LDCTL	(C),HL	6EED	2 NOP 1
+.ADDINSTR	LDCTL	HL,(C)	66ED	2 NOP 1
+.ADDINSTR	IM	3	4EED	2 NOP 1
+.ADDINSTR	LDCTL	USP,HL	8FED	2 NOP 1
+.ADDINSTR	LDCTL	IY,(C)	66EDFD	3 NOP 1
+.ADDINSTR	LDCTL	(C),IY	6EEDFD	3 NOP 1
+.ADDINSTR	MULTU	A,*	F9EDFD	4 NOP 1
+.ADDINSTR	LD2	HL,(HL)	26ED	2 NOP 1
+.ADDINSTR	LD2	(HL),DE	1EED	2 NOP 1

Source/HBIOS/z2u.asm

@@ -173,10 +173,10 @@ Z2U_INT:
 ;
 	; START BY SELECTING I/O PAGE $FE (SAVING PREVIOUS VALUE)
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$66			; LDCTL HL,(C) ; GET CURRENT I/O PAGE
+	LDCTL	HL,(C)			; GET CURRENT I/O PAGE
 	PUSH	HL			; SAVE IT
 	LD	L,$FE			; NEW COUNTER/TIMER I/O PAGE
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; CHECK TO SEE IF SOMETHING IS ACTUALLY THERE
 	IN	A,(Z280_UARTRCTL)	; GET STATUS
@@ -199,11 +199,7 @@ Z2U_INTRCV1:
 Z2U_INTRCV2:
 	INC	HL			; HL NOW HAS ADR OF HEAD PTR
 	PUSH	HL			; SAVE ADR OF HEAD PTR
-	;LD	A,(HL)			; DEREFERENCE HL
-	;INC	HL
-	;LD	H,(HL)
-	;LD	L,A			; HL IS NOW ACTUAL HEAD PTR
-	.DB	$ED,$26			; LD HL,(HL) ; DEREFERENCE HL, HL IS NOW ACTUAL HEAD PTR
+	LD2	HL,(HL)			; DEREFERENCE HL, HL IS NOW ACTUAL HEAD PTR
 	LD	(HL),B			; SAVE CHARACTER RECEIVED IN BUFFER AT HEAD
 	INC	HL			; BUMP HEAD POINTER
 	POP	DE			; RECOVER ADR OF HEAD PTR
@@ -219,10 +215,7 @@ Z2U_INTRCV2:
 	INC	HL			; ... SO HL NOW HAS ADR OF ACTUAL BUFFER START
 Z2U_INTRCV3:
 	EX	DE,HL			; DE := HEAD PTR VAL, HL := ADR OF HEAD PTR
-	;LD	(HL),E			; SAVE UPDATED HEAD PTR
-	;INC	HL
-	;LD	(HL),D
-	.DB	$ED,$1E			;LD (HL),DE ; SAVE UPDATED HEAD PTR
+	LD2	(HL),DE			; SAVE UPDATED HEAD PTR
 
 	; CHECK FOR MORE PENDING...
 	IN	A,(Z280_UARTRCTL)	; GET STATUS
@@ -233,7 +226,7 @@ Z2U_INTRCV4:
 	; RESTORE I/O PAGE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
 	POP	HL			; RECOVER ORIGINAL I/O PAGE
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; RESTORE REGISTERS
 	POP	HL
@@ -267,7 +260,7 @@ Z2U_IN:
 	; START BY SELECTING I/O PAGE $FE
 	LD	L,$FE			; Z280 UART REGISTERS AT I/O PAGE $FE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; GET CHAR
 	IN	A,(Z280_UARTRECV)	; GET A BYTE
@@ -276,7 +269,7 @@ Z2U_IN:
 	; RESTORE I/O PAGE TO $00
 	LD	L,$00			; NORMAL I/O REG IS $00
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	XOR	A			; SIGNAL SUCCESS
 	RET				; DONE
@@ -334,7 +327,7 @@ Z2U_OUT:
 	; START BY SELECTING I/O PAGE $FE
 	LD	L,$FE			; Z280 UART REGISTERS AT I/O PAGE $FE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; WRITE CHAR
 	LD	A,E			; BYTE TO A
@@ -343,7 +336,7 @@ Z2U_OUT:
 	; RESTORE I/O PAGE TO $00
 	LD	L,$00			; NORMAL I/O REG IS $00
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;	
 	XOR	A			; SIGNAL SUCCESS
 	RET				; DONE
@@ -356,7 +349,7 @@ Z2U_IST:
 	; START BY SELECTING I/O PAGE $FE
 	LD	L,$FE			; Z280 UART REGISTERS AT I/O PAGE $FE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; GET RECEIVE STATUS
 	IN	A,(Z280_UARTRCTL)	; GET STATUS
@@ -365,11 +358,11 @@ Z2U_IST:
 	; RESTORE I/O PAGE TO $00
 	LD	L,$00			; NORMAL I/O REG IS $00
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	OR	A			; SET FLAGS
 	JP	Z,CIO_IDLE		; NOT READY, RETURN VIA IDLE PROCESSING
-	
+;	
 	RET
 ;
 #ELSE
@@ -391,7 +384,7 @@ Z2U_OST:
 	; START BY SELECTING I/O PAGE $FE
 	LD	L,$FE			; Z280 UART REGISTERS AT I/O PAGE $FE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; GET TRANSMIT STATUS
 	IN	A,(Z280_UARTXCTL)	; GET STATUS
@@ -399,7 +392,7 @@ Z2U_OST:
 	; RESTORE I/O PAGE TO $00
 	LD	L,$00			; NORMAL I/O REG IS $00
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; CHECK FOR CHAR AVAILABLE
 	AND	$01			; ISOLATE CHAR AVAILABLE BIT
@@ -439,7 +432,6 @@ Z2U_INITDEVX:
 ;
 Z2U_INITDEV1:
 	LD	(Z2U_NEWCFG),DE		; SAVE NEW CONFIG
-	
 ;
 ; HACK FOR TESTING!!!
 ;
@@ -457,8 +449,6 @@ Z2U_INITDEV1:
 	;LD	HL,52			; 24MHZ / 8 / 52 = 57692 BAUD (~57600)
 	JP	Z2U_INITDEV8		; SKIP AHEAD TO IMPLMENT IT
 #ENDIF
-;
-;
 ;
 	LD	A,D			; HIWORD OF CONFIG
 	AND	$1F			; ISOLATE BAUD RATE
@@ -480,7 +470,6 @@ Z2U_INITDEV1:
 	; Z280 UART CAN USE 16, 32, OR 64 AS BAUD RATE DIVISOR
 	; SET E TO IMPLEMENT WHAT WE CAN
 	LD	E,%11000000		; 8N0, DIV 1, NO C/T
-	;JR	Z2U_INITDEV2		; *DEBUG*
 	CP	4			; DIV 16 POSSIBLE?
 	JR	C,Z2U_INITDEV2		; IF NOT, SKIP AHEAD
 	LD	E,%11000010		; 8N0, DIV 16, NO C/T
@@ -508,10 +497,7 @@ Z2U_INITDEV2:
 	LD	H,0			; H MUST BE ZERO
 	LD	DE,1			; RATIO, SO NO CONSTANT
 	CALL	DECODE			; DECODE INTO DE:HL
-	;LD	HL,626			; *DEBUG*
 	JR	NZ,Z2U_INITFAIL		; HANDLE FAILURE
-	;CALL	PC_SPACE		; *DEBUG* 
-	;CALL	PRTHEXWORDHL            ; *DEBUG*
 ;
 	; SAVE CONFIG PERMANENTLY NOW
 	LD	DE,(Z2U_NEWCFG)		; GET NEW CONFIG BACK
@@ -523,7 +509,7 @@ Z2U_INITDEV8:
 	PUSH	HL			; SAVE HL
 	LD	L,$FE			; Z280 UART REGISTERS AT I/O PAGE $FE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 	POP	HL			; RESTORE HL
 ;
 	DEC	HL			; ADJUST FOR T/C
@@ -566,7 +552,7 @@ Z2U_INITDEV9:
 	; RESTORE I/O PAGE TO $00
 	LD	L,$00			; NORMAL I/O REG IS $00
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 #IF (INTMODE == 3)
 ;

Source/ver.inc

@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.47"
+#DEFINE BIOSVER	"3.1.1-pre.48"

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.47"
+	db	"3.1.1-pre.48"
 	endm