Improve IDE Device Detection

Per issue #343, some systems could initially detect a non-existent IDE device which would cause a long time-out.  This should resolve the issue.

.github/workflows/commit.yml

@@ -13,16 +13,18 @@ jobs:
     runs-on: ubuntu-latest
 
     steps:
-      - name: Make Slugs
-        uses: rlespinasse/github-slug-action@v4.4.1
-
       - name: Checkout
         uses: actions/checkout@v3.3.0
 
+      - name: Get Commit Ref
+        run: |
+          COMMIT_REF=$(git rev-parse --short $GITHUB_SHA)
+          echo "COMMIT_REF: $COMMIT_REF"
+          echo "COMMIT_REF=$COMMIT_REF" >>$GITHUB_ENV
+
       - name: Build
         run: |
           export TZ='America/Los_Angeles'
-          sudo apt-get install libncurses-dev
           sudo apt-get install srecord
           make dist
           rm -rf .git*
@@ -36,19 +38,22 @@ jobs:
       - name: Upload Artifact
         uses: actions/upload-artifact@v3.1.1
         with:
-          name: RomWBW-${{env.GITHUB_SHA_SHORT}}-Linux
+          name: RomWBW-${{env.COMMIT_REF}}-Linux
           path: .
 
   buildMacOS:
     runs-on: macOS-latest
 
     steps:
-      - name: Make Slugs
-        uses: rlespinasse/github-slug-action@v4.4.1
-
       - name: Checkout
         uses: actions/checkout@v3.3.0
 
+      - name: Get Commit Ref
+        run: |
+          COMMIT_REF=$(git rev-parse --short $GITHUB_SHA)
+          echo "COMMIT_REF: $COMMIT_REF"
+          echo "COMMIT_REF=$COMMIT_REF" >>$GITHUB_ENV
+
       - name: Build
         run: |
           export TZ='America/Los_Angeles'
@@ -65,5 +70,5 @@ jobs:
       - name: Upload Artifact
         uses: actions/upload-artifact@v3.1.1
         with:
-          name: RomWBW-${{env.GITHUB_SHA_SHORT}}-MacOS
-          path: .
+          name: RomWBW-${{env.COMMIT_REF}}-MacOS
+          path: .

.github/workflows/release.yml

@@ -14,15 +14,6 @@ jobs:
       - name: Checkout
         uses: actions/checkout@v3.3.0
 
-      - name: Create Package Label
-        run: |
-          echo GITHUB_REF: "$GITHUB_REF"
-          LABEL=`echo "$GITHUB_REF" | sed "s|^refs/tags/||"`
-          echo "PKGLBL=$LABEL" >> $GITHUB_ENV
-          echo PKGLBL: "$PKGLBL"
-          echo Upload URL: "${{github.event.release.upload_url}}"
-          echo GITHUB_TOKEN: "${{secrets.GITHUB_TOKEN}}"
-         
       - name: Build
         run: |
           export TZ='America/Los_Angeles'
@@ -33,22 +24,37 @@ jobs:
       
       - name: Create Package Archive
         run: |
-            zip -r RomWBW-${{env.PKGLBL}}-Package.zip .
+          zip -r RomWBW-${{github.ref_name}}-Package.zip .
+
+      - name: Set Title
+        run: |
+          echo "Tag: ${{github.ref_name}}"
+          if grep -q "dev" <<< "${{github.ref_name}}"; then
+            TITLE="RomWBW Development Snapshot"
+          elif grep -q "pre" <<< "${{github.ref_name}}"; then
+            TITLE="RomWBW Prerelease"
+          elif grep -q "rc" <<< "${{github.ref_name}}"; then
+            TITLE="RomWBW Release Candidate"
+          else
+            TITLE="RomWBW"
+          fi
+          echo "Title: $TITLE"
+          echo "TITLE=$TITLE" >>$GITHUB_ENV
 
       - name: Attach Package Archive
         uses: wwarthen/actions/packages/automatic-releases@built-packages
         with:
-          repo_token: "${{ secrets.GITHUB_TOKEN }}"
+          repo_token: "${{secrets.GITHUB_TOKEN}}"
           draft: true
           prerelease: true
-          title: "RomWBW Development SnapShot ${{env.PKGLBL}}"
+          title: "${{env.TITLE}} ${{github.ref_name}}"
           files: |
-            RomWBW-${{env.PKGLBL}}-Package.zip
+            RomWBW-${{github.ref_name}}-Package.zip
       
 #      - name: Upload Package Archive
 #        uses: AButler/upload-release-assets@v2.0.2
 #        with:
-#          repo-token: ${{ secrets.GITHUB_TOKEN }}
+#          repo-token: ${{secrets.github_token}}
 #          files: |
 #            RomWBW-${{env.PKGLBL}}-Package.zip
 
@@ -57,7 +63,7 @@ jobs:
 #        uses: docker://antonyurchenko/git-release:latest
 #        env:
 #          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
-#          RELEASE_NAME_PREFIX: "Development SnapShot Release "
+#          RELEASE_NAME_PREFIX: "${{env.TITLE}} "
 #          CHANGELOG_FILE: "none"
 #        with:
 #          args: |

Binary/DiskList.txt

@@ -1,173 +0,0 @@
-***********************************************************************
-***                                                                 ***
-***                          R o m W B W                            ***
-***                                                                 ***
-***                    Z80/Z180 System Software                     ***
-***                                                                 ***
-***********************************************************************
-
-This directory ("Binary") is part of the RomWBW System Software 
-distribution archive.  Refer to the ReadMe.txt file in this 
-directory for more information on the overall contents of the 
-directory.
-
-RomWBW includes a set of disk images that are ready to copy onto
-a floppy or hard/CF/SD disk.  You can use your modern computer
-(Windows/Linux/Mac) to copy the disk image file onto your disk
-media.  The disk media will then be ready to use in your RomWBW
-System.
-
-WARNING: The hdnew_*.img disk images are part of a new disk
-format that is a work in progress.  Do not use these disk
-images without knowing exactly what you are doing!  The
-hd_*.img disk images continue to be the images you should
-be using under normal circumstances.
-
-A description of the disk images is provided later in this file.
-For more information on the creatioin of these images including
-instructions for customizing them or creating your own, refer to
-the ReadMe.txt file in the Source\Images directory.
-
-Installing Images
------------------
-
-The following instructions apply to Windows computers.  Alternatively,
-you can use the "dd" command on Linux or Mac.
-
-First of all, a MAJOR WARNING!!!!  The tools described below are 
-quite capable of obliterating your running Windows system drive.  Use 
-with extreme caution and make sure you have backups.
-
-To install a floppy image on floppy media, you can use the tool 
-called RaWriteWin.  This tool is included in the Tools directory of 
-the distribution. This tool will write your floppy image (fd_xxx.img) 
-to a floppy disk using a raw block transfer.  The tool is GUI based 
-and it's operation is self explanatory.
-
-To install a hard disk image on a CF card or SD card, you must have 
-the appropriate media card slot on your computer. If you do, you can 
-use the tool called Win32DiskImager. This tool is also included in 
-the Tools directory of the distribution.  It will write your 
-hard disk image (hd_xxx.img) to the designated media card.  This tool 
-is also GUI based and self explanatory.
-
-The use of the SIMH emulator is outside of the scope of this document.  
-However, if you use SIMH, you will find that you can attach the hard 
-disk images to the emulator with lines such as the following in your 
-SIMH configuration file:
-
-  | attach hdsk0 hd_cpm22.img
-  | set hdsk0 format=HDSK
-  | set hdsk0 geom=T:2048/N:256/S:512
-  | set hdsk0 wrtenb
-  
-Making Disk Images Bootable
----------------------------
-
-The Operating System disk images below are ready to boot by the
-RomWBW Boot Loader.  However, if you update your RomWBW ROM, then
-you should also update the system tracks of your bootable disk
-images.  You would use SYSCOPY to do this.  SYSCOPY can also be
-used to make a disk bootable if it is not already bootable.
-
-You would use a command like the following to make drive C bootable:
-
-  | B>SYSCOPY C:=CPM.SYS
-
-The system file to use depends on the operating system you are trying
-to boot from the slice you are initializing with SYSCOPY:
-
-  CP/M 2.2 - cpm.sys
-  ZSDOS 1.1 - zsys.sys
-  CP/M 3 - cpmldr.sys
-  ZPM3 - cpmldr.sys
-  
-Slices
-------
-
-A RomWBW CP/M filesystem is fixed at 8MB.  This is because it is the 
-largest size filesystem supported by all common CP/M variants. Since 
-all modern hard disks (including SD Cards and CF Cards) are much 
-larger than 8MB, RomWBW supports the concept of "slices".  This 
-simply means that you can concatenate multiple CP/M filesystems (up 
-to 256 of them) on a single physical hard disk and RomWBW will allow 
-you to assign drive letters to them and treat them as multiple 
-independent CP/M drives.
-
-With the exception of the hd_combo image, each of the disk images
-includes a single CP/M file system (i.e., a single slice).  However,
-you can easily create a multi-slice disk image by merely concatenating 
-multiple images together.  For example, if you wanted to create a 2 
-slice disk image that has ZSDOS in the first slice and Wordstar in 
-the second slice, you could use the following command from a Windows 
-command prompt:
-
-  | C:\RomWBW\Binary>copy /b hd_zsdos.img + hd_ws.img hd_multi.img
-
-You can now write hd_multi.img onto your SD or CF Card and you will 
-have ZSDOS in the first slice and Wordstar in the second slice.
-
-The hd_combo disk image is an example of this.  It contains several
-slices in one image file.  The contents of this special disk image
-are described below.
-
-The concept of slices applies ONLY to hard disks.  Floppy disks are 
-not large enough to support multiple slices.
-
-Disk Image Contents
--------------------
-
-What follows is a brief description of the contents of the
-disk images automatically provided in the RomWBW distribution.
-Note that all of the OS images include the RomWBW custom
-support apps.
-
-cpm22 - DRI CP/M 2.2 (Bootable Floppy and Hard Disk)
-
-  Standard DRI CP/M 2.2 distribution files along with a few commonly
-  used utilities.
-
-zsdos - ZCPR1 + ZSDOS 1.1 (Bootable Floppy and Hard Disk)
-
-  Contains ZCPR1 and ZSDOS 1.1.  This is roughly equivalent to the
-  ROM boot contents, but provides a full set of the applications
-  and related files that would not all fit on the ROM drive.
-
-nzcom - NZCOM (Bootable Floppy and Hard Disk)
-
-  Standard NZCOM distribution.  Note that you will need to run the
-  NZCOM setup before this will run properly.  You will need
-  to refer to the NZCOM documentation.  
-
-cpm3 - DRI CP/M3 (Bootable Floppy and Hard Disk)
-
-  Standard DRI CP/M 3 adaptation for RomWBW that is ready to run.
-  It can be started by running CPMLDR.
-
-zpm3 - ZPM3 (Bootable Floppy and Hard Disk)
-
-  Simeon Cran's ZCPR 3 compatible OS for CP/M 3 adapted for RomWBW and 
-  ready to run.  It can be started by running CPMLDR (which seems 
-  wrong, but ZPMLDR is somewhat broken).
-
-ws4 - WordStar 4 (Floppy and Hard Disk)
-
-  Micropro Wordstar 4 full distribution.  This image is not bootable
-  and is intended to be added as an additional slice to an OS image.
-
-bp - BPBIOS (Hard Disk only)
-
-  Adaptation of BPBIOS for RomWBW.  This is NOT complete and NOT
-  useable in it's current state.
-
-combo - Multi-Boot Combination (Bootable Hard Disk)
-
-  A pre-created combo image that contains the following slices.  The
-  slices are identical to the individual images listed above.
-
-    Slice 0: cpm22 (bootable)
-    Slice 1: zsdos (bootable)
-    Slice 2: nzcom (bootable)
-    Slice 3: cpm3 (bootable)
-    Slice 4: zpm3 (bootable)
-    Slice 5: ws4 (not bootable)

Binary/ReadMe.txt

@@ -49,7 +49,7 @@ The files with a ".upd" extension are binary images identical to the
 .rom files, but they only have the first 128K bytes.  The first 128K
 is the system image without the ROM disk contents.  These files can be
 used to update the system image without modifying the ROM disk
-contents.  Refer to the Getting Started document for more information.
+contents.  Refer to the RomWBW User Guide for more information.
 
 ROM Executable Images (<plt>_<cfg>.com)
 ---------------------------------------

Doc/ChangeLog.txt

@@ -1,3 +1,23 @@
+Version 3.3
+-----------
+- WBW: Support Front Panel switches
+- A?C: Preliminary support for Z80-Retro
+- A?C: Support for SD PIO
+- A?C: Support for Z80-Retro SD interface
+- WBW: Support per-drive floppy configuration
+
+Version 3.2.1
+-------------
+- M?P: Fixed Zeta 2 FDD and CPUSPD config settings
+- WBW: Fixed SURVEY.COM (again)
+- DDW: Updates to DOS/65 binaries in disk images
+- PMS: Updates to VGMPLAY including support for YM2151
+- WBW: Fix for quark delay adjustment being trashed
+
+Version 3.2
+-----------
+- WBW: Version bump for release
+
 Version 3.1.1
 -------------
 - WBW: Version bumped due to pervasive changes

Doc/ReadMe.txt

@@ -10,6 +10,26 @@ This directory ("Doc") is part of the RomWBW System Software
 distribution archive.  It contains documentation for components of 
 the system.
 
+ChangeLog.txt
+-------------
+
+Log of changes in RomWBW by version.
+
+
+RomWBW User Guide ("RomWBW User Guide.pdf")
+RomWBW System Guide ("RomWBW System Guide.pdf")
+RomWBW Applications ("RomWBW Applications.pdf")
+RomWBW ROM Applications ("RomWBW ROM Applications.pdf")
+RomWBW Disk Catalog ("RomWBW Disk Catalog.pdf")
+RomWBW Errata ("RomWBW Errata.pdf")
+-------------------------------------------------------
+
+Documentation set for RomWBW.  The primary document is the
+User Guide.  The System Guide explains internal system operation
+and has a reference for the HBIOS API.  Use of included tools
+and utilities are detailed in the  Applications and
+ROM Applications documents.
+
 
 CPM Manual ("CPM Manual.pdf")
 -----------------------------
@@ -43,12 +63,6 @@ The operational manual for John Coffman's hard disk partitioning
 program.  This program is included in RomWBW as FDISK80.
 
 
-Floppy Disk Utility Documentation ("FDU.tst")
----------------------------------------------
-
-Operational documentation for the RomWBW FDU application.
-
-
 Hard Disk Anatomy ("Hard Disk Anatomy.pdf")
 -------------------------------------------
 
@@ -61,17 +75,47 @@ NZCOM User's Manual ("NZCOM Users Manual.pdf")
 NZCOM operating system operation manual.
 
 
-RomWBW Architecture ("RomWBW Architecture.pdf")
------------------------------------------------
+ZCPR Manual ("ZCPR Manual.pdf")
+-------------------------------
 
-Document describing the architecture of the RomWBW HBIOS.  It 
-includes reference information for the HBIOS calls.
+ZCPR is the command proccessor portion of Z-System.  This is the 
+manual for ZCPR 1.x as included in RomWBW.  The installation 
+instructions can be ignored since that work has already been 
+completed as part of the RomWBW distribution.
 
-ROM Applications ("ROM Applications.pdf")
------------------------------------------
+ZCPR D&J Manual ("ZCPR-DJ.doc")
+-------------------------------
 
-Breif instructions for the ROM based applications included in
-in the boot ROM.
+ZCPR D&J User Manual.  This manual supplements the ZCPR Manual.
+
+
+ZSDOS Manual ("ZSDOS Manual.pdf")
+---------------------------------
+
+ZSDOS is the DOS portion of Z-System.  This is the manual for ZSDOS 
+1.x as included in RomWBW.  The installation instructions can be 
+ignored since that work has already been completed as part of the 
+RomWBW distribution.
+
+Microsoft Basic-80 Reference Manual v5.0 (Microsoft Basic-80 Reference Manual v5.0.pdf)
+---------------------------------------------------------------------------------------
+
+Official manual for Microsoft BASIC as included in RomWBW.
+
+
+QP/M 2.7 Installation Guide and Supplements ("qpm27.pdf")
+QP/M 2.7 Interface Guide ("qdos27.pdf")
+QP/M 2.7 Features and Facilities ("qcp27.pdf")
+--------------------------------------------
+
+Official documentation set for QP/M 2.7 from original QP/M distribution.
+
+
+SIO+CTC Baud Rate Options (SIO+CTC Baud Rate Options.pdf)
+---------------------------------------------------------
+
+Documents possible baud rates available based on different baud
+clock rates for Zilog SIO using CTC for baud rate clock generation.
 
 
 Z180 ASCI Baud Rate Options ("Z180 ASCI Baud Rate Options.pdf")
@@ -83,19 +127,10 @@ clock rate.  This document provides a list of the possible
 baud rates for typical CPU clock rates.
 
 
-ZCPR Manual ("ZCPR Manual.pdf")
--------------------------------
+UCSD p-System Users Manual ("UCSD p-System Users Manual.pdf")
+-------------------------------------------------------------
 
-ZCPR is the command proccessor portion of Z-System.  This is the 
-manual for ZCPR 1.x as included in RomWBW.  The installation 
-instructions can be ignored since that work has already been 
-completed as part of the RomWBW distribution.
+Official user manual for p-System operating system included with
+RomWBW.
 
-
-ZSDOS Manual ("ZSDOS Manual.pdf")
----------------------------------
-
-ZSDOS is the DOS portion of Z-System.  This is the manual fo ZSDOS 
-1.x as included in RomWBW.  The installation instructions can be 
-ignored since that work has already been completed as part of the 
-RomWBW distribution.
+--WBW 5:18 PM 3/16/2023

Doc/Testing Notes.txt

@@ -40,7 +40,7 @@ N8-2312 (X)
 - Test FDU app
 - Test TMS driver (video & kbd)
 
-N8-2511 ( )
+N8-2511 (X)
 -------
 - Test ASCI driver
 - Test SD driver (Juha mode)
@@ -139,27 +139,6 @@ GENERAL (X)
 - ASSIGN app
 - MODE app
 - SYSCOPY app
-- OSLDR app
 - FDU app
 - FDISK80 app
 - TUNE app
-
-RESULTS
--------
-- Missing HBIOS startup banner (X)
-- PANIC while printing Serial device inventory (X)
-- Unexpected interrupt signals not handled well (X)
-- Fix IT_??? usage (X)
-- Fix HB_DI/HB_EI in PEEK/POKE/BNKCPY (X)
-- Fix SIMH timer interrupt setup (X)
-- Move DI/EI in PEEK/POKE/BNKCPY to API layer? (X)
-- RETI vs. JP in page zero when INTMODE = 0 (X)
-- Check interrupt stack space (X)
-- If an early INT fires, we return with INTs enabled (not good) (X)
-- PPPCON init should display ANSI 80x25 or similar (X)
-- Add INT MODE X message to early boot messages (X)
-- OSLDR fails when LDDS is loaded (X)
-- Add "!!!" to force assembly error as needed ( )
-- TIMER app should check for HBIOS active (X)
-- Halt system after bad interrupt??? ( )
-- Adapt and bundle PLAYER.COM (X)

ReadMe.md

@@ -1,9 +1,9 @@
 
 
 **RomWBW ReadMe** \
-Version 3.2 \
+Version 3.3 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-05 Mar 2023
+16 Apr 2023
 
 # Overview
 
@@ -128,8 +128,8 @@ contributions. The list below is probably missing many names – please
 let me know if I missed you!
 
 - Andrew Lynch started it all when he created the N8VEM Z80 SBC which
-  became the first platform RomWBW supported. Some of his code can still
-  be found in RomWBW.
+  became the first platform RomWBW supported. Some of his original code
+  can still be found in RomWBW.
 
 - Dan Werner wrote much of the code from which RomWBW was originally
   derived and he has always been a great source of knowledge and advice.
@@ -140,23 +140,30 @@ let me know if I missed you!
   due to internal changes within RomWBW. As of RomWBW 2.6, these
   applications are no longer provided.
 
+- Sergey Kiselev created several hardware platforms for RomWBW including
+  the very popular Zeta.
+
 - David Giles created support for the Z180 CSIO which is now included SD
   Card driver.
 
+- Phil Summers contributed the Forth and BASIC adaptations in ROM, the
+  AY-3-8910 sound driver, DMA support, and a long list of general code
+  and documentation enhancements.
+
 - Ed Brindley contributed some of the code that supports the RCBus
   platform.
 
-- Phil Summers contributed the Forth and BASIC adaptations in ROM, the
-  AY-3-8910 sound driver as well as a long list of general code
-  enhancements.
-
 - Spencer Owen created the RC2014 series of hobbyist kit computers which
-  has exponentially increased RomWBW usage.
+  has exponentially increased RomWBW usage. Some of his kits include
+  RomWBW.
 
 - Stephen Cousins has likewise created a series of hobbyist kit
   computers at Small Computer Central and is distributing RomWBW with
   many of them.
 
+- Alan Cox has contributed some driver code and has provided a great
+  deal of advice.
+
 - The CP/NET client files were developed by Douglas Miller.
 
 - Phillip Stevens contributed support for FreeRTOS.
@@ -197,14 +204,15 @@ Portions of RomWBW were created by, contributed by, or derived from the
 work of others. It is believed that these works are being used in
 accordance with the intentions and/or licensing of their creators.
 
-If anyone feels their work is being used outside of it’s intended
+If anyone feels their work is being used outside of its intended
 licensing, please notify:
 
-> Wayne Warthen wwarthen@gmail.com
+> Wayne Warthen  
+> <wwarthen@gmail.com>
 
 RomWBW is an aggregate work. It is composed of many individual,
 standalone programs that are distributed as a whole to function as a
-cohesive system. Each program may have it’s own licensing which may be
+cohesive system. Each program may have its own licensing which may be
 different from other programs within the aggregate.
 
 In some cases, a single program (e.g., CP/M Operating System) is

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-05 Mar 2023
+16 Apr 2023
 
 
 
@@ -129,8 +129,8 @@ contributions. The list below is probably missing many names – please
 let me know if I missed you!
 
 -   Andrew Lynch started it all when he created the N8VEM Z80 SBC which
-    became the first platform RomWBW supported. Some of his code can
-    still be found in RomWBW.
+    became the first platform RomWBW supported. Some of his original
+    code can still be found in RomWBW.
 
 -   Dan Werner wrote much of the code from which RomWBW was originally
     derived and he has always been a great source of knowledge and
@@ -142,23 +142,30 @@ let me know if I missed you!
     due to internal changes within RomWBW. As of RomWBW 2.6, these
     applications are no longer provided.
 
+-   Sergey Kiselev created several hardware platforms for RomWBW
+    including the very popular Zeta.
+
 -   David Giles created support for the Z180 CSIO which is now included
     SD Card driver.
 
+-   Phil Summers contributed the Forth and BASIC adaptations in ROM, the
+    AY-3-8910 sound driver, DMA support, and a long list of general code
+    and documentation enhancements.
+
 -   Ed Brindley contributed some of the code that supports the RCBus
     platform.
 
--   Phil Summers contributed the Forth and BASIC adaptations in ROM, the
-    AY-3-8910 sound driver as well as a long list of general code
-    enhancements.
-
 -   Spencer Owen created the RC2014 series of hobbyist kit computers
-    which has exponentially increased RomWBW usage.
+    which has exponentially increased RomWBW usage. Some of his kits
+    include RomWBW.
 
 -   Stephen Cousins has likewise created a series of hobbyist kit
     computers at Small Computer Central and is distributing RomWBW with
     many of them.
 
+-   Alan Cox has contributed some driver code and has provided a great
+    deal of advice.
+
 -   The CP/NET client files were developed by Douglas Miller.
 
 -   Phillip Stevens contributed support for FreeRTOS.
@@ -202,14 +209,15 @@ Portions of RomWBW were created by, contributed by, or derived from the
 work of others. It is believed that these works are being used in
 accordance with the intentions and/or licensing of their creators.
 
-If anyone feels their work is being used outside of it’s intended
+If anyone feels their work is being used outside of its intended
 licensing, please notify:
 
-  Wayne Warthen wwarthen@gmail.com
+  Wayne Warthen
+  wwarthen@gmail.com
 
 RomWBW is an aggregate work. It is composed of many individual,
 standalone programs that are distributed as a whole to function as a
-cohesive system. Each program may have it’s own licensing which may be
+cohesive system. Each program may have its own licensing which may be
 different from other programs within the aggregate.
 
 In some cases, a single program (e.g., CP/M Operating System) is

Source/Apps/Survey/survey.mac

@@ -15,6 +15,13 @@
 ;
 ;VERSION LIST - Most recent version first.
 ;
+;21/Mar/23 - Previous hack was worthless because it broke
+;            the memory survey.  Rehacked to use HBIOS to
+;            detect if N8VEM SBC MPCL memory management is
+;            in use and bypass MPCL ports if so.  HBIOS check
+;            should allow use in non-RomWBW systems again.
+;            Wayne Warthen
+;
 ;10/Feb/23 - Total hack to avoid crash on ECB SBC
 ;            RomWBW now required by this version
 ;            Wayne Warthen
@@ -240,20 +247,6 @@ TABS	EQU	9		; Tab columns
 ;
 	;ORG	100H
 ;
-;
-;
-	.Z80
-	LD	HL,IMGORG
-	LD	DE,START
-	LD	BC,IMGEND-IMGORG
-	LDIR
-	JP	START
-	.8080
-;
-IMGORG:
-;
-	.PHASE	8000H
-;
 START:
 	LXI	H,0			; Save stack pointer
 	DAD	SP
@@ -261,9 +254,38 @@ START:
 	LXI	SP,FINIS+64
 	CALL	TYPE			; Type initial CRLF
 	DW	CRLF,CRLF
-	DB	TAB,'*** RomWBW System Survey (Feb 2023) ***'
+	DB	TAB,'*** RomWBW System Survey (Mar 2023) ***'
 	DW	CRLF,CRLFE
+;
+; Are we running an N8VEM SBC w/ MPCL on RomWBW???
+;
+	.Z80
+	XOR	A		; assume not
+	LD	(ISMPCL),A	; save it
 
+	; Check for RomWBW (HBIOS)
+	LD	HL,(0FFFEH)	; HL := HBIOS ident location
+	LD	A,'W'		; First byte of ident
+	CP	(HL)		; Compare
+	JR	NZ,NOTMPCL	; Not HBIOS
+	INC	HL		; Next byte of ident
+	LD	A,NOT 'W'	; Second byte of ident
+	CP	(HL)		; Compare
+	JR	NZ,NOTMPCL	; Not HBIOS
+;
+	LD	B,0F1H		; HBIOS: VER function
+	LD	C,0		; required reserved value
+	RST	08		; DE := version, L := platform id
+	LD	A,L		; Platform ID
+	CP	01H		; SBC?
+	JR	NZ,NOTMPCL	; Not SBC
+	LD	A,0FFH		; Flag
+	LD	(ISMPCL),A	; Set flag
+;
+	.8080
+;
+NOTMPCL:
+;
 ;DISK SURVEY
 	LXI	H,8			; Init drive counter
 	MVI	C,24			; Get login vector
@@ -445,20 +467,19 @@ MSURV:
 	ENDM
 	DB	'|'
 	DW	CRLF
-	db	' '			; dmb 31-May-82
-	DB	'T'+EOL
+	DB	'TT','T'+EOL
 	LXI	H,RAM
-	MVI	M,LOW 1023		; Init RAM counter
+	MVI	M,LOW 2047		; Init RAM counter
 	INX	H
-	MVI	M,HIGH 1023
+	MVI	M,HIGH 2047
 	MVI	B,4			; Clear ROM, EMP
 CLREG:
 	INX	H
 	MVI	M,0
 	DCR	B
 	JNZ	CLREG
-	LXI	H,1024			; Init memory pointer
-	MVI	C,63			; K to be checked
+	LXI	H,2048			; Init memory pointer
+	MVI	C,62			; K to be checked
 
 ;Start of analysis loop
 BEGANA:
@@ -492,7 +513,7 @@ NOTEM:
 	INXI	ROM
 NEXT:
 	INX	H			; Index next byte
-	DCX	D			; Decrement K counter
+	DCX	D			; DEC DE; Decrement K counter
 	XRA	A
 	ORA	D
 	ORA	E
@@ -545,8 +566,19 @@ NEXTK:
 ; contents of first page
 	call	type
 	db	'BIOS at',' '+eol
-	hexout	bios+2
-	hexout	bios+1
+	;hexout	bios+2
+	;hexout	bios+1
+	.z80
+	ld	hl,(bios+1)
+	ld	de,-3
+	add	hl,de
+	push	hl
+	ld	a,h
+	call	hexprn
+	pop	hl
+	ld	a,l
+	call	hexprn
+	.8080
 	call	type
 	db	tab,'iobyte',' '+eol
 	hexout	bios+3
@@ -555,8 +587,19 @@ NEXTK:
 	hexout	bios+4
 	call	type
 	db	tab,'BDOS at',' '+eol
-	hexout	bdos+2
-	hexout	bdos+1
+	;hexout	bdos+2
+	;hexout	bdos+1
+	.z80
+	ld	hl,(bdos+1)
+	ld	de,-6
+	add	hl,de
+	push	hl
+	ld	a,h
+	call	hexprn
+	pop	hl
+	ld	a,l
+	call	hexprn
+	.8080
 	call	type
 	dw	crlf,crlfe
 ;
@@ -572,6 +615,8 @@ NEXTK:
 	CALL	TYPE
 	DB	' Bytes ROM',TAB,TAB+EOL
 	LHLD	BDOS+1
+	LXI	D,-6
+	DAD	D
 	CALL	BINDEC
 	CALL	TYPE
 	DB	' Bytes in TPA'
@@ -607,9 +652,6 @@ PDLY:
 	JNZ	PDLY
 ;
 	.Z80
-	; record the active bank
-	ld	a,(0ffe0h)		; get current hbios bank id
-	ld	(BANK),a		; and save it
 	; Check for Z180 CPU
 	xor	a			; assume Z80
 	ld	(IS180),a		; save it
@@ -635,6 +677,17 @@ PORTLP:
 	ENDIF
 ;
 	.Z80
+;
+	ld	a,(ISMPCL)		; MPCL?
+	or	a			; set flags
+	jr	z,PCONT			; if not, skip ahead
+	ld	a,d			; get port to test
+	and	0F8H			; range of 8 ports
+	cp	078H			; starting at 78H
+	jr	z,ISPORT		; if in range, assume real port
+;
+PCONT:
+
 	di				; interrupts off
 	ld	a,(IS180)		; Z180?
 	or	a
@@ -679,11 +732,6 @@ pnum1b	equ	$-1
 	push	af
 ;
 rdz:
-	; Make sure correct bank is still selected!
-	push	af
-	ld	a,(BANK)
-	call	0FFF3H
-	pop	af
 ;
 	ei				; interrupts back on now
 ;
@@ -818,13 +866,9 @@ RAMF:	DS	1			; RAM good flag
 EMPF:	DS	1			; Empty so far flag
 BLKSHF:	DS	1			; block shift factor
 MAXALL:	DS	2			; maximum block number
-BANK:	DS	1			; saved HBIOS bank id
 IS180:	DS	1			; non-zero for Z180 CPU
+ISMPCL:	DS	1			; non-zero for N8VEM SBC MPCL
 FINIS	EQU	$			; End of program
-;
-	.DEPHASE
-;
-IMGEND:
 ;
 	END
 

Source/Apps/Test/DMAmon/dmamon.asm

@@ -39,12 +39,36 @@ INTENABLE	.EQU	TRUE		; ENABLE INT TESTING
 INTIDX		.EQU	1		; INT VECTOR INDEX
 ;
 ;==================================================================================================
-; DMA MODE BYTES
+; DMA MODE BYTES - I/O ROUTINES CLEAR b3 AND ONLY PROGRAM LOW ADDRESS
 ;==================================================================================================
 ;
-DMA_CONTINUOUS			.equ 	%10111101	; + Pulse
-DMA_BYTE			.equ 	%10011101	; + Pulse
-DMA_BURST 			.equ	%11011101	; + Pulse
+DMA_BYTE			.equ 	%10011101	; b7b1b0 = Register		= 1xxxxx01	= Program R4
+							; b6b5	 = Transfer Mode	= x00xxxxx	= Byte transfer mode
+							; b2	 = start address (low)	= xxxxx1xx	= low address follows (1 byte)
+							; b3	 = start address (high) = xxxx1xxx	= high address follows (1 byte)
+							; b4	 = int control byte	= xxx1xxxx	= interrupt, pulse or vector byte follow
+;
+DMA_CONTINUOUS			.equ 	%10111101	; b7b1b0 = Register		= 1xxxxx01	= Program R4
+							; b6b5	 = Transfer Mode	= x01xxxxx	= Continuous transfer mode (default)
+							; b2	 = start address (low)	= xxxxx1xx	= low address follows (1 byte)
+							; b3	 = start address (high) = xxxx1xxx	= high address follows (1 byte)
+							; b4	 = int control byte	= xxx1xxxx	= interrupt, pulse or vector byte follow
+;
+DMA_BURST 			.equ	%11011101	; b7b1b0 = Register		= 1xxxxx01	= Program R4
+							; b6b5	 = Transfer Mode	= x10xxxxx	= Burst transfer mode
+							; b2	 = start address (low)	= xxxxx1xx	= low address follows (1 byte)
+							; b3	 = start address (high) = xxxx1xxx	= high address follows (1 byte)
+							; b4	 = int control byte	= xxx1xxxx	= interrupt, pulse or vector byte follow
+;
+DMA_ICBYTE			.equ	%00001100	; b7	 = Interrupt Cont. Byte	= 0xxxxxxx	= Interrupt Control Byte identifier
+							; b6	 = Interrupt on RDY	= x0xxxxxx	= Do not interrupt on RDY
+							; b5	 = Status affects vector= xx0xxxxx	= Status does not affect vector
+							; b4	 = Interrupt vector byte= xxx0xxxx	= No interrupt vector byte will follow
+							; b3	 = Pulse control byte	= xxxx1xxx	= A pulse control byte will follow
+							; b2	 = Pulse generation	= xxxxx100	= A pulse will be generated
+							; b1	 = Interrupt @ block end= xxxxxx0x	= No interrupt at block end
+							; b0	 = Interrupt on match	= xxxxxxx0	= No interrupt on match
+;
 DMA_LOAD			.equ	$cf 		; %11001111
 DMA_ENABLE			.equ	$87		; %10000111
 DMA_FORCE_READY 		.equ 	$b3
@@ -64,6 +88,7 @@ DMA_REINIT_STATUS_BYTE		.equ	$8b
 ;
 DMA_RDY				.EQU	%00001000
 DMA_FORCE			.EQU	0
+DMA_XMODE			.equ	1		; Byte = 0, Continuous = 1, Burst = 2
 ;
 ;==================================================================================================
 ; ROMWBW HBIOS DEFINITIONS
@@ -116,6 +141,8 @@ MENULP:	CALL	DISPM			; DISPLAY MENU
 ;
 MENULP1:
 	CALL	NEWLINE
+	CP	'C'
+	JP	Z,DMACFG_C		; CONFIGURE XFER MODE
 	CP	'D'
 	JP	Z,DMATST_D		; DUMP REGISTERS
 	CP	'I'
@@ -141,12 +168,33 @@ MENULP1:
 	JP	Z,DMATST_Y		; TOGGLE READY
 #ENDIF
 	cp	'S'
-	call	z,DMACFG_S		; SET PORT
+	jp	z,DMACFG_S		; SET PORT
+	cp	'V'
+	jp	z,DMACFG_V		; TOGGLE VERBOSE
 	CP	'X'
 	JP	Z,DMABYE		; EXIT
 ;
 	JR	MENULP
 ;
+DMABYE:
+#IF (INTENABLE)
+	; Deinstall interrupt vector
+	ld	hl,(orgvec)		; original vector
+	ld	b,bf_sysint
+	ld	c,bf_sysintset		; set new vector
+	ld	e,INTIDX		; vector idx
+	di
+	rst	08			; do it
+	ei				; interrupts back on
+#ENDIF
+;
+	LD	SP,(SAVSTK)		; RESTORE CP/M STACK
+	RET
+;
+;==================================================================================================
+; CONFIGURE PORT
+;==================================================================================================
+;
 DMACFG_S:
 	call	PRTSTRD
 	.db	"\n\rSet port address\n\rPort:$"
@@ -158,21 +206,6 @@ DMACFG_S:
 	ld	(hl),a
 	jp	MENULP
 ;
-DMABYE:
-#IF (INTENABLE)
-	; Deinstall interrupt vector
-	ld	hl,(orgvec)	; original vector
-	ld	b,bf_sysint
-	ld	c,bf_sysintset	; set new vector
-	ld	e,INTIDX	; vector idx
-	di
-	rst	08		; do it
-	ei			; interrupts back on
-#ENDIF
-;
-	LD	SP,(SAVSTK)		; RESTORE CP/M STACK
-	RET
-;
 DMATST_I:
 	call	PRTSTRD
 	.db	"\n\rStart Initialization\n\r$"
@@ -230,6 +263,16 @@ DMATST_R:
 	.db	"\n\rPerforming Reset\n\r$"
 ;	CALL	
 	JP	MENULP
+
+DMACFG_C:
+	CALL	DMA_XferM
+	call	PRTSTRD
+	.db	"\n\rTransfer mode change to: $"
+	LD	a,(dmaxfer)
+	LD	DE,DMA_XFRMODE
+	CALL	PRTIDXDEA
+	CALL	NEWLINE
+	JP	MENULP
 ;
 ;==================================================================================================
 ; DISPLAY MENU
@@ -274,7 +317,6 @@ DISPM_INT:
 #ENDIF
 	call	PRTSTRD			; DISPLAY SPEED
 	.db	"\n\rCPU at $"
-
 	LD	B,bf_sysget
 	LD	C,bf_sysgetcpuspd	; GET CURRENT 
 	RST	08			; SPEED SETTING
@@ -282,9 +324,14 @@ DISPM_INT:
 	LD	A,L
 	JR	Z,SPDDISP
 	LD	A,3
-;
 SPDDISP:LD	DE,DMA_SPD_STR
 	CALL	PRTIDXDEA
+;
+	call	PRTSTRD
+	.db	"\n\rTransfer Mode: $"	; DIPLAY TRANSFER
+	LD	a,(dmaxfer)		; MODE
+	LD	DE,DMA_XFRMODE
+	CALL	PRTIDXDEA
 	CALL	NEWLINE
 ;
 	LD	HL,MENU_OPT		; DISPLAY
@@ -309,13 +356,16 @@ DMA_INIT:
 	LD	A,DMA_FORCE
 	out	(c),a			; force ready off
 #ENDIF
-;
 ;
 	call	DMAProbe		; do we have a dma?
 	jr	nz,DMA_NOTFOUND
 ;
 	call	PRTSTRD
 	.db	" DMA Found\n\r$"
+;
+	ld	hl,DMAInitMode		; setup the 
+	call	SETXFER			; transfer mode
+	set	3,(hl)			; upper and lower address
 ;
 	ld	hl,DMACode		; program the
 	ld	b,DMACode_Len		; dma command
@@ -338,6 +388,27 @@ DMA_NOTFOUND:
 ;
 DMA_FAIL_FLAG:
 	.db	0
+;
+DMACode		;.db	DMA_DISABLE	; R6-Command Disable DMA
+		.db	%01111101 	; R0-Transfer mode, A -> B, start address, block length follow
+		.dw	0		; R0-Port A, Start address
+		.dw	0 		; R0-Block length
+		.db	%00010100	; R1-No timing bytes follow, address increments, is memory
+		.db	%00010000 	; R2-No timing bytes follow, address increments, is memory
+		.db	%10000000 	; R3-DMA, interrupt, stop on match disabled
+DMAInitMode:	.db	DMA_CONTINUOUS	; R4-Transfer mode, destination address, interrupt and control byte follow
+		.dw	0 		; R4-Port B, Destination address
+		.db	DMA_ICBYTE	; R4-Pulse byte follows, Pulse generated
+		.db	0		; R4-Pulse offset
+		.db	%10010010+DMA_RDY; R5-Stop on end of block, ce/wait multiplexed, READY active config
+		.db	DMA_LOAD 	; R6-Command Load
+;		.db	DMA_FORCE_READY	; R6-Command Force ready
+;		.db	DMA_ENABLE 	; R6-Command Enable DMA
+DMACode_Len 	.equ	$-DMACode
+;
+;==================================================================================================
+; STRINGS
+;==================================================================================================
 ;	
 DMA_DEV_STR:
 	.TEXT	"NONE$"
@@ -354,8 +425,14 @@ DMA_SPD_STR:
 	.TEXT	"double speed.$"
 	.TEXT	"unknown speed.$"
 ;
+DMA_XFRMODE:
+	.TEXT	"Byte.$"
+	.TEXT	"Continuous.$"
+	.TEXT	"Burst.$"
+;
 MENU_OPT:
 	.TEXT	"\n\r"
+	.TEXT	"C) Change transfer mode\n\r"
 	.TEXT	"D) Dump DMA registers\n\r"
 	.TEXT	"I) Initialize DMA\n\r"
 	.TEXT	"T) Toggle Interrupt Usage\n\r"
@@ -368,11 +445,36 @@ MENU_OPT:
 	.TEXT	"Y) Test Ready Bit\n\r"
 #ENDIF
 	.TEXT	"S) Set DMA port\n\r"
+	.TEXT	"L) Set Latch port\n\r"
+	.TEXT	"V) Verbose status toggle\n\r"
 	.TEXT	"X) Exit\n\r"
 
 	.TEXT	">$"
 ;
 ;==================================================================================================
+; TOGGLE TRANSFER MODE
+;==================================================================================================
+;
+DMA_XferM:				; Set next transfer mode
+	ld	a,(dmaxfer)
+	inc	a
+	cp	3
+	jr	nz,NextX
+	ld	a,0
+NextX:	ld	(dmaxfer),a
+	ret
+;
+;==================================================================================================
+; TOGGLE VERBOSE MODE
+;==================================================================================================
+;
+DMACFG_V:
+	ld	a,(dmavbs)
+	cpl
+	ld	(dmavbs),a
+	jp	MENULP
+;
+;==================================================================================================
 ; OUTPUT A BUFFER OF TEXT TO AN IOPORT
 ;==================================================================================================
 ;
@@ -393,19 +495,14 @@ IOLoop:	push	bc
 	ld	bc,16
 ;
 	call	DMAOTIR
-;
-	call	PRTSTRD
-	.db	" Return Status: $"
-	call	PRTHEXBYTE
 ;
 	pop	bc
 	djnz	IOLoop
 	call	NEWLINE
-
 	ret
 ;
 ;==================================================================================================
-; PULSE PORT (COMMON ROUTINE WITH A CONTAINING ASCII PORT OFFSET)
+; PULSE PORT (COMMON ROUTINE WHERE A CONTAINS THE ASCII PORT OFFSET)
 ;==================================================================================================
 ;
 DMA_Port01:
@@ -480,7 +577,6 @@ portlp2:push	bc
 ;==================================================================================================
 ;
 DMAMemMove:
-;
 	LD	HL,$8000	; PREFILL DESTINATION WITH $55
 	LD	A,$55
 	LD	(HL),A
@@ -513,10 +609,6 @@ DMAMemMove2:
 ;	LD	A,$00		; BAD
 ;	LD	(HL),A		; SEED
 ;
-	call	PRTSTRD
-	.db	"Return Status: $"
-	call	PRTHEXBYTE
-
 	LD	A,$AA		; CHECK COPY SUCCESSFULL
 	LD	HL,$8000
 	LD	BC,4096
@@ -616,23 +708,6 @@ DMAProbe:
 	cpl
 	ret
 ;
-DMACode		;.db	DMA_DISABLE	; R6-Command Disable DMA
-		.db	%01111101 	; R0-Transfer mode, A -> B, start address, block length follow
-		.dw	0		; R0-Port A, Start address
-		.dw	0 		; R0-Block length
-		.db	%00010100	; R1-No timing bytes follow, address increments, is memory
-		.db	%00010000 	; R2-No timing bytes follow, address increments, is memory
-		.db	%10000000 	; R3-DMA, interrupt, stop on match disabled
-		.db	DMA_CONTINUOUS	; R4-Continuous mode, destination address, interrupt and control byte follow
-		.dw	0 		; R4-Port B, Destination address
-		.db	%00001100	; R4-Pulse byte follows, Pulse generated
-		.db	0		; R4-Pulse offset
-		.db	%10010010+DMA_RDY; R5-Stop on end of block, ce/wait multiplexed, READY active config
-		.db	DMA_LOAD 	; R6-Command Load
-;		.db	DMA_FORCE_READY	; R6-Command Force ready
-;		.db	DMA_ENABLE 	; R6-Command Enable DMA
-DMACode_Len 	.equ	$-DMACode
-;
 ;==================================================================================================
 ; DMA COPY BLOCK CODE -  ASSUMES DMA PREINITIALIZED
 ;==================================================================================================
@@ -641,6 +716,10 @@ DMALDIR:
 	ld	(DMASource),hl		; populate the dma
 	ld	(DMADest),de		; register template
 	ld	(DMALength),bc
+;
+	ld	hl,DMACopyMode
+	call	SETXFER
+	set	3,(hl)			; upper and lower address
 ;
 	ld	hl,DMACopy		; program the
 	ld	b,DMACopy_Len		; dma command
@@ -651,11 +730,7 @@ DMALDIR:
 	otir				; load and execute dma
 	ei
 ;
-	ld	a,DMA_READ_STATUS_BYTE	; check status
-	out	(c),a			; of transfer
-	in	a,(c)			; set non-zero
-;	and	%00111011		; if failed
-;	sub	%00011011
+	call	DMASTATUS
 	ret
 ;
 DMACopy 	;.db	DMA_DISABLE	; R6-Command Disable DMA
@@ -665,9 +740,9 @@ DMALength	.dw	0 		; R0-Block length
 		.db	%00010100	; R1-No timing bytes follow, address increments, is memory
 		.db	%00010000 	; R2-No timing bytes follow, address increments, is memory
 		.db	%10000000 	; R3-DMA, interrupt, stop on match disabled
-		.db	DMA_CONTINUOUS	; R4-Continuous mode, destination address, interrupt and control byte follow
+DMACopyMode:	.db	DMA_CONTINUOUS	; R4-Transfer mode. Destination address, interrupt and control byte follow
 DMADest		.dw	0 		; R4-Port B, Destination address
-		.db	%00001100	; R4-Pulse byte follows, Pulse generated
+		.db	DMA_ICBYTE	; R4-Pulse byte follows, Pulse generated
 		.db	0		; R4-Pulse offset
 ;		.db	%10010010+DMA_RDY;R5-Stop on end of block, ce/wait multiplexed, READY active config
 		.db	DMA_LOAD 	; R6-Command Load
@@ -687,6 +762,10 @@ DMALDIRINT:
 	ld	(DMASourceInt),hl	; populate the dma
 	ld	(DMADestInt),de		; register template
 	ld	(DMALengthInt),bc
+;
+	ld	hl,DMAICopyMode
+	call	SETXFER
+	set	3,(hl)			; upper and lower address
 ;
 	ld	hl,DMACopyInt		; program the
 	ld	b,DMACopyInt_Len	; dma command
@@ -697,17 +776,7 @@ DMALDIRINT:
 	otir				; load and execute dma
 	ei
 ;
-	ld	a,DMA_READ_STATUS_BYTE	; check status
-	out	(c),a		; of transfer
-	in	a,(c)	
-
-	call	PRTSTRD
-	.db	"Return Status: $"
-	call	PRTHEXBYTE
-
-;	and	%00111011		; set non-zero
-;	sub	%00011011		; if failed
-;
+	call	DMASTATUS
 #ENDIF
 ;
 	ret
@@ -721,7 +790,7 @@ DMALengthInt	.dw	0 		; R0-Block length
 		.db	%00010100	; R1-No timing bytes follow, address increments, is memory
 		.db	%00010000 	; R2-No timing bytes follow, address increments, is memory
 		.db	%10100000 	; R3-DMA, interrupt, stop on match disabled
-		.db	DMA_CONTINUOUS	; R4-Continuous mode, destination address, interrupt and control byte follow
+DMAICopyMode:	.db	DMA_CONTINUOUS	; R4-Transfer mode, destination address, interrupt and control byte follow
 DMADestInt	.dw	0 		; R4-Port B, Destination address
 		.db	%00011110	; R4-Interrupt control byte: Pulse byte follows, Pulse generated
 		.db	0		; R4-Pulse control byte
@@ -743,6 +812,10 @@ DMAOTIR:
 	ld	(DMAOutSource),hl	; populate the dma
 	ld	(DMAOutDest),a		; register template
 	ld	(DMAOutLength),bc	
+;
+	ld	hl,DMAOutMode
+	call	SETXFER
+	res	3,(hl)			; no upper address
 ;
 	ld	hl,DMAOutCode		; program the
 	ld	b,DMAOut_Len		; dma command
@@ -753,14 +826,7 @@ DMAOTIR:
 	otir				; load and execute dma
 	ei
 ;
-	ld	a,DMA_READ_STATUS_BYTE	; check status
-	out	(c),a			; of transfer
-	in	a,(c)			; set non-zero
-
-
-;	and	%00111011		; if failed
-;	sub	%00011011
-;
+	call	DMASTATUS
 	ret
 ;
 DMAOutCode  	;.db	DMA_DISABLE	; R6-Command Disable DMA
@@ -772,10 +838,10 @@ DMAOutLength	.dw	0 		; R0-Block length
 		.db	%00101000 	; R2-No timing bytes follow, address static, is i/o			
 		.db	%10000000 	; R3-DMA, interrupt, stop on match disabled
 
-		.db	%10100101	; R4-Continuous mode, destination port, interrupt and control byte follow
+DMAOutMode:	.db	DMA_CONTINUOUS	; R4-Transfer Mode, destination port, interrupt and control byte follow
 DMAOutDest	.db	0 		; R4-Port B, Destination port
-;		.db	%00001100	; R4-Pulse byte follows, Pulse generated
-;		.db	0		; R4-Pulse offset
+		.db	DMA_ICBYTE	; R4-Pulse byte follows, Pulse generated
+		.db	0		; R4-Pulse offset
 
 		.db	%10010010+DMA_RDY;R5-Stop on end of block, ce/wait multiplexed, READY active config	
 		.db	DMA_LOAD 	; R6-Command Load							
@@ -794,6 +860,10 @@ DMAINIR:
 	ld	(DMAInSource),a		; register template
 	ld	(DMAInLength),bc	
 ;
+	ld	hl,DMAOutMode
+	call	SETXFER
+	res	3,(hl)			; no upper address
+
 	ld	hl,DMAInCode		; program the
 	ld	b,DMAIn_Len		; dma command
 	ld	a,(dmaport)		; block
@@ -803,13 +873,7 @@ DMAINIR:
 	otir				; load and execute dma
 	ei
 ;
-	ld	a,DMA_READ_STATUS_BYTE	; check status
-	out	(c),a			; of transfer
-	in	a,(c)			; set non-zero
-
-;	and	%00111011		; if failed
-;	sub	%00011011
-;
+	call	DMASTATUS
 	ret
 ;
 DMAInCode 	;.db	DMA_DISABLE	; R6-Command Disable DMA
@@ -819,10 +883,10 @@ DMAInLength	.dw	0 		; R0-Block length
 		.db	%00010100	; R1-No timing bytes follow, address increments, is memory		
 		.db	%00111000 	; R2-No timing bytes follow, address static, is i/o			
 		.db	%10000000 	; R3-DMA, interrupt, stop on match disabled
-		.db	%10100101	; R4-Continuous mode, destination port, no interrupt, control byte.	
+DMAInMode:	.db	DMA_CONTINUOUS	; R4-Transfer mode, destination port, no interrupt, control byte.	
 DMAInSource	.db	0 		; R4-Port B, Destination port
-;		.db	%00001100	; R4-Pulse byte follows, Pulse generated
-;		.db	0		; R4-Pulse offset
+		.db	DMA_ICBYTE	; R4-Pulse byte follows, Pulse generated
+		.db	0		; R4-Pulse offset
 		.db	%10010010+DMA_RDY;R5-Stop on end of block, ce/wait multiplexed, READY active config	
 		.db	DMA_LOAD 	; R6-Command Load							
 		.db	DMA_FORCE_READY	; R6-Command Force ready						
@@ -831,6 +895,99 @@ DMAInSource	.db	0 		; R4-Port B, Destination port
 DMAIn_Len 	.equ	$-DMAInCode
 ;
 ;==================================================================================================
+; SET TRANSFER MODE
+;==================================================================================================
+;
+SETXFER:
+	ld	a,(dmaxfer)		; setup the 
+	cp	0			; transfer mode
+	jr	nz,DMAX1
+	ld	a,DMA_BYTE
+	jr	DMAX3
+DMAX1:	cp	1
+	jr	nz,DMAX2
+	ld	a,DMA_CONTINUOUS
+	jr	DMAX3
+DMAX2:	cp	2
+	ret	nz
+	ld	a,DMA_BURST
+DMAX3:	ld	(hl),a
+	ret
+;
+;==================================================================================================
+; GET STATUS
+;==================================================================================================
+;
+DMASTATUS:
+	ld	a,(dmaxfer)		; if byte mode
+	cp	0			; give some time to finish
+	jr	nz,DMASTS1
+
+;	ld	b,1
+;DMASTS2:call	delay
+;	djnz	DMASTS2
+;
+DMASTS1:ld	a,DMA_READ_STATUS_BYTE	; check status
+	out	(c),a			; of transfer
+	in	a,(c)
+	and	%00111011
+;
+;	push	af
+;	ld	a,DMA_REINIT_STATUS_BYTE
+;	out	(c),a
+;	pop	af
+;
+	call	PRTSTRD
+	.db	"\n\rReturn Status: $"
+	call	PRTHEXBYTE
+	call	NEWLINE
+;
+	ld	c,a
+	ld	a,(dmavbs)
+	or	a
+	jr	z,DMSSTS2
+	ld	a,c
+;
+	ld	a,%00000001
+	ld	de,DMASTSBIT0
+	call	PRTIDXMSK
+;
+	ld	a,%00000010
+	ld	de,DMASTSBIT1
+	call	PRTIDXMSK
+;
+	ld	a,%00001000
+	ld	de,DMASTSBIT3
+	call	PRTIDXMSK
+;
+	ld	a,%00010000
+	ld	de,DMASTSBIT4
+	call	PRTIDXMSK
+;
+	ld	a,%00100000
+	ld	de,DMASTSBIT5
+	call	PRTIDXMSK
+;
+DMSSTS2:ld	a,c
+	ret
+
+DMASTSBIT0:
+	.TEXT	"DMA Bus request did not occur after LOAD command\n\r$"
+	.TEXT	"DMA Bus request occurred after the LOAD command\n\r$"
+DMASTSBIT1:
+	.TEXT	"Ready line inactive\n\r$"
+	.TEXT	"Ready line active\n\r$"
+DMASTSBIT3:
+	.TEXT	"Interrupt pending\n\r$"
+	.TEXT	"No interrupt pending\n\r$"
+DMASTSBIT4:
+	.TEXT	"Match found\n\r$"
+	.TEXT	"No match found\n\r$"
+DMASTSBIT5:
+	.TEXT	"End of block reached\n\r$"
+	.TEXT	"End of block not reached\n\r$"
+;
+;==================================================================================================
 ; DEBUG - READ START, DESTINATION AND COUNT REGISTERS
 ;==================================================================================================
 ;
@@ -1010,7 +1167,11 @@ CST:
 	RET
 ;
 USEINT	.DB	FALSE		; USE INTERRUPTS FLAG
-;
+counter	.dw	0	
+dmaport	.db	DMABASE
+dmautil	.db	DMABASE+1
+dmaxfer	.db	DMA_XMODE
+dmavbs	.db	0
 SAVSTK:	.DW	2
 	.FILL	64
 STACK:	.EQU	$
@@ -1050,10 +1211,6 @@ int:
 	or	$ff		; signal int handled
 	ret
 ;
-counter	.dw	0	
-dmaport	.db	DMABASE
-dmautil	.db	DMABASE+1
-;
 hsiz	.equ	$ - $A000	; size of handler to relocate
 ;
 	.org	reladr + hsiz

Source/Apps/Tune/tune.asm

@@ -45,6 +45,7 @@
 ;   2021-08-13 [WBW] Add support for LiNC Z50 Sound Card
 ;   2021-08-17 [WBW] When playing via HBIOS, call BF_SNDRESET at end
 ;   2022-03-20 [DDW] Add support for MBC PSG module
+;   2023-03-30 [WBW] Fix for quark delay adjustment being trashed
 ;_______________________________________________________________________________
 ;
 ; ToDo:
@@ -301,6 +302,11 @@ GOPT3	LD	A,0			; SETUP value to PT3 sound files
 	JR	GOPTX			; Play PTx file
 
 GOPTX
+	LD	HL,(QDLY)		; Get basic quark delay
+	OR	A			; Clear carry
+	SBC	HL,DE			; Adjust for file type
+	LD	(QDLY),HL		; Save updated quark delay factor
+
 	CALL	CRLF2
 	LD	DE, MSGSONGNAME         ; Print song name message
 	CALL	PRTSTR
@@ -322,10 +328,6 @@ GOPTX2	LD	A,(DE)
 	CALL	CRLF2			; Formatting
 	LD	DE,MSGPLY		; Playing message
 	CALL	PRTSTR			; Print message
-	LD	HL,(QDLY)		; Get basic quark delay
-	OR	A			; Clear carry
-	SBC	HL,DE			; Adjust for file type
-	LD	(QDLY),HL		; Save updated quark delay factor
 	CALL	START			; Do initialization
 PTXLP	CALL	START+5			; Play one quark
 	LD	A,(START+10)		; Get setup byte
@@ -655,8 +657,8 @@ TMP		.DB	0	; work around use of undocumented Z80
 HBIOSMD		.DB	0	; NON-ZERO IF USING HBIOS SOUND DRIVER, ZERO OTHERWISE
 OCTAVEADJ	.DB	0	; AMOUNT TO ADJUST OCTAVE UP OR DOWN
 
-MSGBAN		.DB	"Tune Player for RomWBW v3.5, 20-Mar-2022",0
-MSGUSE		.DB	"Copyright (C) 2021, Wayne Warthen, GNU GPL v3",13,10
+MSGBAN		.DB	"Tune Player for RomWBW v3.5a, 30-Mar-2023",0
+MSGUSE		.DB	"Copyright (C) 2023, Wayne Warthen, GNU GPL v3",13,10
 		.DB	"PTxPlayer Copyright (C) 2004-2007 S.V.Bulba",13,10
 		.DB	"MYMPlay by Marq/Lieves!Tuore",13,10,13,10
 		.DB	"Usage: TUNE <filename>.[PT2|PT3|MYM] [--hbios] [+tn|-tn]",0

Source/Apps/VGM/vgmplay.asm

@@ -12,14 +12,12 @@
 ; default file type, basic file size checking, polled CTC mode
 ; added by Phil Summers
 ;
-; Bugs: YM2151 playback untested & no mute.
-;       CTC polled timing - predicted 44100 divider is too slow
+; Bugs: CTC polled timing - predicted 44100 divider is too slow
 ;
 ; Assemble with:
 ;
 ;   TASM -80 -b VGMPLAY.ASM VGMPLAY.COM
 ;
-;
 ; A VGM file can play 44100 samples a second. This may be sound chip
 ; register commands or PCM data. This player does not support PCM playback
 ; due to the high processor speed and file size required. Typical VGM files
@@ -31,60 +29,59 @@
 ; Device and system specific definitions
 ;------------------------------------------------------------------------------
 ;
-custom		.equ	0           	        ; System configurations
+custom		.equ	0           	; System configurations
 P8X180          .equ    1
 RCBUS           .equ    2
-sbcecb		.equ	3			
+sbcecb		.equ	3		
 MBC		.equ	4
 ;
-plt_romwbw	.equ	1			; Build for ROMWBW?
-plt_type	.equ	sbcecb			; Select build configuration
-debug		.equ	0			; Display port, register, config info
+plt_romwbw	.equ	1		; Build for ROMWBW?
+plt_type	.equ	sbcecb		; Select build configuration
+debug		.equ	0		; Display port, register, config info
 ;
 ;------------------------------------------------------------------------------
 ; Platform specific definitions. If building for ROMWBW, these may be overridden
 ;------------------------------------------------------------------------------
 
 #IF (plt_type=custom)
-RSEL            .equ    09AH			; Primary AY-3-8910 Register selection
-RDAT            .equ    09BH			; Primary AY-3-8910 Register data
-RSEL2           .equ    88H			; Secondary AY-3-8910 Register selection
-RDAT2           .equ    89H			; Secondary AY-3-8910 Register data
+RSEL            .equ    09AH		; Primary AY-3-8910 Register selection
+RDAT            .equ    09BH		; Primary AY-3-8910 Register data
+RSEL2           .equ    88H		; Secondary AY-3-8910 Register selection
+RDAT2           .equ    89H		; Secondary AY-3-8910 Register data
 VGMBASE		.equ	$C0
-YMSEL		.equ	VGMBASE+00H		; Primary YM2162 11000000 a1=0 a0=0
-YMDAT		.equ	VGMBASE+01H		; Primary YM2162 11000001 a1=0 a0=1
-YM2SEL		.equ	VGMBASE+02H		; Secondary YM2162 11000010 a1=1 a0=0
-YM2DAT		.equ	VGMBASE+03H		; Secondary YM2162 11000011 a1=1 a0=1
-PSG1REG         .equ    VGMBASE+08H		; Primary SN76489
-PSG2REG         .equ    VGMBASE+09H		; Secondary SN76489
-ctcbase		.equ	VGMBASE+0CH		; CTC base address
-YM2151_SEL1	.equ	0FEH			; Primary YM2151 register selection
-YM2151_DAT1	.equ	0FFH			; Primary YM2151 register data
-YM2151_SEL2	.equ	0FEH			; Secondary YM2151 register selection
-YM2151_DAT2	.equ	0FFH			; Secondary YM2151 register data
-plt_cpuspd	.equ	6;000000		; Non ROMWBW cpu speed default
-FRAME_DLY       .equ    10  			; Frame delay (~ 1/44100)
-
+YMSEL		.equ	VGMBASE+00H	; Primary YM2162 11000000 a1=0 a0=0
+YMDAT		.equ	VGMBASE+01H	; Primary YM2162 11000001 a1=0 a0=1
+YM2SEL		.equ	VGMBASE+02H	; Secondary YM2162 11000010 a1=1 a0=0
+YM2DAT		.equ	VGMBASE+03H	; Secondary YM2162 11000011 a1=1 a0=1
+PSG1REG         .equ    VGMBASE+04H	; Primary SN76489
+PSG2REG         .equ    VGMBASE+05H	; Secondary SN76489
+YM2151_SEL1	.equ	VGMBASE+08H	; Primary YM2151 register selection
+YM2151_DAT1	.equ	VGMBASE+09H	; Primary YM2151 register data
+YM2151_SEL2	.equ	VGMBASE+0AH	; Secondary YM2151 register selection
+YM2151_DAT2	.equ	VGMBASE+0BH	; Secondary YM2151 register data
+ctcbase		.equ	VGMBASE+0CH	; CTC base address
+plt_cpuspd	.equ	6;000000	; Non ROMWBW cpu speed default
+FRAME_DLY       .equ    10  		; Frame delay (~ 1/44100)
 #ENDIF
 ;
 #IF (plt_type=P8X180)
-RSEL            .equ    82H			; Primary AY-3-8910 Register selection
-RDAT            .equ    83H			; Primary AY-3-8910 Register data
-RSEL2           .equ    88H			; Secondary AY-3-8910 Register selection
-RDAT2           .equ    89H			; Secondary AY-3-8910 Register data
-PSG1REG         .equ    84H			; Primary SN76489
-PSG2REG         .equ    8AH			; Secondary SN76489
-YM2151_SEL1	.equ	0B0H			; Primary YM2151 register selection
-YM2151_DAT1	.equ	0B1H			; Primary YM2151 register data
-YM2151_SEL2	.equ	0B2H			; Secondary YM2151 register selection
-YM2151_DAT2	.equ	0B3H			; Secondary YM2151 register data
-ctcbase		.equ	000H			; CTC base address
-YMSEL		.equ	000H			; Primary YM2162 11000000 a1=0 a0=0
-YMDAT		.equ	000H			; Primary YM2162 11000001 a1=0 a0=1
-YM2SEL		.equ	000H			; Secondary YM2162 11000010 a1=1 a0=0
-YM2DAT		.equ	000H			; Secondary YM2162 11000011 a1=1 a0=1
-FRAME_DLY       .equ    48			; Frame delay (~ 1/44100)
-plt_cpuspd	.equ	20			; Non ROMWBW cpu speed default
+RSEL            .equ    82H		; Primary AY-3-8910 Register selection
+RDAT            .equ    83H		; Primary AY-3-8910 Register data
+RSEL2           .equ    88H		; Secondary AY-3-8910 Register selection
+RDAT2           .equ    89H		; Secondary AY-3-8910 Register data
+PSG1REG         .equ    84H		; Primary SN76489
+PSG2REG         .equ    8AH		; Secondary SN76489
+YM2151_SEL1	.equ	0B0H		; Primary YM2151 register selection
+YM2151_DAT1	.equ	0B1H		; Primary YM2151 register data
+YM2151_SEL2	.equ	0B2H		; Secondary YM2151 register selection
+YM2151_DAT2	.equ	0B3H		; Secondary YM2151 register data
+ctcbase		.equ	000H		; CTC base address
+YMSEL		.equ	000H		; Primary YM2162 11000000 a1=0 a0=0
+YMDAT		.equ	000H		; Primary YM2162 11000001 a1=0 a0=1
+YM2SEL		.equ	000H		; Secondary YM2162 11000010 a1=1 a0=0
+YM2DAT		.equ	000H		; Secondary YM2162 11000011 a1=1 a0=1
+FRAME_DLY       .equ    48		; Frame delay (~ 1/44100)
+plt_cpuspd	.equ	20		; Non ROMWBW cpu speed default
 #ENDIF
 ;
 #IF (plt_type=RCBUS)
@@ -103,7 +100,7 @@ YMSEL		.equ	000H		; UNDEFINED	; Primary YM2162 11000000 a1=0 a0=0
 YMDAT		.equ	000H		; UNDEFINED	; Primary YM2162 11000001 a1=0 a0=1
 YM2SEL		.equ	000H		; UNDEFINED	; Secondary YM2162 11000010 a1=1 a0=0
 YM2DAT		.equ	000H		; UNDEFINED	; Secondary YM2162 11000011 a1=1 a0=1
-plt_cpuspd	.equ	7;372800	; CPUOSC		; Non ROMWBW cpu speed default
+plt_cpuspd	.equ	7;372800	; CPUOSC	; Non ROMWBW cpu speed default
 FRAME_DLY       .equ    12				; Frame delay (~ 1/44100)
 #ENDIF
 ;
@@ -184,7 +181,7 @@ RTCIO		.equ	070H
 ; YM2162 Register write macros - with wait and timeout
 ;------------------------------------------------------------------------------
 ;
-#DEFINE	setreg(reg,val) \
+#DEFINE	s2612reg(reg,val) \
 #DEFCONT \	ld	a,reg 
 #DEFCONT \	out	(YMSEL),a 
 #DEFCONT \	ld	a,val 
@@ -195,7 +192,7 @@ RTCIO		.equ	070H
 #DEFCONT \	jp	nc,$+5
 #DEFCONT \	djnz	$-6
 ;
-#DEFINE	setreg2(reg,val) \
+#DEFINE	s2612reg2(reg,val) \
 #DEFCONT \	ld	a,reg 
 #DEFCONT \	out	(YM2SEL),a 
 #DEFCONT \	ld	a,val 
@@ -205,9 +202,30 @@ RTCIO		.equ	070H
 #DEFCONT \	rlca
 #DEFCONT \	jp	nc,$+5
 #DEFCONT \	djnz	$-6
-
+;
 ;------------------------------------------------------------------------------
-; VGM Codes - see vgmrips.net/wiki/VGM_specification
+; YM2151 Register write macros - with wait and timeout
+;------------------------------------------------------------------------------
+;
+; Status Byte: 	Bit
+;		7       Busy Flag (1=Busy)
+;		6-2     Not Used
+;		1       Timer B Overflow (0=No Overflow, 1=Overflow)
+;		0       Timer A Overflow (0=No Overflow, 1=Overflow)
+;
+#DEFINE	s2151reg(reg,val) \
+#DEFCONT \	ld	a,reg 
+#DEFCONT \	out	(YM2151_SEL1),a 
+#DEFCONT \	ld	a,val 
+#DEFCONT \	out	(YM2151_DAT1),a 
+#DEFCONT \	ld	b,0
+#DEFCONT \	in	a,(YM2151_SEL1)
+#DEFCONT \	rlca
+#DEFCONT \	jp	nc,$+5
+#DEFCONT \	djnz	$-6
+;
+;------------------------------------------------------------------------------
+; VGM Codes - see vgmrips.net/wiki/VGM_Specification
 ;------------------------------------------------------------------------------
 
 VGM_GG_W	.equ	04FH			; GAME GEAR PSG STEREO. WRITE DD TO PORT 0X06
@@ -219,8 +237,8 @@ VGM_WNS		.equ	061H			; WAIT N SAMPLES
 VGM_W735	.equ	062H			; WAIT 735 SAMPLES (1/60TH SECOND)
 VGM_W882	.equ	063H			; WAIT 882 SAMPLES (1/50TH SECOND)
 VGM_ESD		.equ	066H			; END OF SOUND DATA
-VGM_YM21511_W	.equ	054H			; YM2612 #1 WRITE VALUE DD
-VGM_YM21512_W	.equ	0A4H			; YM2612 #2 WRITE VALUE DD
+VGM_YM21511_W	.equ	054H			; YM2151 #1 WRITE VALUE DD
+VGM_YM21512_W	.equ	0A4H			; YM2151 #2 WRITE VALUE DD
 
 ;------------------------------------------------------------------------------
 ; Generic CP/M definitions
@@ -490,7 +508,7 @@ YM2162_2	CP      VGM_YM26122_W
 ;	YM2151 SECTION
 ;
 YM2151_1	CP      VGM_YM21511_W
-                JR      NZ,YM2151_2
+		JR      NZ,YM2151_2
 		LD	A,(HL)
 		OUT	(YM2151_SEL1),A
 		INC	HL
@@ -759,252 +777,254 @@ SKIP1:		LD	A,(IX+0)
                 XOR     A
                 OUT     (RDAT), A
                 OUT     (RDAT2), A
+#IFDEF SBCV2004
 		CALL	FASTIO
+#ENDIF
 
 SKIP2:		LD	A,(IX+0)		; mute all channels on ym2612
 		AND	%00110000
 		JP	Z,SKIP3
 
-		setreg($22,$00)			; lfo off
+		s2612reg($22,$00)		; lfo off
 
-		setreg($27,$00)			; Disable independant Channel 3
-		setreg($28,$00)			; note off ch 1
-		setreg($28,$01)			; note off ch 2
-		setreg($28,$02)			; note off ch 3
-		setreg($28,$04)			; note off ch 4
-		setreg($28,$05)			; note off ch 5
-		setreg($28,$06)			; note off ch 6
-		setreg($2b,$00)			; dac off
+		s2612reg($27,$00)		; Disable independant Channel 3
+		s2612reg($28,$00)		; note off ch 1
+		s2612reg($28,$01)		; note off ch 2
+		s2612reg($28,$02)		; note off ch 3
+		s2612reg($28,$04)		; note off ch 4
+		s2612reg($28,$05)		; note off ch 5
+		s2612reg($28,$06)		; note off ch 6
+		s2612reg($2b,$00)		; dac off
 
-		setreg($b4,$00)			; sound off ch 1-3
-		setreg($b5,$00)
-		setreg($b6,$00)
-		setreg2($b4,$00)		; sound off ch 4-6
-		setreg2($b5,$00)
-		setreg2($b6,$00)
+		s2612reg($b4,$00)		; sound off ch 1-3
+		s2612reg($b5,$00)
+		s2612reg($b6,$00)
+		s2612reg2($b4,$00)		; sound off ch 4-6
+		s2612reg2($b5,$00)
+		s2612reg2($b6,$00)
 
-		setreg($40,$7f)			; ch 1-3 total level minimum
-		setreg($41,$7f)
-		setreg($42,$7f)
-		setreg($44,$7f)
-		setreg($45,$7f)
-		setreg($46,$7f)
-		setreg($48,$7f)
-		setreg($49,$7f)
-		setreg($4a,$7f)
-		setreg($4c,$7f)
-		setreg($4d,$7f)
-		setreg($4e,$7f)
+		s2612reg($40,$7f)		; ch 1-3 total level minimum
+		s2612reg($41,$7f)
+		s2612reg($42,$7f)
+		s2612reg($44,$7f)
+		s2612reg($45,$7f)
+		s2612reg($46,$7f)
+		s2612reg($48,$7f)
+		s2612reg($49,$7f)
+		s2612reg($4a,$7f)
+		s2612reg($4c,$7f)
+		s2612reg($4d,$7f)
+		s2612reg($4e,$7f)
 
-		setreg2($40,$7f)		; ch 4-6 total level minimum
-		setreg2($41,$7f)
-		setreg2($42,$7f)
-		setreg2($44,$7f)
-		setreg2($45,$7f)
-		setreg2($46,$7f)
-		setreg2($48,$7f)
-		setreg2($49,$7f)
-		setreg2($4a,$7f)
-		setreg2($4c,$7f)
-		setreg2($4d,$7f)
-		setreg2($4e,$7f)
+		s2612reg2($40,$7f)		; ch 4-6 total level minimum
+		s2612reg2($41,$7f)
+		s2612reg2($42,$7f)
+		s2612reg2($44,$7f)
+		s2612reg2($45,$7f)
+		s2612reg2($46,$7f)
+		s2612reg2($48,$7f)
+		s2612reg2($49,$7f)
+		s2612reg2($4a,$7f)
+		s2612reg2($4c,$7f)
+		s2612reg2($4d,$7f)
+		s2612reg2($4e,$7f)
 
 #if (0)
 
-		setreg($2a,$00)			; dac value
+		s2612reg($2a,$00)		; dac value
 
-		setreg($24,$00)			; timer A frequency
-		setreg($25,$00)			; timer A frequency
-		setreg($26,$00)			; time B frequency
+		s2612reg($24,$00)		; timer A frequency
+		s2612reg($25,$00)		; timer A frequency
+		s2612reg($26,$00)		; time B frequency
 
-		setreg($30,$00)			; ch 1-3 multiply & detune
-		setreg($31,$00)
-		setreg($32,$00)
-		setreg($34,$00)
-		setreg($35,$00)
-		setreg($36,$00)
-		setreg($38,$00)
-		setreg($39,$00)
-		setreg($3a,$00)
-		setreg($3c,$00)
-		setreg($3d,$00)
-		setreg($3e,$00)
+		s2612reg($30,$00)		; ch 1-3 multiply & detune
+		s2612reg($31,$00)
+		s2612reg($32,$00)
+		s2612reg($34,$00)
+		s2612reg($35,$00)
+		s2612reg($36,$00)
+		s2612reg($38,$00)
+		s2612reg($39,$00)
+		s2612reg($3a,$00)
+		s2612reg($3c,$00)
+		s2612reg($3d,$00)
+		s2612reg($3e,$00)
 
-		setreg2($30,$00)		; ch 4-6 multiply & detune
-		setreg2($31,$00)
-		setreg2($32,$00)
-		setreg2($34,$00)
-		setreg2($35,$00)
-		setreg2($36,$00)
-		setreg2($38,$00)
-		setreg2($39,$00)
-		setreg2($3a,$00)
-		setreg2($3c,$00)
-		setreg2($3d,$00)
-		setreg2($3e,$00)
+		s2612reg2($30,$00)		; ch 4-6 multiply & detune
+		s2612reg2($31,$00)
+		s2612reg2($32,$00)
+		s2612reg2($34,$00)
+		s2612reg2($35,$00)
+		s2612reg2($36,$00)
+		s2612reg2($38,$00)
+		s2612reg2($39,$00)
+		s2612reg2($3a,$00)
+		s2612reg2($3c,$00)
+		s2612reg2($3d,$00)
+		s2612reg2($3e,$00)
 
-		setreg($50,$00)			; ch 1-3 attack rate and scaling
-		setreg($51,$00)
-		setreg($52,$00)
-		setreg($54,$00)
-		setreg($55,$00)
-		setreg($56,$00)
-		setreg($58,$00)
-		setreg($59,$00)
-		setreg($5a,$00)
-		setreg($5c,$00)
-		setreg($5d,$00)
-		setreg($5e,$00)
+		s2612reg($50,$00)		; ch 1-3 attack rate and scaling
+		s2612reg($51,$00)
+		s2612reg($52,$00)
+		s2612reg($54,$00)
+		s2612reg($55,$00)
+		s2612reg($56,$00)
+		s2612reg($58,$00)
+		s2612reg($59,$00)
+		s2612reg($5a,$00)
+		s2612reg($5c,$00)
+		s2612reg($5d,$00)
+		s2612reg($5e,$00)
 
-		setreg2($50,$00)		; ch 4-6 attack rate and scaling
-		setreg2($51,$00)
-		setreg2($52,$00)
-		setreg2($54,$00)
-		setreg2($55,$00)
-		setreg2($56,$00)
-		setreg2($58,$00)
-		setreg2($59,$00)
-		setreg2($5a,$00)
-		setreg2($5c,$00)
-		setreg2($5d,$00)
-		setreg2($5e,$00)
+		s2612reg2($50,$00)		; ch 4-6 attack rate and scaling
+		s2612reg2($51,$00)
+		s2612reg2($52,$00)
+		s2612reg2($54,$00)
+		s2612reg2($55,$00)
+		s2612reg2($56,$00)
+		s2612reg2($58,$00)
+		s2612reg2($59,$00)
+		s2612reg2($5a,$00)
+		s2612reg2($5c,$00)
+		s2612reg2($5d,$00)
+		s2612reg2($5e,$00)
 
-		setreg($60,$00)			; ch 1-3 decay rate and am enable
-		setreg($61,$00)
-		setreg($62,$00)
-		setreg($64,$00)
-		setreg($65,$00)
-		setreg($66,$00)
-		setreg($68,$00)
-		setreg($69,$00)
-		setreg($6a,$00)
-		setreg($6c,$00)
-		setreg($6d,$00)
-		setreg($6e,$00)
+		s2612reg($60,$00)		; ch 1-3 decay rate and am enable
+		s2612reg($61,$00)
+		s2612reg($62,$00)
+		s2612reg($64,$00)
+		s2612reg($65,$00)
+		s2612reg($66,$00)
+		s2612reg($68,$00)
+		s2612reg($69,$00)
+		s2612reg($6a,$00)
+		s2612reg($6c,$00)
+		s2612reg($6d,$00)
+		s2612reg($6e,$00)
 
-		setreg2($60,$00)		; ch 4-6 decay rate and am enable
-		setreg2($61,$00)
-		setreg2($62,$00)
-		setreg2($64,$00)
-		setreg2($65,$00)
-		setreg2($66,$00)
-		setreg2($68,$00)
-		setreg2($69,$00)
-		setreg2($6a,$00)
-		setreg2($6c,$00)
-		setreg2($6d,$00)
-		setreg2($6e,$00)
+		s2612reg2($60,$00)		; ch 4-6 decay rate and am enable
+		s2612reg2($61,$00)
+		s2612reg2($62,$00)
+		s2612reg2($64,$00)
+		s2612reg2($65,$00)
+		s2612reg2($66,$00)
+		s2612reg2($68,$00)
+		s2612reg2($69,$00)
+		s2612reg2($6a,$00)
+		s2612reg2($6c,$00)
+		s2612reg2($6d,$00)
+		s2612reg2($6e,$00)
 
-		setreg($70,$00)			; ch 1-3 sustain rate
-		setreg($71,$00)
-		setreg($72,$00)
-		setreg($74,$00)
-		setreg($75,$00)
-		setreg($76,$00)
-		setreg($78,$00)
-		setreg($79,$00)
-		setreg($7a,$00)
-		setreg($7c,$00)
-		setreg($7d,$00)
-		setreg($7e,$00)
+		s2612reg($70,$00)		; ch 1-3 sustain rate
+		s2612reg($71,$00)
+		s2612reg($72,$00)
+		s2612reg($74,$00)
+		s2612reg($75,$00)
+		s2612reg($76,$00)
+		s2612reg($78,$00)
+		s2612reg($79,$00)
+		s2612reg($7a,$00)
+		s2612reg($7c,$00)
+		s2612reg($7d,$00)
+		s2612reg($7e,$00)
 
-		setreg2($70,$00)		; ch 4-6 sustain rate
-		setreg2($71,$00)
-		setreg2($72,$00)
-		setreg2($74,$00)
-		setreg2($75,$00)
-		setreg2($76,$00)
-		setreg2($78,$00)
-		setreg2($79,$00)
-		setreg2($7a,$00)
-		setreg2($7c,$00)
-		setreg2($7d,$00)
-		setreg2($7e,$00)
+		s2612reg2($70,$00)		; ch 4-6 sustain rate
+		s2612reg2($71,$00)
+		s2612reg2($72,$00)
+		s2612reg2($74,$00)
+		s2612reg2($75,$00)
+		s2612reg2($76,$00)
+		s2612reg2($78,$00)
+		s2612reg2($79,$00)
+		s2612reg2($7a,$00)
+		s2612reg2($7c,$00)
+		s2612reg2($7d,$00)
+		s2612reg2($7e,$00)
 
-		setreg($80,$00)			; ch 1-3 release rate and sustain level
-		setreg($81,$00)
-		setreg($82,$00)
-		setreg($84,$00)
-		setreg($85,$00)
-		setreg($86,$00)
-		setreg($88,$00)
-		setreg($89,$00)
-		setreg($8a,$00)
-		setreg($8c,$00)
-		setreg($8d,$00)
-		setreg($8e,$00)
+		s2612reg($80,$00)		; ch 1-3 release rate and sustain level
+		s2612reg($81,$00)
+		s2612reg($82,$00)
+		s2612reg($84,$00)
+		s2612reg($85,$00)
+		s2612reg($86,$00)
+		s2612reg($88,$00)
+		s2612reg($89,$00)
+		s2612reg($8a,$00)
+		s2612reg($8c,$00)
+		s2612reg($8d,$00)
+		s2612reg($8e,$00)
 
-		setreg2($80,$00)		; ch 4-6 release rate and sustain level
-		setreg2($81,$00)
-		setreg2($82,$00)
-		setreg2($84,$00)
-		setreg2($85,$00)
-		setreg2($86,$00)
-		setreg2($88,$00)
-		setreg2($89,$00)
-		setreg2($8a,$00)
-		setreg2($8c,$00)
-		setreg2($8d,$00)
-		setreg2($8e,$00)
+		s2612reg2($80,$00)		; ch 4-6 release rate and sustain level
+		s2612reg2($81,$00)
+		s2612reg2($82,$00)
+		s2612reg2($84,$00)
+		s2612reg2($85,$00)
+		s2612reg2($86,$00)
+		s2612reg2($88,$00)
+		s2612reg2($89,$00)
+		s2612reg2($8a,$00)
+		s2612reg2($8c,$00)
+		s2612reg2($8d,$00)
+		s2612reg2($8e,$00)
 
-		setreg($90,$00)			; ch 1-3 ssg-eg
-		setreg($91,$00)
-		setreg($92,$00)
-		setreg($94,$00)
-		setreg($95,$00)
-		setreg($96,$00)
-		setreg($98,$00)
-		setreg($99,$00)
-		setreg($9a,$00)
-		setreg($9c,$00)
-		setreg($9d,$00)
-		setreg($9e,$00)
+		s2612reg($90,$00)		; ch 1-3 ssg-eg
+		s2612reg($91,$00)
+		s2612reg($92,$00)
+		s2612reg($94,$00)
+		s2612reg($95,$00)
+		s2612reg($96,$00)
+		s2612reg($98,$00)
+		s2612reg($99,$00)
+		s2612reg($9a,$00)
+		s2612reg($9c,$00)
+		s2612reg($9d,$00)
+		s2612reg($9e,$00)
 
-		setreg2($90,$00)		; ch 4-6 ssg-eg
-		setreg2($91,$00)
-		setreg2($92,$00)
-		setreg2($94,$00)
-		setreg2($95,$00)
-		setreg2($96,$00)
-		setreg2($98,$00)
-		setreg2($99,$00)
-		setreg2($9a,$00)
-		setreg2($9c,$00)
-		setreg2($9d,$00)
-		setreg2($9e,$00)
+		s2612reg2($90,$00)		; ch 4-6 ssg-eg
+		s2612reg2($91,$00)
+		s2612reg2($92,$00)
+		s2612reg2($94,$00)
+		s2612reg2($95,$00)
+		s2612reg2($96,$00)
+		s2612reg2($98,$00)
+		s2612reg2($99,$00)
+		s2612reg2($9a,$00)
+		s2612reg2($9c,$00)
+		s2612reg2($9d,$00)
+		s2612reg2($9e,$00)
 
-		setreg($a0,$00)			; ch 1-3 frequency
-		setreg($a1,$00)
-		setreg($a2,$00)
-		setreg($a4,$00)
-		setreg($a5,$00)
-		setreg($a6,$00)
-;		setreg($a8,$00)			; ch 3 special mode
-;		setreg($a9,$00)
-;		setreg($aa,$00)
-;		setreg($ac,$00)
-;		setreg($ad,$00)
-;		setreg($ae,$00)
+		s2612reg($a0,$00)		; ch 1-3 frequency
+		s2612reg($a1,$00)
+		s2612reg($a2,$00)
+		s2612reg($a4,$00)
+		s2612reg($a5,$00)
+		s2612reg($a6,$00)
+;		s2612reg($a8,$00)		; ch 3 special mode
+;		s2612reg($a9,$00)
+;		s2612reg($aa,$00)
+;		s2612reg($ac,$00)
+;		s2612reg($ad,$00)
+;		s2612reg($ae,$00)
 
-		setreg2($a0,$00)		; ch 4-6 frequency
-		setreg2($a1,$00)
-		setreg2($a2,$00)
-		setreg2($a4,$00)
-		setreg2($a5,$00)
-		setreg2($a6,$00)
-;		setreg2($a8,$00)		; ch 3 special mode
-;		setreg2($a9,$00)
-;		setreg2($aa,$00)
-;		setreg2($ac,$00)
-;		setreg2($ad,$00)
-;		setreg2($ae,$00)
+		s2612reg2($a0,$00)		; ch 4-6 frequency
+		s2612reg2($a1,$00)
+		s2612reg2($a2,$00)
+		s2612reg2($a4,$00)
+		s2612reg2($a5,$00)
+		s2612reg2($a6,$00)
+;		s2612reg2($a8,$00)		; ch 3 special mode
+;		s2612reg2($a9,$00)
+;		s2612reg2($aa,$00)
+;		s2612reg2($ac,$00)
+;		s2612reg2($ad,$00)
+;		s2612reg2($ae,$00)
 
-		setreg($b0,$00)			; ch 1-3 algorith + feedback
-		setreg($b1,$00)
-		setreg($b2,$00)
-		setreg2($b0,$00)		; ch 4-6 algorith + feedback
-		setreg2($b1,$00)
-		setreg2($b2,$00)
+		s2612reg($b0,$00)		; ch 1-3 algorith + feedback
+		s2612reg($b1,$00)
+		s2612reg($b2,$00)
+		s2612reg2($b0,$00)		; ch 4-6 algorith + feedback
+		s2612reg2($b1,$00)
+		s2612reg2($b2,$00)
 
 #endif
 		
@@ -1014,6 +1034,64 @@ SKIP3:		LD	A,(IX+0)		; For YM2151 ... Unimplemented
 
 		; MUTE YM2151
 
+		s2151reg($14,$30)		; disable timer %00110000		
+
+		s2151reg($0f,$00)		; disable noise
+;
+		s2151reg($1b,$00)		; CTx output off, LFO waveform
+
+		s2151reg($08,$00)		; key off all channels
+		s2151reg($08,$01)
+		s2151reg($08,$02)
+		s2151reg($08,$03)
+		s2151reg($08,$04)
+		s2151reg($08,$05)
+		s2151reg($08,$06)
+		s2151reg($08,$07)
+
+		s2151reg($60,$7f)		; total level = silent
+		s2151reg($61,$7f)
+		s2151reg($62,$7f)
+		s2151reg($63,$7f)
+		s2151reg($64,$7f)
+		s2151reg($65,$7f)
+		s2151reg($66,$7f)
+		s2151reg($67,$7f)
+		s2151reg($68,$7f)
+		s2151reg($69,$7f)
+		s2151reg($6A,$7f)
+		s2151reg($6B,$7f)
+		s2151reg($6C,$7f)
+		s2151reg($6D,$7f)
+		s2151reg($6E,$7f)
+		s2151reg($6F,$7f)
+		s2151reg($70,$7f)
+		s2151reg($71,$7f)
+		s2151reg($72,$7f)
+		s2151reg($73,$7f)
+		s2151reg($74,$7f)
+		s2151reg($75,$7f)
+		s2151reg($76,$7f)
+		s2151reg($77,$7f)
+		s2151reg($78,$7f)
+		s2151reg($79,$7f)
+		s2151reg($7A,$7f)
+		s2151reg($7B,$7f)
+		s2151reg($7C,$7f)
+		s2151reg($7D,$7f)
+		s2151reg($7E,$7f)
+		s2151reg($7F,$7f)
+
+		s2151reg($20,$00)		; channel output off, no feedback
+		s2151reg($21,$00)
+		s2151reg($22,$00)
+		s2151reg($23,$00)
+		s2151reg($24,$00)
+		s2151reg($25,$00)
+		s2151reg($26,$00)
+		s2151reg($27,$00)
+;
+
 SKIP4		RET
 ;
 ;------------------------------------------------------------------------------

Source/Apps/VGM/vgmplay.txt

@@ -21,7 +21,7 @@ Supported platforms
 ===================
 
 VGM Player is currently being developed on the ROMWBW platform using the Retrobrew computers
-EBC-SBC-V2 (Z80), ECB-SCG (AY-3-8910) and ECB-VGM (YM2612 and 2xSN76489) board. 
+EBC-SBC-V2 (Z80), ECB-SCG (AY-3-8910) and ECB-VGM (YM2612,YM2151 2xSN76489) board. 
 It can be configured to run with other hardware such as RCBus, P8X180 and nhyodyne MBC.
 
 VGM files can be very big and are limited in size by the available TPA space, which is typically 52k.
@@ -50,13 +50,15 @@ FIELDMAP.VGM - SN76489+YM2612      - Taikou Risshiden: Field Map: Summer
 ITSGAMOV.VGM - SN76489+YM2612      - Puyo Puyo Tsuu: It's Game Over!                              : 16K
 STARTDEM.VGN - 2xSN76489+AY-3-8910 * Exed Exes / Savage Bees: Start Demo ~Main BGM                : 32K
 INCHINA.VGM  - YM2612              * Double Dragon 3: The Rosetta Stone: In China                 : 44K
-
+SURE.VGM     - YM2151              - Martial Age: Sure??                                          : 36K
+SABERDAN.VGM - YM2151              - Road Runner: Sabre Dance (Attract Mode - Stage 4)            : 28K
 * Included in disk images
 
 VGM sources
 ===========
 https://www.smspower.org/forums/15359-VGMPacksGameGearMegaCollection
 https://vgmrips.net/packs/chip/ym2612
+https://vgmrips.net/packs/chip/ym2151 
 https://project2612.org/
 
 VGM Tools

Source/Doc/Applications.md

@@ -104,7 +104,7 @@ The `ASSIGN` command supports "stacking" of instructions. For example,
 two slices of IDE 0 and will unassign E:.
 
 When the command runs it will echo the resultant assignments to the
-console to confirm it's actions. It will also display the remaining
+console to confirm its actions. It will also display the remaining
 space available in disk buffers.
 
 ## Notes
@@ -158,7 +158,7 @@ should only be specified for hard disk devices (SD, IDE, PPIDE).
 Only one drive letter may be assigned to a specific device/unit/slice
 at a time. Attempts to assign a duplicate drive letter will fail and
 display an error. If you wish to assign a different drive letter to a
-device/unit/slice, unassign the the existing drive letter first.
+device/unit/slice, unassign the existing drive letter first.
 
 Be aware that this command will allow you to reassign or remove the
 assignment of your system drive letter. This can cause your operating
@@ -235,8 +235,8 @@ confusing that ZPM3 is in the file called CPM3.SYS, but it is normal
 for ZPM3.
 
 For the purposes of booting an operating system, each disk slice is
-considered it's own operating system. Each slice can be made bootable
-with it's own system tracks.
+considered its own operating system. Each slice can be made bootable
+with its own system tracks.
 
 `SYSCOPY` uses drive letters to specify where to read/write the system
 boot images. However, at startup, the boot loaded will require you to
@@ -246,7 +246,7 @@ to a drive letter so you will know what to enter at the boot loader
 prompt. By way of explanation, the boot loader does not know about
 drive letters because the operating system is not loaded yet.
 
-If you want to put a a boot system image on a device and slice that is
+If you want to put a boot system image on a device and slice that is
 not currently assigned to a drive letter, you will need to assign a
 drive letter first.
 
@@ -466,7 +466,7 @@ control is fully functional (end to end).
 The `XM` application provided in RomWBW is an adaptation of a
 pre-existing XModem application. Based on the source code comments, it
 was originally adapted from Ward Christensen's MODEM2 by Keith
-Petersen and is labeled version 12.5.
+Petersen and is labelled version 12.5.
 
 The original source of the application was found in the Walnut Creek
 CD-ROM and is called XMDM125.ARK dated 7/15/86.
@@ -529,14 +529,14 @@ manually perform a verification function with the `FLASH VERIFY` form
 of the command.
 
 The author's documentation for the application is found in the RomWBW
-distribution in the Doc\\Contrib directory.
+distribution in the Doc/Contrib directory.
 
 ## Notes
 
 The application supports a significant number of EEPROM parts. It
 should automatically detect your part. If it does not recognize your
 chip, make sure that you do not have a write protect jumper set --
-this jumper will cause the ROM chip type to be unrecognized.
+this jumper can prevent the ROM chip from being recognized.
 
 Reprogramming a ROM chip in-place is inherently dangerous. If anything
 goes wrong, you will be left with a non-functional system and no
@@ -557,12 +557,17 @@ GitHub repository](https://github.com/willsowerbutts/flash4).
 
 # FDISK80
 
-RomWBW supports disk media with MS-DOS FAT filesystems (see FAT
-application). If you wish to put a FAT filesystem on your media, the
-FDISK80 application can be used to partition your media which is
-required in order to add a FAT filesystem.
+`FDISK80` allows you to create and manage traditional partitions on
+your hard disk media.  Depending on the hard disk format and features
+you are using, RomWBW may need hard disk partitions defined.
 
-This application is provided by John Coffman.
+Please refer to the $doc_user$ for more information on the use of
+partitions within RomWBW.  It is very important to understand that
+RomWBW slices are completely different from disk partitions.
+
+This application is provided by John Coffman.  The primary
+documentation is in the file "FDisk Manual.pdf" found in the
+Doc directory of the RomWBW distribution.
 
 ## Usage
 
@@ -577,20 +582,15 @@ applications. Please refer to the file called "FDisk Manual.pdf" in
 the Doc directory of the RomWBW distribution for further instructions.
 
 There is also more information on using FAT partitions with RomWBW in
-the "RomWBW Getting Started.pdf" document in the Doc directory of the
-distribution.
+the $doc_user$ document in the Doc directory of the distribution.
 
 ## Notes
 
-Partitioning of RomWBW media is **only** required if you want to add a
-FAT filesystem to your media. Do not partition your media if you are
-simply using it for RomWBW. To be clear, RomWBW slices do not require
-partitioning.
-
-As described in "RomWBW Getting Started.pdf", you should be careful
-when adding a FAT partition to your media that the partition does not
-overlap with the area of the media being used for RomWBW slices. The
-"(R)eserve" function in `FDISK80` can help prevent this.
+Hard disk partition tables allow a maximum of 1024 cylinders when
+defining partitions.  However, RomWBW uses exclusively Logical Block
+Addressing (LBA) which does not have this limitation.  When defining
+partitions is usually best to define the start and size of of the
+partition using bytes or sectors.
 
 ## Etymology
 
@@ -661,7 +661,7 @@ After startup, the application provides the following options:
 | `R)aw`      | will read the minute/second of the RTC clock iteratively every time the space key is pressed.  Press enter to end. |
 | `L)oop`     | will read the full date/time of the RTC clock iteratively every time the space key is pressed.  Press enter to end. |
 | `C)harge`   | will enable the battery charging function of the RTC.  |
-| `N)ocharge` | will disable the battery charging functino of the RTC. |
+| `N)ocharge` | will disable the battery charging function of the RTC. |
 | `D)elay`    | allows you to test the built-in timing delay in the program.  It is not unusual for it to be wrong. |
 | `I)nit`     | allows you to enter a date/time value for subsequent programming of the RTC using the S)et option. |
 | `G)et`      | allows you to read the value of a non-volatile register in the RTC. |
@@ -683,7 +683,7 @@ bypassing HBIOS.
 
 ## Etymology
 
-The `RTC` application was originally written by Andrew Lync as part of
+The `RTC` application was originally written by Andrew Lynch as part of
 the original ECB SBC board development.  It has since been modified to
 support most of the hardware variations included with RomWBW.
 
@@ -922,7 +922,7 @@ for the hardware found. If no hardware is detected, it will abort with
 an error message.
 
 On Z180 systems, I/O wait states are added when writing to the sound
-chip to avoid exceeding it's speed limitations. On Z80 systems, you
+chip to avoid exceeding its speed limitations. On Z80 systems, you
 will need to ensure that the CPU clock speed of your system does not
 exceed the timing limitations of your sound chip.
 
@@ -939,7 +939,7 @@ By default the application will attempt to interface directly to the sound
 chip.  The optional argument `--hbios` supplied after the filename, will
 enable the application to use the HBIOS sound driver.
 
-The HBIOS mode also support other switch as desribed below.
+The HBIOS mode also support other switch as described below.
 
 | Switch      | Description                                            |
 | ----------- | ------------------------------------------------------ |
@@ -1012,9 +1012,9 @@ speed will actually work on the current hardware.  Setting a CPU
 speed that exceeds the capabilities of the system will result in
 unstable operation or a system stall.
 
-Some peripherals are dependant on the CPU speed.  For example, the Z180
+Some peripherals are dependent on the CPU speed.  For example, the Z180
 ASCI baud rate and system timer are derived from the CPU speed.  The
-CPUSPD applicastion will attempt to adjust these peripherals for
+CPUSPD application will attempt to adjust these peripherals for
 correct operation after modifying the CPU speed.  However, in some
 cases this may not be possible.  The baud rate of ASCI ports have a
 limited set of divisors.  If there is no satisfactory divisor to
@@ -1028,3 +1028,81 @@ hardware interface code is specific to RomWBW and the application will
 not operate correctly on non-RomWBW systems.
 
 The source code is provided in the RomWBW distribution.
+
+
+`\clearpage`{=latex}
+
+# VGMPLAY
+
+This application will allow you to play Video Game Music files. VGM 
+files contain music samples from a range of different sound chips 
+that were used in arcade games, game consoles and personal computer 
+systems.
+
+Video Game Music files have a .VGM file extension and each file 
+contains an embedded header that identifies the hardware it is 
+intended for and also the title of the music.
+
+All RomWBW operating system boot disks include a selection of sound
+files in user area 3. Additional music files can be found at:
+
+[VGMRIPS website](https://vgmrips.net)
+
+[PROJECT2612 website](https://project2612.org/)
+
+Sound files are loaded into memory for playback, so the maximum size
+file that can be played is around 52Kb.
+
+Sound chips currently supported are:
+
+* AY-3-8190 (and equivalent YM2149)
+* YM2612 (and equivalent YM3848)
+* SN76489 (single chip mono and dual chip stereo)
+* YM2151 
+
+VGMPLAY supports playback of files with multiple combinations of these
+chips.
+
+## Syntax
+
+`VGMPLAY `*`<filename>`*
+
+*`<filename>`* is the name of a sound file ending in .VGM
+
+## Usage
+
+VGMPLAY does not automatically detect the hardware platform or sound
+hardware that you are using. This means a version customized for your
+system must be assembled before use.
+
+To play a sound file, just use the VGMPLAY command and specify the file
+to play after the command. So, for example, `VGMPLAY TEDDY` will load
+the TEDDY.VGM sound file into memory and begin playing it.
+
+Playback can be stopped by pressing a key. There may be a delay before
+playback stops.
+
+## Notes
+
+The default build configuration for VGMPLAY is:
+
+CPU speed: Autodetected
+
+| chip      | number  | port     | notes
+| --------- | ------- | -------- | ----------
+| AY-3-8910 |  1st    | 09ah     | stereo
+| AY-3-8910 |  2nd    | not set  | stereo
+| YM2612    |  1st    | 0c0h     | stereo
+| YM2612    |  2nd    | 0c4h     | stereo
+| SN76489   |  1st    | 0c8h     | mono/left
+| SN76489   |  2nd    | 0c9h     | mono/right
+| YM2151    |  1st    | 0cah     | stereo
+| YM2151    |  2nd    | 0cbh     | stereo
+
+Inconsistant, garbled or distorted playback can be an indication that
+your CPU clock speed is too high for your sound chip. In this case, if 
+your platform supports speed switching, then the CPUSPD application 
+can be used to reduce your processor speed.
+
+VGMPLAY is still under development. The source code is provided in the 
+RomWBW distribution.

Source/Doc/Basic.h

@@ -1,4 +1,4 @@
-$define{doc_ver}{Version 3.2}$
+$define{doc_ver}{Version 3.3}$
 $define{doc_product}{RomWBW}$
 $define{doc_root}{https://github.com/wwarthen/RomWBW/raw/dev/Doc}$
 $ifndef{doc_title}$ $define{doc_title}{Document Title}$ $endif$

Source/Doc/Book.h

@@ -11,12 +11,13 @@ toc-depth: 2
 numbersections: true
 secnumdepth: 2
 header-includes:
-- \setlength{\headheight}{15pt}
 - |
   ```{=latex}
+  \setlength{\headheight}{15pt}
   \usepackage{fancyhdr}
   \usepackage{xcolor}
   \usepackage{xhfill}
+  \usepackage{tocloft}
   \renewcommand*{\familydefault}{\sfdefault}
   \renewcommand{\maketitle}{
     \begin{titlepage}
@@ -44,6 +45,7 @@ include-before:
   ```{=latex}
   \pagestyle{fancyplain}
   \fancyhf{}
+  \lhead{\fancyplain{}{\nouppercase{\bfseries \leftmark \hfill $doc_product$  $doc_title$}}}
   \lfoot{\small RetroBrew Computing Group ~~ {\xrfill[3pt]{1pt}[cyan]} ~~ \thepage}
   \pagenumbering{roman}
   ```
@@ -52,5 +54,4 @@ include-before:
 ```{=latex}
 \clearpage
 \pagenumbering{arabic}
-\lhead{\fancyplain{}{\nouppercase{\bfseries \leftmark \hfill $doc_product$  $doc_title$}}}
 ```

Source/Doc/ROM_Applications.md

@@ -246,7 +246,7 @@ memory starting at location xxxx.
 protocol.
 
 If the monitor is assembled with the DSKY functionality,
-this feature will be exclude due to space limitions.
+this feature will be exclude due to space limitations.
 
 
 ## NOTES:
@@ -624,7 +624,7 @@ Feedback to the ROMWBW developers on these guidelines would be appreciated.
 
 ## Notes:
 All testing was done with Teraterm x-modem, Forcing checksum mode using macros was found to give  the most reliable transfer.
-Partial writes can be completed with 39SF040 chips. Other chips require entire flash to be erased before before being written.
+Partial writes can be completed with 39SF040 chips. Other chips require entire flash to be erased before being written.
 An SBC V2-005 MegaFlash or Z80 MBC required for 1mb flash support. The Updater assumes both chips are same type
 Failure handling has not been tested.
 Timing broadly calibrated on a Z80 SBC-v2

Source/Doc/ReadMe.md

@@ -117,7 +117,7 @@ please let me know if I missed you!
 
 * Andrew Lynch started it all when he created the N8VEM Z80 SBC
   which became the first platform RomWBW supported.  Some of his
-  code can still be found in RomWBW.
+  original code can still be found in RomWBW.
 
 * Dan Werner wrote much of the code from which RomWBW was originally
   derived and he has always been a great source of knowledge and
@@ -129,23 +129,30 @@ please let me know if I missed you!
   due  to internal changes within RomWBW. As of RomWBW 2.6, these
   applications are no longer provided.
 
+* Sergey Kiselev created several hardware platforms for RomWBW
+  including the very popular Zeta.
+
 * David Giles created support for the Z180 CSIO which is now included
   SD Card driver.
 
+* Phil Summers contributed the Forth and BASIC adaptations in ROM, the
+  AY-3-8910 sound driver, DMA support, and a long list of general code
+  and documentation enhancements.
+
 * Ed Brindley contributed some of the code that supports the RCBus
   platform.
 
-* Phil Summers contributed the Forth and BASIC adaptations in ROM, the
-  AY-3-8910 sound driver as well as a long list of general code
-  enhancements.
-
 * Spencer Owen created the RC2014 series of hobbyist kit computers
-  which has exponentially increased RomWBW usage.
+  which has exponentially increased RomWBW usage.  Some of his kits
+  include RomWBW.
 
 * Stephen Cousins has likewise created a series of hobbyist kit
   computers at Small Computer Central and is distributing RomWBW
   with many of them.
 
+* Alan Cox has contributed some driver code and has provided a great
+  deal of advice.
+
 * The CP/NET client files were developed by Douglas Miller.
 
 * Phillip Stevens contributed support for FreeRTOS.
@@ -186,15 +193,15 @@ Portions of RomWBW were created by, contributed by, or derived from
 the work of others.  It is believed that these works are being used
 in accordance with the intentions and/or licensing of their creators.
 
-If anyone feels their work is being used outside of it's intended
+If anyone feels their work is being used outside of its intended
 licensing, please notify:
 
-> Wayne Warthen
-> wwarthen@gmail.com
+> $doc_author$ \
+> [$doc_authmail$](mailto:$doc_authmail$)
 
 RomWBW is an aggregate work.  It is composed of many individual,
 standalone programs that are distributed as a whole to function as
-a cohesive system.  Each program may have it's own licensing which
+a cohesive system.  Each program may have its own licensing which
 may be different from other programs within the aggregate.
 
 In some cases, a single program (e.g., CP/M Operating System) is

Source/Doc/SystemGuide.md

@@ -182,7 +182,7 @@ not know anything about what is being loaded (the image is usually an
 operating system, but could be any executable code image). Once the Boot
 Loader has loaded the image at the selected location, it will transfer
 control to it. Assuming the typical situation where the image was an
-operating system, the loaded operating system will then perform it's own
+operating system, the loaded operating system will then perform its own
 initialization and begin normal operation.
 
 ## Application Boot
@@ -207,8 +207,8 @@ the previously running operating system starting at $0100. Note that the
 program image contains a full copy of the HBIOS to be installed and run. Once
 the Application Boot program is loaded by the previous operating system,
 control is passed to it and it performs a system initialization similar
-to the ROM Boot, but using the image loaded in RAM.  Once te new
-HBIOS completes it's initialization, it will launch the Boot Loader
+to the ROM Boot, but using the image loaded in RAM.  Once the new
+HBIOS completes its initialization, it will launch the Boot Loader
 just like a ROM boot.
 
 The Application Boot program actually contains two other components
@@ -228,7 +228,7 @@ they have a small hardware bootstrap that loads a chunk of code from a
 disk device directly into RAM at system startup.
 
 The startup then proceeds very much like the Application Boot
-process described above.  HBIOS is installed in it's operating bank
+process described above.  HBIOS is installed in its operating bank
 and control is passed to the Boot Loader.
 
 # Driver Model
@@ -245,7 +245,7 @@ layout expected by the operating system and application.
 Drivers do need to be aware of the bank switching if a buffer address
 is being used in the function call.
 
-* If the buffer address is in the lower 32K of RAM, then the memroy
+* If the buffer address is in the lower 32K of RAM, then the memory
   it points to will be from the User Bank, not the HBIOS bank which
   is now active.  In this case, the driver must use an inter-bank
   copy to access the data.
@@ -363,7 +363,7 @@ HBIOS functions. Most function calls will return a result in register A.
 | -1       | undefined error                        |
 | -2       | function not implemented               |
 | -3       | invalid function                       |
-| -4       | invalid unit numberr                   |
+| -4       | invalid unit number                    |
 | -5       | out of memory                          |
 | -6       | parameter out of range                 |
 | -7       | media not present                      |
@@ -617,7 +617,7 @@ Returns the driver specific Status (A) of the specified disk device unit
 The return value in register A is used as both a device status and a 
 standard HBIOS result code. Negative values (bit 7 set) indicate a 
 standard HBIOS result (error) code.  Otherwise, the return value 
-represents a driver-specific device status.  In call cases, the value 0 
+represents a driver-specific device status.  In all cases, the value 0 
 means OK.
 
 ### Function 0x11 -- Disk Reset (DIORESET)
@@ -1619,7 +1619,7 @@ Status (A) is a standard HBIOS result code.
 | E: 0x04                                | HL: Ports                              |
 |                                        | DE: Ports                              |
 
-This subfunction reports detailed device informatoin for the specified 
+This subfunction reports detailed device information for the specified 
 Sound Unit (C).
 
 Driver Identity (B) reports the audio device type.  Ports (HL & DE) 
@@ -1652,7 +1652,7 @@ the duration, the actual duration is applied in the SNDPLAY function.
 If the Duration (HL) is set to zero, then the SNDPLAY function will 
 operate in a non-blocking mode. i.e. a tone will start playing and the 
 play function will return. The tone will continue to play until the next
- tone is played.  If the Duration (HL) is greater than zero, the the 
+ tone is played.  If the Duration (HL) is greater than zero, the 
 sound will play for the duration defined in HL and then return.
 
 **\*\*\* Function Not Implemented \*\*\**
@@ -2024,7 +2024,7 @@ lookup.
 
 Return the value of the global system timer Tick Count (DEHL).  This is 
 a double-word binary value.  The frequency of the system timer in Hertz 
-is returned in Frequncy (C). The returned Status (A) is a standard HBIOS
+is returned in Frequency (C). The returned Status (A) is a standard HBIOS
 result code.
 
 Note that not all hardware configuration have a system timer.  You
@@ -2123,6 +2123,17 @@ Wait States (D) is the actual number of wait states, not the number
 of wait states added.  The returned Status (A) is a standard HBIOS 
 result code.
 
+#### SYSGET Subfunction 0xF4 -- Get Front Panel Swithes (PANEL)
+
+| **Entry Parameters**                   | **Returned Values**                    |
+|----------------------------------------|----------------------------------------|
+| B: 0xF8                                | A: Status                              |
+| C: 0xF4                                | L: Switches                            |
+
+This function will return the current value of the switches (L) from the
+front panel of the system.  If no front panel is available in the
+system, the returned Status (A) will indicate a No Hardware error.
+
 ### Function 0xF9 -- System Set (SYSSET)
 
 | **Entry Parameters**                   | **Returned Values**                    |
@@ -2197,7 +2208,7 @@ Wait States (E) will be set if possible.  The value of Memory Wait
 States (D) is the actual number of wait states, not the number of wait 
 states added.
 
-Some peripherals are dependant on the CPU speed.  For example, the Z180
+Some peripherals are dependent on the CPU speed.  For example, the Z180
 ASCI baud rate and system timer are derived from the CPU speed.  The
 Set CPU Speed function will attempt to adjust these peripherals for
 correct operation after modifying the CPU speed.  However, in some
@@ -2206,6 +2217,18 @@ limited set of divisors.  If there is no satisfactory divisor to
 retain the existing baud rate under the new CPU speed, then the baud
 rate of the ASCI port(s) will be affected.
 
+#### SYSSET Subfunction 0xF4 -- Set Front Panel LEDs (PANEL)
+
+| **Entry Parameters**                   | **Returned Values**                    |
+|----------------------------------------|----------------------------------------|
+| B: 0xF8                                | A: Status                              |
+| C: 0xF4                                |                                        |
+| L: LEDs                                |                                        |
+
+This function will set the front panel LEDs based on the bits in L. If 
+no front panel is available in the system, the returned Status (A) will 
+indicate a No Hardware error.
+
 ### Function 0xFA -- System Peek (SYSPEEK)
 
 | **Entry Parameters**                   | **Returned Values**                    |
@@ -2389,7 +2412,7 @@ are not reported to the console.
 
 If the diagnosis level is set to display the diagnosis information, then
 memory address, register dump and error code is displayed.
-A key differance with the PANIC error is that execution may be continued. 
+A key difference with the PANIC error is that execution may be continued. 
 
 Example error message:
 

Source/Doc/UserGuide.md

@@ -133,7 +133,7 @@ contributions are very welcome.
 #### Distribution Directory Layout
 
 The RomWBW distribution is a compressed zip archive file organized in
-a set of directories. Each of these directories has it's own
+a set of directories. Each of these directories has its own
 ReadMe.txt file describing the contents in detail. In summary, these
 directories are:
 
@@ -201,6 +201,7 @@ below, **carefully** pick the appropriate ROM image for your hardware.
 | [Z80 ZRC CPU Module]^7^                                        | RCBus   | RCZ80_zrc.rom      | 115200        |
 | [Z280 ZZRCC CPU Module]^7^                                     | RCBus   | RCZ280_zzrc.rom    | 115200        |
 | [Z280 ZZ80MB SBC]^7^                                           | RCBus   | RCZ280_zz80mb.rom  | 115200        |
+| [Z80-Retro SBC]^8^                                             | -       | Z80RETRO_std.rom   | 38400         |
 
 | ^1^Designed by Andrew Lynch
 | ^2^Designed by Sergey Kiselev
@@ -209,6 +210,7 @@ below, **carefully** pick the appropriate ROM image for your hardware.
 | ^5^Designed by Stephen Cousins
 | ^6^Designed by Steve Garcia
 | ^7^Designed by Bill Shen
+| ^8^Designed by Peter Wilson
 
 RCBus refers to Spencer Owen's RC2014 bus specification and derivatives
 including RC26, RC40, RC80, and BP80.
@@ -405,8 +407,9 @@ to your system that is not automatically identified, you may need
 to build a custom ROM to add support for it.  Building a custom ROM
 is covered later.
 
-[Appendix A - Device Summary] contains a list of the RomWBW hardware devices which may
-help you identify the hardware discovered in your system.
+[Appendix B - Device Summary] contains a list of the RomWBW hardware
+devices which may help you identify the hardware discovered in your
+system.
 
 ## Device Unit Assignments
 
@@ -529,7 +532,7 @@ ROM Applications:
 
 To start a ROM application you just enter the corresponding letter at
 the Boot Loader prompt.  In the following example, we launch the
-built-in Micrsosoft BASIC interpreter.  From within BASIC, we use the
+built-in Microsoft BASIC interpreter.  From within BASIC, we use the
 `BYE` command to return to the Boot Loader:
 
 ```
@@ -620,7 +623,7 @@ Boot [H=Help]: 4
 
 Booting Disk Unit 4, Slice 0, Sector 0x00000800...
 
-Volume "Unlabeled" [0xD000-0xFE00, entry @ 0xE600]...
+Volume "Unlabelled" [0xD000-0xFE00, entry @ 0xE600]...
 
 CBIOS v3.1.1-pre.194 [WBW]
 
@@ -660,7 +663,7 @@ Boot [H=Help]: 4.3
 
 Booting Disk Unit 4, Slice 3, Sector 0x0000C800...
 
-Volume "Unlabeled" [0x0100-0x1000, entry @ 0x0100]...
+Volume "Unlabelled" [0x0100-0x1000, entry @ 0x0100]...
 
 CP/M V3.0 Loader
 Copyright (C) 1998, Caldera Inc.
@@ -720,7 +723,7 @@ The 'R' command within the Boot Loader performs a software reset of
 the system.  It is the software equivalent of pressing the reset
 button.
 
-There is generallhy no need to do this, but it can be convenient when
+There is generally no need to do this, but it can be convenient when
 you want to see the boot messages again or ensure your system is in
 a clean state.
 
@@ -735,7 +738,7 @@ Restarting System...
 Your system can support a number of devices for the console. They may
 be VDU type devices or serial devices. If you want to change which
 device is the console, the ***I*** menu option can be used to choose
-the unit and it's speed.
+the unit and its speed.
 
 The command format is ```I <unit> [<baudrate>]```
 
@@ -781,6 +784,55 @@ The use of diagnostic levels above 4 are really intended only for
 software developers.  I do not recommend changing this under
 normal circumstances.
 
+## Front Panel
+
+RomWBW supports the concept of a simple front panel.  The following 
+image is a conceptual view of such a front panel.  If your system has a 
+front panel, it should look similar to the [RomWBW Front Panel](#panel).
+
+![RomWBW Front Panel](Graphics/Panel){#panel width=50% }
+
+The LEDs in the top row of the panel are used for multiple purposes.
+They are initially used to display the progress of the
+system boot.  This may help in diagnosing a hardware or configuration
+issue in a system that does not progress far enough to display text
+output on the console.  The meaning of the LEDs is:
+
+|            |                              |
+|------------|------------------------------|
+| `O-------` | System Boot has started      |
+| `OO------` | Common RAM bank activated    |
+| `OOO-----` | HBIOS transitioned to RAM    |
+| `OOOO----` | Basic initialization done    |
+| `OOOOO---` | CPU detection complete       |
+| `OOOOOO--` | System timer configured      |
+| `OOOOOOO-` | Pre-console device init done |
+| `OOOOOOOO` | Console activation           |
+
+Once the system has booted, the LEDs are used to indicate disk device
+activity.  Each LED numbered 7-0 represents disk units 7-0.  As each
+disk device performs I/O, the LED will light.
+
+The second row of the front panel is composed of switches that allow
+you to control a few aspects of the system startup.
+
+The first two switches affect the device used as the console initially.
+Setting the CRT/Serial switch will cause the system to boot directly 
+to an attached CRT device (if available).  Setting the Pri/Sec switch 
+will cause the system to boot to the secondary Serial or CRT device 
+(depending on the setting of the first switch).
+
+The final six switches allow you to cause the system to automatically
+boot into a desired function.  The Auto/Menu switch must be set to
+enable this, otherwise the normal ROM Loader prompt will be used.
+If the Disk/ROM switch is not set, then you can use the last 3
+switches to select a ROM app to auto-start.  If the Disk/ROM switch is
+set, then the system will attempt a disk boot based on the following
+switches.  The Floppy/Hard switch can be used to boot to a Floppy or
+Hard Disk.  In either case, the first Floppy or Hard Disk will be used
+for the boot.  If a Hard Disk boot is selected, then the last three
+switches can be used to select any of the first 8 slices.
+
 # Disk Management
 
 The systems supported by RomWBW all have the ability to use persistent
@@ -823,11 +875,11 @@ The messages you see will vary depending on your hardware and the
 media you have installed. But, they will all have the same general
 format as the example above.
 
-Once your your system has working disk devices, they will be accessible
+Once your system has working disk devices, they will be accessible
 from any operating system you choose to run.  Disk storage is available
 whether you boot your OS from ROM or from the disk media itself.
 
-Refering back to the Boot Loader section on "Launching from ROM", you
+Referring back to the Boot Loader section on "Launching from ROM", you
 could start CP/M 2.2 using the 'C' command.  As the operating system
 starts up, you should see a list of drive letters assigned to the disk
 media you have installed. Here is an example of this:
@@ -1071,7 +1123,7 @@ PROGRESS: TRACK=4F HEAD=01 SECTOR=01
 ```
 
 Since the physical format of floppy media is the same as that used
-in a standard MS-DOS/Windows computer, you can also physicall format
+in a standard MS-DOS/Windows computer, you can also physical format
 floppy media in a modern computer.  However, the directory format
 itself will not be compatible with CP/M OSes.  In this case, you
 can use the `CLRDIR` application supplied with RomWBW to reformat
@@ -1091,7 +1143,7 @@ after inserting a new floppy disk.
 
 Under RomWBW, a hard disk is similar to a floppy disk in that it is
 considered a disk unit.  However, RomWBW has multiple features that
-allow it's legacy operating systems to take advantage of modern
+allow its legacy operating systems to take advantage of modern
 mass storage media.
 
 To start with, the concept of a hard disk in RomWBW applies to any
@@ -1340,7 +1392,7 @@ B>stat e:dsk:
 ```
 
 It is critical that you include "dsk:" after the drive letter in the
-`STAT` command line.  The important line to look at is labeled "32 Byte
+`STAT` command line.  The important line to look at is labelled "32 Byte
 Directory Entries".  In this case, the value is 1024 which implies that
 this drive is located on a modern (hd1k) disk layout.  If the value
 was 512, it would indicate a legacy (hd512) disk layout.
@@ -1366,7 +1418,7 @@ Essentially, this means you are creating a set of blank directories on
 your disk so that files can be saved there.  This process is described
 below under Disk Initialization. In this scenario, you will need to
 subsequently copy any files you want to use onto the newly initialized
-disk (see Transferring Files).
+disk (see [Transferring Files]).
 
 You will notice that in the following instructions there is no mention
 of specific hardware.  Because the RomWBW firmware provides a 
@@ -1402,6 +1454,7 @@ The following table shows the disk images available.
 | xxx_cpm3.img    | DRI CP/M 3 Operating System            | Yes      |
 | xxx_zpm3.img    | ZPM3 Operating System                  | Yes      |
 | xxx_qpm.img     | QPM Operating System                   | Yes      |
+| xxx_dos65.img   | DOS/65 Operating System                | Yes      |
 | xxx_ws4.img     | WordStar v4 & ZDE Applications         | No       |
 
 You will find 3 sets of these .img files in the distribution.  The
@@ -1411,8 +1464,8 @@ layout hard disk image.
 
 There is also an image file called "psys.img" which contains a bootable 
 p-System hard disk image.  It contains 6 p-System filesystem slices, but
- these are not interoperable with the CP/M slices described above.  This
- file is discussed separately under p-System in the Operating Systems 
+these are not interoperable with the CP/M slices described above.  This
+file is discussed separately under p-System in the [Operating Systems] 
 section.
 
 ### Floppy Disk Images
@@ -1462,7 +1515,7 @@ hard disk image with the specific slice contents you choose.
 #### Combo Hard Disk Image
 
 The combo disk image is essentially just a single image that has several
- of the individual filesystem images already concatenated together. The 
+of the individual filesystem images already concatenated together. The 
 combo disk image contains the following 6 slices in the positions 
 indicated:
 
@@ -1516,6 +1569,9 @@ In all of the examples above, the resulting file (hd.img) would now be
 written to your hard disk media and would be ready to use in a RomWBW 
 system.
 
+If you wish to further customize or create new disk image definitions,
+please refer to the ReadMe.txt file in the Source/Images directory.
+
 #### Writing Hard Disk Images
 
 Once you have chosen a combo hard disk image file or prepared your own 
@@ -1539,7 +1595,7 @@ image that you write to your hard disk media.  You can use additional
 slices as long your media has room for them.  However, writing the disk 
 image will not initialize the additional slices.  If these additional 
 slices were previously initialized, they will not be corrupted when you 
-write the new image and will still contain their prvious contents.  If 
+write the new image and will still contain their previous contents.  If 
 the additional slices were not previously initialized, you can use 
 `CLRDIR` to do so and optionally `SYSCOPY` if you want them to be 
 bootable.
@@ -1770,7 +1826,7 @@ less likely to encounter compatibility issues.
 
 #### Boot Disk
 
-To make make a bootable CP/M disk, use the RomWBW `SYSCOPY` tool
+To make a bootable CP/M disk, use the RomWBW `SYSCOPY` tool
 to place a copy of the operating system on the boot track of
 the disk.  The RomWBW ROM disk has a copy of the boot track
 call "CPM.SYS".  For example:
@@ -1786,7 +1842,7 @@ call "CPM.SYS".  For example:
 
 * `SUBMIT.COM` has been patched per DRI to always place submit
   files on A:.  This ensures the submitted file will always be
-  properlly executed.
+  properly executed.
 
 * The original versions of DDT, DDTZ, and ZSID used the RST 38
   vector which conflicts with interrupt mode 1 use of this vector.
@@ -1818,7 +1874,7 @@ via the NZ-COM adaptation (see below).
 
 #### Boot Disk
 
-To make make a bootable Z-System disk, use the RomWBW `SYSCOPY` tool
+To make a bootable Z-System disk, use the RomWBW `SYSCOPY` tool
 to place a copy of the operating system on the boot track of
 the disk.  The RomWBW ROM disk has a copy of the boot track
 call "ZSYS.SYS".  For example:
@@ -1896,7 +1952,7 @@ configured in the most basic way possible.  You should refer to the
 documentation and use `MKZCM` as desired to customize your system.
 
 NZCOM has substantially more functionality than CP/M or basic
-Z-System.  It is important to read the the "NZCOM Users
+Z-System.  It is important to read the "NZCOM Users
 Manual.pdf" document in order to use this operating system effectively.
 
 #### Documentation
@@ -1933,29 +1989,48 @@ has a new suite of support tools and help system.
 
 #### Boot Disk
 
-To make a CP/M 3 boot disk, you actually place CPMLDR.SYS
-on the system tracks of the disk. You do not place CPM3.SYS on the
-system tracks.  `CPMLDR.SYS` chain loads `CPM3.SYS` which must
-exist as a file on the disk.
-  
-CP/M 3 uses a multi-step boot process involving multiple files.
+To create (or update) a CP/M 3 boot drive, you must place `CPMLDR.SYS` on
+the system track of the disk.  You must also place `CPM3.SYS` and 
+`CCP.COM` on the target drive as regular files.  Do **not** place 
+CPM3.SYS on the boot track.  `CPMLDR.SYS` chain loads `CPM3.SYS` which 
+must exist as a regular file on the disk.  Subsequently, `CPM3.SYS` 
+loads `CCP.COM`.
+
 The CP/M 3 boot files are not included on the ROM disk due to
-space constraints.  You will need to transfer the files to your
-system from the RomWBW distribution directory Binary\\CPM3.
+space constraints.  You will need to transfer the following files to
+your system from the RomWBW distribution directory Binary/CPM3.  You
+can use XModem for this (or any of the mechanisms in [Transferring
+Files].
 
-After this is done, you will need to use `SYSCOPY` to place
-the CP/M 3 loader image on the boot tracks of all CP/M 3
-boot disks/slices.  The loader image is called `CPMLDR.SYS`.
-You must then copy (at a minimum) `CPM3.SYS` and `CCP.COM`
-onto the disk/slice.  Assuming you copied the CP/M 3 boot files
-onto your RAM disk at A:, you would use:
+- `CPMLDR.SYS`
+- `CPM3.SYS` or `CPM3BNK.SYS`
+- `CCP.COM`
+
+The `CPM3.SYS` boot file is provided in 2 versions.  In the Binary/CPM3 
+distribution directory, `CPM3.SYS` is the "non-banked" version of
+CP/M 3.  The `CPM3BNK.SYS` file is the "banked" version of CP/M 3.  You 
+almost certainly want to transfer the banked `CPM3BNK.SYS` version.
+
+After transferring the boot files to your RomWBW system, you will
+need to use `SYSCOPY` to place `CPMLDR.SYS` on the boot track of the
+target drive.  `CPM3.SYS` and `CCP.COM` can be copied to the target
+drive using any standard file copy tool such as `PIP` or `COPY`.
+
+You do not need to be booted into CP/M 3 to create or update a CP/M 3 
+disk.  The recommended approach is to boot CP/M 2.2 or Z-System from 
+ROM.  Transfer the boot files to the RAM disk.  Then simply copy the 
+files onto the CP/M 3 disk.  Assuming the target CP/M 3 disk is F:, you 
+can use the following commands to place the files on the target drive:
 
 ```
-SYSCOPY C:=CPMLDR.SYS
-PIP C:=CPM3.SYS
-PIP C:=CCP.COM
+SYSCOPY F:=A:CPMLDR.SYS
+COPY A:CPM3BNK.SYS F:CPM3.SYS
+COPY A:CCP.COM F:
 ```
 
+Note in the example above that `CPM3BNK.SYS` is renamed to `CPM3.SYS`
+in the copy command.
+
 #### Notes
 
 - The `COPYSYS` command described in the DRI CP/M 3 documentation is
@@ -1968,16 +2043,29 @@ PIP C:=CCP.COM
   program   of CP/M 3 is completely different/incompatible from the
   `SUBMIT` program of CP/M 2.2.
 
-* RomWBW fully suppoerts CP/M 3 file date/time stamping, but this 
+- RomWBW fully supports CP/M 3 file date/time stamping, but this 
   requires that the disk be properly initialized for it.  This process 
   has not been performed on the CP/M 3 disk image.  Follow the 
-  CP/M 3 documentation to complete this process.
+  CP/M 3 documentation to complete this process, if desired.
 
-## Simeon Cran's ZPM3
+## ZPM3
 
-ZPM3 is an interesting combination of the features of both CP/M 3 and
-ZCPR 3. Essentially, it has the features of and compatibility with
-both.
+Simeon Cran's ZPM3 is an interesting combination of the features of both
+CP/M 3 and ZCPR3. Essentially, it has the features of and 
+compatibility with both.
+
+Due to this dual compatibility, the ZPM3 distribution image contains 
+most of the standard CP/M 3 files as well as a variety of common ZCPR3 
+applications.  However, you will notice that user area 0 of the disk has
+only a few files.  Most of the files are distributed among other user 
+areas which is standard practice for ZCPR3.  Most importantly, you will 
+see most of the applications in user area 15.  The applications can be 
+executed from any user area because ZPM3 has a default search path that 
+includes User 15.
+
+The ZPM3 distribution comes with essentially no utility programs at
+all.  In addition to the standard CP/M 3 utilities, RomWBW includes
+a variety of common ZCPR3 utilities.
 
 #### Documentation
 
@@ -1986,31 +2074,55 @@ CP/M 3 and ZCPR 3.
 
 #### Boot Disk
 
-ZPM3 uses a multi-step boot process involving multiple files. The ZPM3 
-boot files are not included on the ROM disk due to space constraints.  
-You will need to transfer the files to your system from the RomWBW 
-distribution directory Binary\\ZPM3.
+To create (or update) a ZPM3 boot drive, you must place `ZPMLDR.SYS` on 
+the system track of the disk.  You must also place `CPM3.SYS`, 
+`ZCCP.COM`, `ZINSTAL.ZPM`, and `STARTZPM.COM` on the target drive as 
+regular files.  Do **not** place CPM3.SYS on the boot track.  
+`ZPMLDR.SYS` chain loads `CPM3.SYS` which must exist as a regular file 
+on the disk.  Subsequently, `CPM3.SYS` loads `CCP.COM`.
 
-After this is done, you will need to use `SYSCOPY` to place the ZPM3 
-loader image on the boot tracks of the disk. The loader image is called 
-`ZPMLDR.SYS`. You must then copy (at a minimum) `CPM3.SYS`, `ZCCP.COM`, 
-`ZINSTAL.ZPM`, and `STARTZPM.COM` onto the disk/slice. Assuming you 
-copied the ZPM3 boot files onto your RAM disk at A:, you would use:
+The CP/M 3 boot files are not included on the ROM disk due to space 
+constraints.  You will need to transfer the following files to your 
+system from the RomWBW distribution directory Binary/ZPM3.  You can use 
+XModem for this (or any of the mechanisms in [Transferring Files].
+
+- `ZPMLDR.SYS`
+- `CPM3.SYS`
+- `ZCCP.COM`
+- `ZINSTAL.ZPM`
+- `STARTZPM.COM`
+
+You may be surprised to see the file called `CPM3.SYS`.  This is not a 
+typo. Although it is called `CPM3.SYS`, it is ZPM and not the same as 
+`CPM3.SYS` in the CPM3 directory.  Also, unlike CP/M 3, ZPM3 is always 
+banked, so you will not find two versions of the file.  `CPM3.SYS` is a 
+banked implementation of ZPM3.
+
+After transferring the boot files to your RomWBW system, you will
+need to use `SYSCOPY` to place `ZPMLDR.SYS` on the boot track of the
+target drive.  The remaining boot files can be copied to the target
+drive using any standard file copy tool such as `PIP` or `COPY`.
+
+You do not need to be booted into ZPM3 to create or update a ZPM3 
+disk.  The recommended approach is to boot CP/M 2.2 or Z-System from 
+ROM.  Transfer the boot files to the RAM disk.  Then simply copy the 
+files onto the ZPM disk.  Assuming the target ZPM3 disk is F:, you 
+can use the following commands to place the files on the target drive:
 
 ```
-A>B:SYSCOPY C:=ZPMLDR.SYS
-A>B:COPY CPM3.SYS C:
-A>B:COPY ZCCP.COM C:
-A>B:COPY ZINSTAL.ZPM C:
-A>B:COPY STARTZPM.COM C:
+SYSCOPY F:=A:ZPMLDR.SYS
+COPY A:CPM3.SYS F:CPM3.SYS
+COPY A:CCP.COM F:
+COPY A:ZINSTAL.ZPM F:
+COPY A:STARTZPM.COM F:
 ```
 
 #### Notes
 
-* The ZPM operating system is contained in the file called CPM3.SYS
+- The ZPM3 operating system is contained in the file called CPM3.SYS 
   which is confusing, but this is as intended by the ZPM3 distribution.
-  I believe it was done this way to make it easier for users to transition
-  from CP/M 3 to ZPM3.
+  I believe it was done this way to make it easier for users to
+  transition from CP/M 3 to ZPM3.
 
 ## QP/M
 
@@ -2029,18 +2141,27 @@ regarding the RomWBW adaptation and customizations.
 #### Boot Disk
 
 There is no RomWBW-specific boot disk creation procedure.  QP/M
-comes with a QINSTALL tool for this purpose.  You can use the
-tool if you want to perform a fresh installation.
+comes with a QINSTALL which is used to install QPM over an existing
+CP/M 2 installation or to update an existing QPM disk.  `QINSTALL.COM`
+is included with the RomWBW distribution.
 
 #### Notes
 
-* QPM is not available as source.  This implementation was based
+- QPM is not available as source.  This implementation was based
   on the QPM binary distribution and has been minimally customized
   for RomWBW.
- 
-* QINSTALL is used to customize QPM.  It is included on the
+
+- QINSTALL is used to customize QPM.  It is included on the
   disk image.  You should review the notes in the ReadMe.txt
-  file in Source/Image/d_qpm before making changes.
+  file in Source/Images/d_qpm before making changes.
+
+- In addition to the QPM disk image, all of the QPM distribution
+  files can be found in the RomWBW distribution in the
+  Source/Images/d_qpm/u0 directory.
+
+- The QPM disk image is not included as one of the slices on the
+  RomWBW combo disk image.  If you want to include QPM, you can do
+  so by following the directions in Source/Images/Readme.txt.
 
 ## UCSD p-System
 
@@ -2053,7 +2174,7 @@ some other distributions, this implements a native p-System
 Z80 Extended BIOS, it does not rely on a CP/M BIOS layer.
 
 The p-System is provided on a hard disk image file called
-psys.img.  This must be copied to it's own dedicated hard
+psys.img.  This must be copied to its own dedicated hard
 disk media (CF Card, SD Card, etc.).  It is booted by
 selecting slice 0 of the corresponding hard disk unit at
 the RomWBW Boot Loader prompt.  Do not attempt to use
@@ -2153,7 +2274,7 @@ therefore, globally available.
 | CPUSPD          | Change the running CPU speed and wait states of the system.                                          |
 
 Some custom applications do not fit on the ROM disk. They are found on the
-disk image files or the individual files can be found in the Binary\\Apps
+disk image files or the individual files can be found in the Binary/Apps
 directory of the distribution.
 
 | **Application** | **Description**                                                    |
@@ -2207,7 +2328,7 @@ default FAT partition.
 You can confirm the existence of the FAT partition with `FDISK80` by 
 using the 'P' command to show the current partition table.  Here is an 
 example of a partition table listing from `FDISK80` that includes the 
-FAT partition (labeled "FAT16"):
+FAT partition (labelled "FAT16"):
 
 ```
 Capacity of disk 4:  (  4G)  7813120      Geom 77381010
@@ -2221,7 +2342,7 @@ Nr  ---Type- A --      Start         End   LBA start  LBA count  Size
 If your hard disk media does not have a FAT partition already defined,
 you will need to define one using FDISK80 by using the 'N' command.
 Ensure that the location and size of the FAT partition does not
-overlap any of the CP/M slice area and that it fits within the szie
+overlap any of the CP/M slice area and that it fits within the size
 of your media.
 
 Once the partition is defined, you will still need to format it.  Just
@@ -2246,7 +2367,7 @@ If your RomWBW system has multiple disk drives/slots, you can also just
 create a disk with your modern computer that is a dedicated FAT 
 filesystem disk.  You can use your modern computer to format the disk 
 (floppy, CF Card, SD Card, etc.), then insert the disk in your RomWBW 
-computer and access if using `FAT` based on it's RomWBW unit number.
+computer and access if using `FAT` based on its RomWBW unit number.
 
 ## FAT Application Usage
 
@@ -2334,7 +2455,7 @@ Copying...
 SAMPLE.TXT ==> 4:/SAMPLE.TXT Overwrite? (Y/N) ... [OK]
 SAMPLE2.TXT ==> 4:/SAMPLE2.TXT ... [OK]
 
-    2 File(s) Copiedd
+    2 File(s) Copied
 ```
 
 # CP/NET Networking
@@ -2719,7 +2840,7 @@ usage documents.
 Note that the build scripts for RomWBW create the default disk images
 supplied with RomWBW. It is relatively easy to customize the contents
 of the disk images that are part of RomWBW. This is described in more
-detail in the Source\\Images directory of the distribution.
+detail in the Source/Images directory of the distribution.
 
 ## FAT Filesystem Transfers
 
@@ -2779,7 +2900,7 @@ boot. To customize this file, you use the ZCPR ALIAS facility. You
 will need to refer to ZCPR documentation for more information on the
 ALIAS facility.
 
-p-System has it's own startup command processing mechanism that is
+p-System has its own startup command processing mechanism that is
 covered in the p-System documentation.
 
 ## ROM Customization
@@ -2815,7 +2936,7 @@ built into the ROM.
 # UNA Hardware BIOS
 
 John Coffman has produced a new generation of hardware BIOS called
-UNA. The standard RomWBW distribution includes it's own hardware
+UNA. The standard RomWBW distribution includes its own hardware
 BIOS. However, RomWBW can alternatively be constructed with UNA as
 the hardware BIOS portion of the ROM. If you wish to use the UNA
 variant of RomWBW, then just program your ROM with the ROM image
@@ -2845,6 +2966,31 @@ Please refer to the
 [UNA BIOS Firmware Page](https://www.retrobrewcomputers.org/doku.php?id=software:firmwareos:una:start)
 for more information on UNA.
 
+## UNA Usage Notes
+
+- At startup, UNA will display a prompt similar to this:
+
+  `Boot UNA unit number or ROM? [R,X,0..3] (R):`
+
+  You generally want to choose 'R' which will then launch the RomWBW
+  loader.  Attempting to boot from a disk using a number at the UNA
+  prompt will only work for the legacy (hd512) disk format.  However,
+  if you go to the RomWBW loader, you will be able to perform a disk
+  boot on either disk format.
+
+- The disk images created and distributed with RomWBW do not have the
+  correct system track code for UNA.  In order to boot to disk under
+  UNA, you must first use SYSCOPY to update the system track of the
+  target disk.  The UNA ROM disk has the correct system track files
+  for UNA: `CPM.SYS` and `ZSYS.SYS`.  So, you can boot a ROM OS and
+  then use one of these files to update the system track.
+
+- Only Z-System and CP/M 2 are available OSes under UNA at this time.
+  Since NZ-COM launches from CP/M 2, it is usable.  p-System is not
+  usable under UNA.
+
+- Some of the RomWBW-specific applications are not UNA compatible.
+
 # Upgrading
 
 Upgrading to a newer release of RomWBW is essentially just a matter of
@@ -2915,7 +3061,7 @@ occurred.
 
 Similar to using the Flash utility, the system ROM can be updated
 or upgraded through the ROM based updater utility. This works by
-by reprogrammed the flash ROM as the file is being transfered.
+by reprogrammed the flash ROM as the file is being transferred.
 
 This has the advantage that secondary storage is not required to
 hold the new image.
@@ -2937,7 +3083,7 @@ firmware, you are likely to have odd problems.
 
 The simplest way to update your disk media is to just use your modern
 computer to overwrite the entire media with the latest disk image of
-your choice. This process is described below in the Disk Images
+your choice. This process is described below in the [Disk Images]
 section. If you wish to update existing disk media in your system, you
 need to perform the following steps.
 
@@ -2953,7 +3099,7 @@ them over any older versions of the app on your disk:
 * ASSIGN.COM
 * SYSCOPY.COM
 * MODE.COM
-* FDU.COM (was FDTST.COM)
+* FDU.COM
 * FORMAT.COM
 * XM.COM
 * FLASH.COM
@@ -2961,14 +3107,13 @@ them over any older versions of the app on your disk:
 * TALK.COM
 * RTC.COM
 * TIMER.COM
-* INTTEST.COM
 
 For example: `B>COPY ASSIGN.COM C:`
 
 Some RomWBW custom applications are too large to fit on the ROM disk.
 If you are using any of these you will need to transfer them to your
 system and then update all copies. These applications are found in
-the Binary\\Apps directory of the distribution and in all of the disk
+the Binary/Apps directory of the distribution and in all of the disk
 images.
 
 * FAT.COM
@@ -2976,30 +3121,34 @@ images.
 
 ## System Update
 
-If the system running ROMWBW utilizes the SST39SF040 Flash chip then it
-is possible to do a System Update in place of a System Upgrade in some
-cases.
+As previously described, a RomWBW ROM contains ROM applications as well 
+as a ROM disk image.  If you are upgrading your ROM with a new patch 
+level release, you may wish to upgrade just the application portion of 
+the ROM.  This is referred to as a System Update.
 
-A System Update would involve only updating the BIOS, ROM applications
-and CP/M system.
+If the system running ROMWBW utilizes the SST39SF040 Flash chip then it 
+is possible to do a System Update in place of a System Upgrade in some 
+cases.  A System Update would involve only updating the BIOS, ROM 
+applications and ROM-hosted operating systems.
 
 A System Update may be more favorable than a System Upgrade in cases
 such as:
 
- - Overwriting of the ROM drive is not desired.
- - Space is unavailable to hold a full ROMWBW ROM.
- - To mimimize time taken to transfer and flash a full ROM.
- - Configuration changes are only minor and do not impact disk applications.
+ - Overwriting of the ROM drive contents is not desired.
+ - Temporary disk space is unavailable to hold a full ROM image.
+ - To reduce the time taken to transfer and flash a full ROM.
+ - Configuration changes are only minor and do not impact disk
+   applications.
 
-The ROMWBW build process generates a system upgrade file along with
+The RomWBW build process generates a system update file along with
 the normal ROM image and can be identified by the extension ".upd". It
 will be 128Kb in size. In comparison the normal ROM image will have
 the extension ".rom" and be 512Kb or 1024Kb in size.
 
-Transferring and flashing the System Update is accomplished in the
-same manner as described above in *Upgrading* with the required
-difference being that the flash application needs to be directed to
-complete a partial flash using the /P command line switch.
+Transferring and flashing the System Update is accomplished in the same 
+manner as described above in [Upgrading via Flash Utility] with the 
+required difference being that the flash application needs to be 
+directed to complete a partial flash using the /P command line switch.
 
 `E>FLASH WRITE ROM.UPD /P`
 
@@ -3013,7 +3162,7 @@ please let me know if I missed you!
 
 * Andrew Lynch started it all when he created the N8VEM Z80 SBC
   which became the first platform RomWBW supported.  Some of his
-  code can still be found in RomWBW.
+  original code can still be found in RomWBW.
 
 * Dan Werner wrote much of the code from which RomWBW was originally
   derived and he has always been a great source of knowledge and
@@ -3025,23 +3174,30 @@ please let me know if I missed you!
   due  to internal changes within RomWBW. As of RomWBW 2.6, these
   applications are no longer provided.
 
+* Sergey Kiselev created several hardware platforms for RomWBW
+  including the very popular Zeta.
+
 * David Giles created support for the Z180 CSIO which is now included
   SD Card driver.
 
+* Phil Summers contributed the Forth and BASIC adaptations in ROM, the
+  AY-3-8910 sound driver, DMA support, and a long list of general code
+  and documentation enhancements.
+
 * Ed Brindley contributed some of the code that supports the RCBus
   platform.
 
-* Phil Summers contributed the Forth and BASIC adaptations in ROM, the
-  AY-3-8910 sound driver as well as a long list of general code
-  enhancements.
-
 * Spencer Owen created the RC2014 series of hobbyist kit computers
-  which has exponentially increased RomWBW usage.
+  which has exponentially increased RomWBW usage.  Some of his kits
+  include RomWBW.
 
 * Stephen Cousins has likewise created a series of hobbyist kit
   computers at Small Computer Central and is distributing RomWBW
   with many of them.
 
+* Alan Cox has contributed some driver code and has provided a great
+  deal of advice.
+
 * The CP/NET client files were developed by Douglas Miller.
 
 * Phillip Stevens contributed support for FreeRTOS.
@@ -3082,15 +3238,15 @@ Portions of RomWBW were created by, contributed by, or derived from
 the work of others.  It is believed that these works are being used
 in accordance with the intentions and/or licensing of their creators.
 
-If anyone feels their work is being used outside of it's intended
+If anyone feels their work is being used outside of its intended
 licensing, please notify:
 
-> Wayne Warthen
-> wwarthen@gmail.com
+> $doc_author$ \
+> [$doc_authmail$](mailto:$doc_authmail$)
 
 RomWBW is an aggregate work.  It is composed of many individual,
 standalone programs that are distributed as a whole to function as
-a cohesive system.  Each program may have it's own licensing which
+a cohesive system.  Each program may have its own licensing which
 may be different from other programs within the aggregate.
 
 In some cases, a single program (e.g., CP/M Operating System) is
@@ -3248,7 +3404,7 @@ the RomWBW HBIOS configuration.
 | Interrupts        | Mode 2        |
 
  - CPU speed is detected at startup if DS1302 RTC is active
-   - Otherwise 20.000 MHz assumed
+   - Otherwise 8.000 MHz assumed
  - System timer is generated by onboard CTC
  - Hardware auto-detected:
    - Onboard DS1302 RTC
@@ -3703,6 +3859,21 @@ the RomWBW HBIOS configuration.
 
 `\clearpage`{=latex}
 
+### Z80-Retro SBC
+
+|                   |                  |
+|-------------------|------------------|
+| ROM Image File    | Z80RETRO_std.rom |
+| Console Baud Rate | 38400            |
+| Interrupts        | Mode 2           |
+
+ - CPU speed is assumed to be 14.7456 MHz
+ - Hardware auto-detected:
+   - SIO Serial Interface Module
+   - Onboard CTC
+
+`\clearpage`{=latex}
+
 ## Appendix B - Device Summary
 
 The table below briefly describes each of the possible devices that

Source/HBIOS/API.txt

@@ -117,7 +117,11 @@ GET ($F8):
 						L=Clock Mult (0:Half, 1:Full, 2: Double)
 						D=Memory Wait States
 						E=I/O Wait States
-						
+
+    PANEL ($F4):
+      BC=Function/Subfunction			A=Result
+						L=Switch Values
+
 
 SET ($F9):
   BC=Function/Subfunction                       A=Result
@@ -142,6 +146,11 @@ SET ($F9):
 						E=I/O Wait States
 						
 
+    PANEL ($F4):
+      BC=Function/Subfunction			A=Result
+						L=LED Values
+
+
 PEEK ($FA):
   B=Function                       		A=Result
   D=Bank					E=Byte Value

Source/HBIOS/Build.cmd

@@ -223,5 +223,6 @@ call Build SCZ180 sc503 || exit /b
 call Build DYNO std || exit /b
 call Build UNA std || exit /b
 call Build RPH std || exit /b
+call Build Z80RETRO std || exit /b
 
 goto :eof

Source/HBIOS/Build.ps1

@@ -27,7 +27,7 @@ $ErrorAction = 'Stop'
 # UNA BIOS is simply imbedded, it is not built here.
 #
 
-$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "UNA"
+$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "UNA"
 $PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH"
 $PlatformListZ280 = "RCZ280"
 

Source/HBIOS/Build.sh

@@ -38,6 +38,7 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
 	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc140"; bash Build.sh
 	ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc503"; bash Build.sh
 	ROM_PLATFORM="UNA"; ROM_CONFIG="std"; bash Build.sh
+	ROM_PLATFORM="Z80RETRO"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="ZETA"; ROM_CONFIG="std"; bash Build.sh
 	ROM_PLATFORM="ZETA2"; ROM_CONFIG="std"; bash Build.sh
 	exit

Source/HBIOS/Config/RCZ180_ext.asm

@@ -29,6 +29,8 @@
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 MEMMGR		.SET	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;
 Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2

Source/HBIOS/Config/RCZ180_nat.asm

@@ -29,6 +29,8 @@
 CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 MEMMGR		.SET	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;
 Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2

Source/HBIOS/Config/RCZ280_ext.asm

@@ -30,6 +30,8 @@ CPUOSC		.SET	12000000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 MEMMGR		.SET	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;
 Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)

Source/HBIOS/Config/RCZ280_nat.asm

@@ -30,6 +30,8 @@ CPUOSC		.SET	12000000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	3		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 MEMMGR		.SET	MM_Z280		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 ;
 Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)

Source/HBIOS/Config/RCZ280_zz80mb.asm

@@ -32,6 +32,8 @@ CPUOSC		.SET	12000000	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	3		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 MEMMGR		.SET	MM_Z280		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 ;
 RAMLOC		.SET	23		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE

Source/HBIOS/Config/RCZ280_zzrc.asm

@@ -32,6 +32,8 @@ CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
 INTMODE		.SET	3		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 MEMMGR		.SET	MM_Z280		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 ;
 RAMSIZE		.SET	256		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)

Source/HBIOS/Config/RCZ80_easy.asm

@@ -33,6 +33,8 @@ CPUOSC		.SET	10000000	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 WDOGMODE	.SET	WDOG_EZZ80	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 WDOGIO		.SET	$6F		; WATCHDOG REGISTER ADR
 ;

Source/HBIOS/Config/RCZ80_kio.asm

@@ -30,6 +30,8 @@ CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 KIOENABLE	.SET	TRUE		; ENABLE ZILOG KIO SUPPORT

Source/HBIOS/Config/RCZ80_skz.asm

@@ -29,6 +29,8 @@
 CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 SKZENABLE	.SET	TRUE		; ENABLE SERGEY'S Z80-512K FEATURES
 SKZDIV		.SET	DIV_12		; UART CLK (CLK2) DIVIDER FOR Z80-512K
 WDOGMODE	.SET	WDOG_SKZ	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]

Source/HBIOS/Config/RCZ80_std.asm

@@ -29,6 +29,8 @@
 CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
@@ -53,6 +55,7 @@ FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3
 IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_PIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
 SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
 ;
 PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)

Source/HBIOS/Config/RCZ80_tiny.asm

@@ -33,6 +33,8 @@ CPUOSC		.SET	16000000	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 EIPCENABLE	.SET	TRUE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 WDOGMODE	.SET	WDOG_EZZ80	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 WDOGIO		.SET	$6F		; WATCHDOG REGISTER ADR

Source/HBIOS/Config/RCZ80_zrc.asm

@@ -30,6 +30,8 @@
 CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 RAMSIZE		.SET	1536		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 MEMMGR		.SET	MM_ZRC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
 ;

Source/HBIOS/Config/RCZ80_zrc_ram.asm

@@ -31,6 +31,8 @@
 CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
 CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+;
 RAMSIZE		.SET	2048		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	0		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 MEMMGR		.SET	MM_ZRC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]

Source/HBIOS/Config/SBC_simh.asm

@@ -30,6 +30,9 @@ INTMODE		.SET	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 ;
 HTIMENABLE	.SET	TRUE		; ENABLE SIMH TIMER SUPPORT
 ;
+SIMRTCENABLE	.SET	TRUE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+;
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTSBCFORCE	.SET	TRUE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
 ;

Source/HBIOS/Config/SCZ180_sc126.asm

@@ -35,6 +35,7 @@ Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
 DIAGENABLE	.SET	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.SET	$0D		; DIAGNOSTIC PORT ADDRESS
 ;

Source/HBIOS/Config/SCZ180_sc140.asm

@@ -34,9 +34,11 @@ Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.SET	$A0		; FRONT PANEL I/O PORT BASE ADDRESS
 LEDENABLE	.SET	TRUE		; ENABLE STATUS LED (SINGLE LED)
 DIAGENABLE	.SET	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.SET	$0D		; DIAGNOSTIC PORT ADDRESS
+DIAGPORT	.SET	$A0		; DIAGNOSTIC PORT ADDRESS
 ;
 DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
@@ -59,3 +61,5 @@ SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
 ;
 PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+;
+IDE0BASE	.SET	$90		; IDE 0: IO BASE ADDRESS

Source/HBIOS/Config/SCZ180_sc503.asm

@@ -34,9 +34,11 @@ Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
+FPENABLE	.SET	TRUE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.SET	$A0		; FRONT PANEL I/O PORT BASE ADDRESS
 LEDENABLE	.SET	TRUE		; ENABLE STATUS LED (SINGLE LED)
 DIAGENABLE	.SET	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.SET	$0D		; DIAGNOSTIC PORT ADDRESS
+DIAGPORT	.SET	$A0		; DIAGNOSTIC PORT ADDRESS
 ;
 DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
@@ -59,3 +61,5 @@ SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
 SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
 ;
 PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+;
+IDE0BASE	.SET	$90		; IDE 0: IO BASE ADDRESS

Source/HBIOS/Config/Z80RETRO_std.asm

@@ -0,0 +1,35 @@
+;
+;==================================================================================================
+;   ZETA2 STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_z80retro.asm"
+;
+CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+;
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+;
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)

Source/HBIOS/Config/ZETA2_std.asm

@@ -26,7 +26,7 @@
 ;
 #include "cfg_zeta2.asm"
 ;
-CPUOSC		.SET	20000000	; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 ;
@@ -35,7 +35,7 @@ UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTSBC		.SET	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
 ;
 FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.SET	FDMODE_ZETA	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+FDMODE		.SET	FDMODE_ZETA2	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
 ;
 PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)

Source/HBIOS/asci.asm

@@ -53,7 +53,7 @@
 ; ASEXT:
 ; 7 6 5 4 3 2 1 0
 ; R D C X B F D S
-; 0 1 1 0 0 1 1 0   DEFAULT VALUES
+; 0 1 1 0 0 0 0 0   DEFAULT VALUES
 ; | | | | | | | |
 ; | | | | | | | +-- SEND BREAK
 ; | | | | | | +---- BREAK DETECT (RO)
@@ -64,6 +64,10 @@
 ; | +-------------- DCD0 DISABLE
 ; +---------------- RDRF INT INHIBIT
 ;
+ASCI_DEF_CNTLA	.EQU	$64
+ASCI_DEF_CNTLB	.EQU	$20
+ASCI_DEF_ASEXT	.EQU	$60
+;
 ASCI_BUFSZ	.EQU	32		; RECEIVE RING BUFFER SIZE
 ;
 ASCI_NONE	.EQU	0		; NOT PRESENT
@@ -513,17 +517,29 @@ ASCI_INITDEV3:
 	SET	4,C			; SET CNTLB BIT 4 FOR ODD PARITY
 ;
 ASCI_INITDEV4:
+	; SETUP ASEXT
+	LD	A,D			; CONFIG HIGH BYTE
+	AND	%00100000		; BIT 5 IS RTS
+	CPL				; INVERT FOR ASEXT
+	LD	L,A			; MOVE TO L
+	LD	A,ASCI_DEF_ASEXT	; GET ASEXT DEFAULT
+	AND	L			; COMBINE
+	LD	L,A			; AND LEAVE IN L
+;
 	; SAVE CONFIG PERMANENTLY NOW
 	LD	(IY+4),E		; SAVE LOW WORD
 	LD	(IY+5),D		; SAVE HI WORD
 	JR	ASCI_INITGO
 ;
 ASCI_INITSAFE:
-	LD	B,$64			; CNTLA FAILSAFE VALUE
-	LD	C,$20			; CNTLB FAILSAFE VALUE
+	LD	B,ASCI_DEF_CNTLA	; CNTLA FAILSAFE VALUE
+	LD	C,ASCI_DEF_CNTLB	; CNTLB FAILSAFE VALUE
+	LD	L,ASCI_DEF_ASEXT	; ASEXT FAILSAFE VALUE
 ;
 ASCI_INITGO:
 	; IMPLEMENT CONFIGURATION
+	; B = CNTLA, C=CNTLB, L=ASEXT
+	PUSH	HL			; SAVE ASEXT
 	LD	H,B			; H := CNTLA VAL
 	LD	L,C			; L := CNTLB VAL
 	LD	B,0			; MSB OF PORT MUST BE ZERO!
@@ -532,6 +548,7 @@ ASCI_INITGO:
 	INC	C			; BUMP TO
 	INC	C			; ... CNTLB REG, B IS STILL 0
 	OUT	(C),L			; WRITE CNTLB VALUE
+	POP	HL			; RECOVER ASEXT
 	INC	C			; BUMP TO
 	INC	C			; ... STAT REG, B IS STILL 0
 #IF ((ASCIINTS) & (INTMODE > 0))
@@ -543,8 +560,11 @@ ASCI_INITGO:
 	LD	A,$0E			; BUMP TO
 	ADD	A,C			; ... ASEXT REG
 	LD	C,A			; PUT IN C FOR I/O, B IS STILL 0
-	LD	A,$66			; STATIC VALUE FOR ASEXT
-	OUT	(C),A			; WRITE ASEXT REG
+	BIT	0,C			; IS C ADDRESSING AN ODD NUMBERED PORT?
+	JR	NZ,ASCI_INITGOZ		; IF SO, THIS IS SEC SERIAL, NO CTS!
+	OUT	(C),L			; WRITE ASEXT REG
+;
+ASCI_INITGOZ:
 ;
 #IF ((ASCIINTS) & (INTMODE > 0))
 ;

Source/HBIOS/cfg_dyno.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -66,6 +66,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -146,7 +148,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
@@ -154,7 +156,7 @@ SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
@@ -183,9 +185,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_DYNO	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -225,7 +227,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_master.asm

@@ -12,7 +12,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -95,6 +95,8 @@ SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 WDOGIO		.EQU	$6F		; WATCHDOG REGISTER ADR
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -194,7 +196,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -202,7 +204,7 @@ SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
@@ -237,9 +239,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_NONE	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
@@ -280,7 +282,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_NONE	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_NONE	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_mbc.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -60,6 +60,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -132,7 +134,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -166,9 +168,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_MBC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
@@ -209,7 +211,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_mk4.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -66,6 +66,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -143,7 +145,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -176,9 +178,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_DIDE	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
@@ -219,7 +221,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MK4	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_MK4	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_n8.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -68,6 +68,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -145,7 +147,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -178,9 +180,9 @@ FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_N8	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
@@ -221,7 +223,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
+SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	N8_PPI0		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_rcz180.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -66,6 +66,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -146,7 +148,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
@@ -154,7 +156,7 @@ SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
@@ -183,9 +185,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -225,7 +227,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_rcz280.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z280	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -66,6 +66,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -156,7 +158,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -164,7 +166,7 @@ SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
@@ -193,9 +195,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -235,7 +237,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_rcz80.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -65,6 +65,8 @@ SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 WDOGIO		.EQU	$6E		; WATCHDOG REGISTER ADR
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -150,7 +152,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -158,7 +160,7 @@ SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
@@ -187,9 +189,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -229,7 +231,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_rph.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -66,6 +66,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -167,9 +169,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_N8	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
@@ -210,7 +212,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	RPH_PPI0	; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_sbc.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -60,6 +60,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -132,7 +134,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
@@ -161,14 +163,13 @@ MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
 MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-;
 FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_DIO3	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
@@ -209,7 +210,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_scz180.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -66,6 +66,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$0D		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$0D		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -146,7 +148,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
@@ -154,7 +156,7 @@ SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
 SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
+SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
 SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
 SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
@@ -183,9 +185,9 @@ FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -225,7 +227,7 @@ PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_una.asm

@@ -15,10 +15,12 @@
 ;
 #INCLUDE "../UBIOS/ubios.inc"
 ;
-;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+;PLATFORM	.EQU	PLT_UNA		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_UNA	; HARDWARE BIOS: BIOS_[WBW|UNA]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+;
 BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO

Source/HBIOS/cfg_z80retro.asm

@@ -0,0 +1,223 @@
+;
+;==================================================================================================
+;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR SIMPLE Z80 RETRO
+;==================================================================================================
+;
+; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
+; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
+; UNDER THIS DIRECTORY.
+;
+; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
+; FOR THE PLATFORM.
+;
+#DEFINE PLATFORM_NAME "Z80Retro", " [", CONFIG, "]"
+;
+#INCLUDE "hbios.inc"
+;
+PLATFORM	.EQU	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
+CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+;
+BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+;
+CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.EQU	14745600	; CPU OSC FREQ IN MHZ
+INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+;
+RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE_CHK	.EQU	0		; ROMSIZE VALUE VERIFICATION (0=DISABLED)
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
+MPGSEL_0	.EQU	$60		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.EQU	$61		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.EQU	$62		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.EQU	$63		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.EQU	$64		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+;
+RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
+;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
+CTCENABLE	.EQU	TRUE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.EQU	$40		; CTC BASE I/O ADDRESS
+CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER (too fast for RomWBW right now)
+CTCMODE		.EQU	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.EQU	0		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.EQU	1		; TIMER CHANNEL (0-3)
+CTCOSC		.EQU	7372800		; CTC CLOCK FREQUENCY
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
+DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
+DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
+DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+;
+LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
+LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|RTC]
+LEDPORT		.EQU	$00		; STATUS LED PORT ADDRESS
+LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+;
+DSKYENABLE	.EQU	FALSE		; ENABLES DSKY
+DSKYMODE	.EQU	DSKYMODE_V1	; DSKY VERSION: DSKYMODE_[V1|NG]
+DSKYPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF DSKY PPI
+DSKYOSC		.EQU	3000000		; OSCILLATOR FREQ FOR DSKYNG (IN HZ)
+;
+BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
+CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MKYENABLE	.EQU	FALSE		; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
+;
+DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
+DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+;
+DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+;
+BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+;
+INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
+HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+;
+DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+;
+DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+;
+UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UARTCFG		.EQU	DEFSERCFG	; UART: LINE CONFIG FOR UART PORTS
+UARTCASSPD	.EQU	SER_300_8N1	; UART: ECB CASSETTE UART DEFAULT SPEED
+UARTSBC		.EQU	TRUE		; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
+UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
+UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
+UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
+UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
+UARTRC		.EQU	FALSE		; UART: AUTO-DETECT RC UART
+UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+;
+ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+;
+Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+;
+ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+;
+SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIO0MODE	.EQU	SIOMODE_Z80R	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.EQU	CPUOSC/2	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.EQU	CPUOSC/2	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.EQU	SIOMODE_Z80R	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.EQU	CPUOSC/2	; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.EQU	CPUOSC/2	; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+;
+XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+;
+VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
+TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+;
+MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+;
+FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.EQU	FDMODE_ZETA2	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.EQU	1		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+;
+RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+;
+IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+;
+PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.EQU	$60		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+;
+SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.EQU	SDMODE_Z80R	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
+SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+;
+PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+;
+PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPBASE		.EQU	$60		; PPP: PPI REGISTERS BASE ADDRESS
+PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
+PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
+;
+HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+;
+PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+;
+LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+;
+PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIOSBASE	.EQU	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
+;
+UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+SN76489ENABLE	.EQU	FALSE		; SN76489 SOUND DRIVER
+AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+;
+DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+;
+YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
+VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_zeta.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; BIOS_[WBW|UNA]: HARDWARE BIOS
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -52,6 +52,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -137,9 +139,9 @@ FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_ZETA	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	1		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -153,7 +155,7 @@ PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
 PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/cfg_zeta2.asm

@@ -15,7 +15,7 @@
 ;
 #INCLUDE "hbios.inc"
 ;
-PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH]
+PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
 CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -28,7 +28,7 @@ BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
 ;
 CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
 CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	20000000	; CPU OSC FREQ IN MHZ
+CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
 INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
@@ -63,6 +63,8 @@ SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
+FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
+FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
@@ -148,9 +150,9 @@ FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
 FDMODE		.EQU	FDMODE_ZETA2	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
 FDCNT		.EQU	1		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
 FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMEDIA		.EQU	FDM144		; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
-FDMEDIAALT	.EQU	FDM720		; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
 FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
 RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
@@ -164,7 +166,7 @@ PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
 PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
 SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
+SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
 SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
 SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
 SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

Source/HBIOS/ctc.asm

@@ -9,7 +9,7 @@ CTC_DEFCFG	.EQU	%01010011	; CTC DEFAULT CONFIG
 CTC_CTRCFG	.EQU	%01010111	; CTC COUNTER MODE CONFIG
 CTC_TIM16CFG	.EQU	%00010111	; CTC TIMER/16 MODE CONFIG
 CTC_TIM256CFG	.EQU	%00110111	; CTC TIMER/256 MODE CONFIG
-CTC_TIMCFG	.EQU	%11010111	; CTC TIMER CHANNEL CONFIG
+;CTC_TIMCFG	.EQU	%11010111	; CTC TIMER CHANNEL CONFIG
 		;	 |||||||+-- CONTROL WORD FLAG
 		;	 ||||||+--- SOFTWARE RESET
 		;	 |||||+---- TIME CONSTANT FOLLOWS
@@ -19,6 +19,12 @@ CTC_TIMCFG	.EQU	%11010111	; CTC TIMER CHANNEL CONFIG
 		;	 |+-------- COUNTER MODE
 		;	 +--------- INTERRUPT ENABLE
 ;
+;==================================================================================================
+; ONLY IM2 IMPLEMENTED BELOW.  I DON'T SEE ANY REASONABLE WAY TO IMPLEMENT AN IM1 TIMER BECAUSE
+; THE CTC PROVIDES NO WAY TO DETERMINE IF IT WAS THE CAUSE OF AN INTERRUPT OR A WAY TO
+; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT.
+;==================================================================================================
+;
 #IF (INTMODE != 2)
 	.ECHO	"*** WARNING: CTC TIMER DISABLED -- INTMODE 2 REQUIRED!!!\n"
 #ENDIF
@@ -32,15 +38,56 @@ CTC_TIMCFG	.EQU	%11010111	; CTC TIMER CHANNEL CONFIG
 	.ECHO	(INT_CTC0A % 4)
 	.ECHO	"\n"
   
-	.ECHO	"*** ERROR: CTC BASE VECTOR NOT /4 ALIGNED!!!\n"
+	.ECHO	"*** ERROR: CTC BASE VECTOR NOT DWORD ALIGNED!!!\n"
 	!!!	; FORCE AN ASSEMBLY ERROR
   #ENDIF
 ;
-; ONLY IM2 IMPLEMENTED BELOW.  I DON'T SEE ANY REASONABLE WAY TO
-; IMPLEMENT AN IM1 TIMER BECAUSE THE CTC PROVIDES NO WAY TO
-; DETERMINE IF IT WAS THE CAUSE OF AN INTERRUPT OR A WAY TO
-; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT.
-;  
+;==================================================================================================
+; TIMER SETUP
+;
+; A PERIODIC INTERRUPT TIMER CAN BE SETUP USING EITHER THE CPU SYSTEM CLOCK OR AN EXTERNAL
+; OSCILLATOR CONNECTED TO THE CTC. THE DEFACTO PERIOD FOR THIS TIMER IS 50Hz OR 60Hz.
+;
+; THE DESIRED TIMER PERIOD IS SET IN THE CONFIGURATION:
+;	TICKFREQ	.SET	60	; OR
+;	TICKFREQ	.SET	50
+;
+; THIS DRIVER USES TWO CTC CHANNELS TO CREATE A TWO STEP DIVIDER THAT DIVIDES THE CPU SYSTEM 
+; CLOCK OR EXTERNAL OSCILLATOR INTO A PERIODIC TICK THAT GENERATES AN INTERRUPT.
+;
+; THE CPU CLOCK OR CTC EXTERNAL OSCILLATOR NEEDS TO BE LESS THAN 3.932160MHz FOR A 60HZ TIMER
+; TICK OR 3.276800MHz FOR A 50Hz TIMER TICK.
+;
+; THE CHANNELS USED ARE DEFINED BY THE CTCPRECH AND CTCTIMCH DEFINITIONS - TYPICALLY 2 & 3.
+; EXTERNAL HARDWARE MUST BE CONFIGURED TO MATCH THIS CONFIGURATION.
+;
+; EACH CHANNEL SUCCESSIVELY DIVIDES THE CLOCK OR OSCILLATOR FREQUENCY DOWN TO A 50 OR 60Hz TICK.
+; THE FIRST DIVIDER CHANNEL IS THE PRESCALER, THE SECOND IS THE TIMER CHANNEL. 
+;
+; IF CTCMODE IS CTCMODE_CTR THEN THE OSCILLATOR CONNECTED TO CTC PRESCALER CHANNEL IS USED.
+;
+; 	THE CONFIGURATION FILES DEFINE THE OSCILLATOR FREQUENCY THAT IS CONNECTED TO THE PRESCALER
+; 	CHANNEL. I.E. THE EXTERNAL HARDWARE CONNECTED TO THE CTC.
+;
+;	FOR A 60Hz TIMER WITH A 3.579545Mhz OSCILLATOR USE:
+;	CTCMODE		.SET	CTCMODE_CTR
+;	TICKFREQ	.SET	60
+;	CTCOSC		.SET	3579545	
+;	
+; IF CTCMODE IS CTCMODE_TIM16 OR CTCMODE_TIM256 THE CPU SYSTEM CLOCK FREQUENCY IS USED.
+;
+;  	THIS MODE HAS LIMITED VALUE AS MANY SYSTEMS OPERATE ABOVE THE USABLE TOP FREQUENCY.
+;	THE CONFIGURATION FILE MUST BE UPDATED TO MATCH YOUR CPU CLOCK FREQUENCY.
+;
+;	FOR A 60Hz TIMER WITH A 2Mhz OSCILLATOR USE:
+;	CTCMODE		.SET	CTCMODE_TIM256
+;	TICKFREQ	.SET	60
+;	CTCOSC		.SET	2000000
+;
+;	NOTE THAT IF CPU SPEED IS CHANGED IN THIS MODE, THE TIMER SPEED WILL ALSO CHANGE.
+;
+;==================================================================================================
+;
 CTC_PREIO	.EQU	CTCBASE + CTCPRECH
 CTC_SCLIO	.EQU	CTCBASE + CTCTIMCH
 ;
@@ -81,29 +128,35 @@ CTC_DIVLO	.EQU	(CTC_DIV / CTC_DIVHI)
   #ENDIF
 ;
   #IF ((CTC_DIVHI * CTC_DIVLO * CTC_PRESCL * TICKFREQ) != CTCOSC)
-	.ECHO "COMPUTED CTC DIVISOR IS UNUSABLE!\n"
-	!!!
+	.ECHO "WARNING: COMPUTED CTC DIVISOR IS INACCURATE!\n"
   #ENDIF
 ;
 CTCTIVT		.EQU	INT_CTC0A + CTCTIMCH
 ;
 #ENDIF
 ;
+;==================================================================================================
+; CTC PRE-INITIALIZATION
 ;
+; CHECK TO SEE IF A CTC EXISTS. IF IT EXISTS, ALL FOUR CTC CHANNELS ARE PROGRAMMED TO:
+;  INTERRUPTS DISABLED, COUNTER MODE, RISING EDGE TRIGGER, RESET STATE.
+;
+; IF THE CTCTIMER CONFIGURATION IS SET, THEN A PERIOD INTERRUPT TIMER IS SET UP USING CTC CHANNELS
+; 2 (CTCPRECH) & 3 (CTCTIMCH). THE TIMER WILL BE SETUP TO 50 OR 60HZ DEPENDING ON CONFIGURATION 
+; SETTING TICKFREQ. CHANNEL 3 WILL GENERATE THE TICK INTERRUPT.. 
+;==================================================================================================
 ;
 CTC_PREINIT:
+	; BLINDLY RESET THE CTC ASSUMING IT IS THERE
+	LD	A,CTC_DEFCFG
+	OUT	(CTCBASE),A
+	OUT	(CTCBASE+1),A
+	OUT	(CTCBASE+2),A
+	OUT	(CTCBASE+3),A
+;
 	CALL	CTC_DETECT		; DO WE HAVE ONE?
 	LD	(CTC_EXIST),A		; SAVE IT
 	RET	NZ			; ABORT IF NONE
-;
-	; RESET ALL CTC CHANNELS
-	LD	B,4			; 4 CHANNELS
-	LD	C,CTCBASE		; FIRST CHANNEL PORT
-CTC_PREINIT1:
-	LD	A,CTC_DEFCFG		; CTC DEFAULT CONFIG
-	OUT	(C),A			; CTC COMMAND
-	INC	C			; NEXT CHANNEL PORT
-	DJNZ	CTC_PREINIT1
 ;
 #IF (CTCTIMER & (INTMODE == 2))
 	; SETUP TIMER INTERRUPT IVT SLOT
@@ -122,12 +175,12 @@ CTC_PREINIT1:
 	; CTC CHANNEL AS A PRESCALER AND ANOTHER AS THE ACTUAL
 	; TIMER INTERRUPT.  THE PRESCALE CHANNEL OUTPUT MUST BE WIRED
 	; TO THE TIMER CHANNEL TRIGGER INPUT VIA HARDWARE.
-	LD	A,CTC_PRECFG		; PRESCALE CHANNEL CONFIGURATION
+	LD	A,CTC_PRECFG		; PRESCALE TIMER CHANNEL CFG
 	OUT	(CTC_PREIO),A		; SETUP PRESCALE CHANNEL
 	LD	A,CTC_DIVHI & $FF	; PRESCALE CHANNEL CONSTANT
 	OUT	(CTC_PREIO),A		; SET PRESCALE CONSTANT
 ;
-	LD	A,CTC_TIMCFG		; TIMER CHANNEL CONTROL WORD VALUE
+	LD	A,CTC_CTRCFG | $80	; TIMER CHANNEL + INT CFG
 	OUT	(CTC_SCLIO),A		; SETUP TIMER CHANNEL
 	LD	A,CTC_DIVLO & $FF	; TIMER CHANNEL CONSTANT
 	OUT	(CTC_SCLIO),A		; SET TIMER CONSTANT
@@ -137,7 +190,9 @@ CTC_PREINIT1:
 	XOR	A
 	RET
 ;
-;
+;==================================================================================================
+; DRIVER INITIALIZATION
+;==================================================================================================
 ;
 CTC_INIT:				; MINIMAL INIT
 CTC_PRTCFG:
@@ -200,30 +255,34 @@ CTC_PRTCFG1:
 	XOR	A
 	RET
 ;
-;
+;==================================================================================================
+; DETECT CTC BY PROGRAMMING THE FIRST CHANNEL TO COUNT IN TIMER
+; MODE (BASED ON CPU CLOCK).  THEN CHECK IF COUNTER IS ACTUALLY
+; RUNNING.
+;==================================================================================================
 ;
 CTC_DETECT:
-	LD	A,CTC_TIM256CFG
-	OUT	(CTCBASE),A
-	XOR	A
-	OUT	(CTCBASE),A
-	; CTC SHOULD NOW BE RUNNING WITH TIME CONSTANT 0
-	LD	A,CTC_TIM256CFG		; RESET
-	OUT	(CTCBASE),A
-	IN	A,(CTCBASE)		; SHOULD READ 0 NOW
-	CP	0
-	JR	NZ,CTC_NO
+	LD	A,CTC_TIM16CFG		; RESET & SETUP TIMER MODE
+	OUT	(CTCBASE),A		; SEND TO CTC
 	LD	A,$FF			; TIME CONSTANT $FF
-	OUT	(CTCBASE),A
-	IN	A,(CTCBASE)		; SHOULD NOT BE 0 NOW
-	CP	0
-	JR	Z,CTC_NO
-	XOR	A
-	RET
+	OUT	(CTCBASE),A		; SEND CONSTANT & START CTR
+	NOP				; BRIEF DELAY
+	IN	A,(CTCBASE)		; READ COUNTER
+	LD	C,A			; SAVE VALUE
+	CALL	DLY8			; WAIT A BIT
+	IN	A,(CTCBASE)		; READ COUNTER AGAIN
+	PUSH	AF			; SAVE RESULT
+	LD	A,CTC_DEFCFG		; DEFAULT CHANNEL CFG
+	OUT	(CTCBASE),A		; RESTORE TO DEFAULTS
+	POP	AF			; GET RESULT BACK
+	CP	C			; COMPARE TO PREVIOUS
+	JR	Z,CTC_NO		; IF SAME, FAIL
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND DONE
 CTC_NO:
-	OR	$FF
-	RET
+	OR	$FF			; SIGNAL FAILURE
+	RET				; AND DONE
 ;
+; CTC DRIVER DATA STORAGE
 ;
-;
-CTC_EXIST	.DB	$FF	
+CTC_EXIST	.DB	$FF		; SET TO ZERO IF EXISTS

Source/HBIOS/dbgmon.asm

@@ -878,6 +878,8 @@ GETLNLOP:
 	JR	Z,GETLNDONE		; YES, EXIT
 	CP	CHR_BS			; IS <BS>?
 	JR	Z,GETLNBS		; IF SO, HANDLE IT
+	CP	CHR_DEL			; IS <DEL>?
+	JR	Z,GETLNBS		; IF SO, HANDLE AS <BS>
 	CP	' '			; UNEXPECTED CONTROL CHAR?
 	JR	C,GETLNLOP		; IF SO, IGNORE IT AND GET NEXT
 	LD	B,A			; SAVE CHAR IN B FOR NOW
@@ -1854,6 +1856,7 @@ CHR_CR		.EQU	0DH
 CHR_LF		.EQU	0AH
 CHR_BS		.EQU	08H
 CHR_ESC		.EQU	1BH
+CHR_DEL		.EQU	7FH
 ;
 ;__________________________________________________________________________________________________
 ;

Source/HBIOS/dma.asm

@@ -72,7 +72,9 @@ DMA_INIT:
 	di
 	otir				; load dma
 	ei
+
 	xor	a			; set status
+	ld	(DMA_FAIL_FLAG),a	; ok to use dma
 ;
 DMA_EXIT:
 	DMAIOFULL
@@ -94,7 +96,7 @@ DMA_NOTFOUND:
 	jr	DMA_EXIT
 ;
 DMA_FAIL_FLAG:
-	.db	0	
+	.db	DMA_FAIL_FLAG	
 ;
 ;==================================================================================================
 ; DMA PROBE - WRITE TO ADDRESS REGISTER AND READ BACK

Source/HBIOS/fd.asm

@@ -109,7 +109,7 @@ FRC_TOSEEKWT	.EQU	-15H		; EB
 ; FD DEVICE CONFIGURATION
 ;
 FD_DEVCNT	.EQU	FDCNT		; 2 DEVICES SUPPORTED
-FD_CFGSIZ	.EQU	8		; SIZE OF CFG TBL ENTRIES
+FD_CFGSIZ	.EQU	9		; SIZE OF CFG TBL ENTRIES
 ;
 ; PER DEVICE DATA OFFSETS
 ;					; OFFSET OF...
@@ -121,25 +121,28 @@ FD_HST		.EQU	4		; HOSTS SEEK POSITION
 FD_HSTTRK	.EQU	FD_HST + 0	; HOST TRACK (WORD)
 FD_HSTSEC	.EQU	FD_HST + 2	; HOST SECTOR (BYTE)
 FD_HSTHD	.EQU	FD_HST + 3	; HOST HEAD (BYTE)
+FD_TYPE		.EQU	8		; FLOPPY DSIK TYPE (BYTE)
 ;
 FD_CFGTBL:
 	; DEVICE 0, PRIMARY MASTER
 	.DB	0			; DEVICE NUMBER
 	.DB	0			; DEVICE STATUS
-	.DB	FDMEDIA			; MEDIA TYPE
+	.DB	$FF			; CURRENT MEDIA TYPE (INIT TO NONE)
 	.DB	$FF			; CURRENT TRACK
 	.DW	0			; HOST TRACK
 	.DB	0			; HOST SECTOR
 	.DB	0			; HOST HEAD
+	.DB	FD0TYPE			; DRIVE TYPE
 #IF (FD_DEVCNT >= 2)
 	; DEVICE 1, PRIMARY SLAVE
 	.DB	1			; DRIVER DEVICE NUMBER
 	.DB	0			; DEVICE STATUS
-	.DB	FDMEDIA			; MEDIA TYPE
+	.DB	$FF			; CURRENT MEDIA TYPE (INIT TO NONE)
 	.DB	$FF			; CURRENT TRACK
 	.DW	0			; HOST TRACK
 	.DB	0			; HOST SECTOR
 	.DB	0			; HOST HEAD
+	.DB	FD1TYPE			; DRIVE TYPE
 #ENDIF
 ;
 #IF ($ - FD_CFGTBL) != (FD_DEVCNT * FD_CFGSIZ)
@@ -199,6 +202,42 @@ FSST_ENTSIZ	.EQU	$ - FSST
 FSST_COUNT	.EQU	(($ - FSST) / FSST_ENTSIZ)	; # ENTRIES IN TABLE
 #ENDIF
 ;
+; FDC DRIVE TYPE MEDIA OPTIONS
+;
+; THIS TABLE LISTS THE TYPES OF MEDIA THAT SHOULD BE ATTEMPTED
+; FOR EACH POSSIBLE DRIVE TYPE.  THE ENTRIES MATCH THE ORDER OF THE
+; FDT_ VALUES DEFINED IN STD.ASM
+;
+FD_MEDIAMAP:
+		.DW	FDMM_NONE	; NO DRIVE TYPE
+		.DW	FDMM_3DD
+		.DW	FDMM_3HD
+		.DW	FDMM_5DD
+		.DW	FDMM_5HD
+		.DW	FDMM_8
+;
+FDMM_NONE	.DB	$FF
+FDMM_3DD	.DB	FDM720, $FF
+FDMM_3HD	.DB	FDM144, FDM720, $FF
+FDMM_5DD	.DB	FDM360, $FF
+FDMM_5HD	.DB	FDM120, FDM360, $FF
+FDMM_8		.DB	FDM111, $FF
+;
+; FDC DRIVE TYPE ATTRIBUTES
+;
+; LOOKUP TABLE TO MAP THE DEVICE ATTRIBUTES BYTE RETURNED
+; BY THE FD_DEVICE FUNCTION BASED ON THE DRIVE TYPE.
+; THE ENTRIES MATCH THE ORDER OF THE
+; FDT_ VALUES DEFINED IN STD.ASM
+;
+FD_DEVATTR:
+		.DB	%11100000	; DRIVE TYPE NONE
+		.DB	%11010100	; DRIVE TYPE 3.5 DD
+		.DB	%11011000	; DRIVE TYPE 3.5 HD
+		.DB	%10110100	; DRIVE TYPE 5.25 DD
+		.DB	%10111000	; DRIVE TYPE 5.25 HD
+		.DB	%10010100	; DRIVE TYPE 8
+;
 ; FDC COMMANDS
 ;
 CFD_READ	.EQU	00000110B	; CMD,HDS/DS,C,H,R,N,EOT,GPL,DTL --> ST0,ST1,ST2,C,H,R,N
@@ -498,21 +537,11 @@ FD_DEFMED:
 FD_DEVICE:
 	LD	D,DIODEV_FD		; D := DEVICE TYPE
 	LD	E,(IY+FD_DEV)		; E := PHYSICAL DEVICE NUMBER
-#IF (FDMEDIA == FDM720)
-	LD	C,%11010100		; 3.5" DS/DD
-#ENDIF
-#IF (FDMEDIA == FDM144)
-	LD	C,%11011000		; 3.5" DS/HD
-#ENDIF
-#IF (FDMEDIA == FDM360)
-	LD	C,%10110100		; 5.25" DS/DD
-#ENDIF
-#IF (FDMEDIA == FDM120)
-	LD	C,%10111000		; 5.25" DS/HD
-#ENDIF
-#IF (FDMEDIA == FDM111)
-	LD	C,%10010100		; 8" DS/DD
-#ENDIF
+
+	LD	A,(IY+FD_TYPE)		; DRIVE TYPE
+	LD	HL,FD_DEVATTR		; DEVICE ATTR TABLE
+	CALL	ADDHLA			; POINT TO ENTRY
+	LD	C,(HL)			; GET IT
 	LD	H,FDMODE		; H := MODE
 	LD	L,FDC_MSR		; L := BASE I/O ADDRESS
 	XOR	A			; SIGNAL SUCCESS
@@ -527,9 +556,7 @@ FD_MEDIA:
 
 #IF (FDMAUTO)
 	; SETUP TO READ TRK 0, HD 0, SEC 0
-	;LD	A,C			; C STILL HAS REQUESTED DRIVE
 	LD	A,(IY+FD_DEV)		; GET DRIVE UNIT
-	;AND	0FH
 	LD	(FCD_DS),A
 	LD	A,0
 	LD	(FCD_C),A
@@ -538,53 +565,77 @@ FD_MEDIA:
 	LD	(FCD_R),A
 	LD	A,DOP_READID
 	LD	(FCD_DOP),A
+#ENDIF
 
-#IF (FDTRACE < 3)
+
+	LD	A,(IY+FD_TYPE)		; GET DRIVE TYPE VALUE
+	;CALL	PRTHEXBYTE		; *DEBUG*
+	LD	HL,FD_MEDIAMAP		; POINT TO MEDIA MAP TABLE
+	ADD	A,A			; TABLE IS WORD SIZED
+	CALL	ADDHLA			; LOOKUP ENTRY
+	LD	A,(HL)			; DEREFERENCE
+	INC	HL
+	LD	H,(HL)
+	LD	L,A
+
+#IF (FDMAUTO)
+  #IF (FDTRACE < 3)
 	; SUPPRESS TRACING FOR MEDIA TESTS
 	LD	A,0
 	LD	(FCD_TRACE),A
-#ENDIF
-
-	LD	B,5
+  #ENDIF
 
+	LD	B,5			; 5 ATTEMPTS
 FD_MEDIARETRY:
-	; TRY PRIMARY MEDIA CHOICE FIRST
-	LD	A,FDMEDIA
-	CALL	FD_TESTMEDIA
-	JR	Z,FD_MEDIA3		; IF SUCCESS, WE ARE DONE
-
-	; TRY ALTERNATE MEDIA CHOICE
-	LD	A,FDMEDIAALT
-	CALL	FD_TESTMEDIA
-	JR	Z,FD_MEDIA3		; IF SUCCESS, WE ARE DONE
-
-	DJNZ	FD_MEDIARETRY
+	PUSH	HL			; SAVE MEDIA MAP PTR
+	CALL	FD_MEDIALOOP		; TRY IT
+	POP	HL			; RECOVER MEDIA MAP PTR
+	JR	Z,FD_MEDIA3		; CONTINUE ON SUCCESS
+	DJNZ	FD_MEDIARETRY		; LOOP TILL DONE
 
+FD_MEDIARETRY1:
 	; NO JOY, RETURN WITH E=0 (NO MEDIA)
-	;LD	HL,(FDDS_MEDIAADR)
-	;LD	(HL),0			; SET TO NO MEDIA
-	LD	(IY+FD_MEDTYP),0	; SET DRIVE = NO MEDIA
-	LD	E,0
+	LD	(IY+FD_MEDTYP),$FF	; SET MEDIA TYPE TO UNDEFINED
+	LD	E,0			; NO MEDIA FLAG
 	LD	A,ERR_NOMEDIA		; SIGNAL ERROR
 	OR	A			; SET FLAGS
 	RET
 
+FD_MEDIALOOP:
+	LD	A,(HL)			; LOAD NEXT MEDIA TYPE TO TRY
+	CP	$FF			; END OF MEDIA TYPES TO TRY?
+	JR	Z,FD_MEDIALOOP1		; NO MORE TO TRY, LOOP EXIT
+	CALL	FD_TESTMEDIA		; TRY IT
+	RET	Z			; RETURN ON SUCCESS
+	INC	HL			; NEXT MEDIA TYPE TO TRY
+	JR	FD_MEDIALOOP		; LOOP
+FD_MEDIALOOP1:
+	OR	$FF			; SIGNAL FAILURE
+	RET				; RETURN
+
 FD_TESTMEDIA:
-	;LD	HL,(FDDS_MEDIAADR)
-	;LD	(HL),A
+	;CALL	PRTHEXBYTE		; *DEBUG*
 	LD	(IY+FD_MEDTYP),A
+	PUSH	HL
 	PUSH	BC
 	CALL	FD_START
 	POP	BC
+	POP	HL
+	;CALL	PRTHEXBYTE		; *DEBUG*
 	RET
 
 FD_MEDIA3:
 
-#IF (FDTRACE < 3)
+  #IF (FDTRACE < 3)
 	; RESTORE TRACING FOR MEDIA TESTS
 	LD	A,FDTRACE
 	LD	(FCD_TRACE),A
-#ENDIF
+  #ENDIF
+#ELSE
+
+	LD	A,(HL)
+	LD	(IY+FD_MEDTYP),A
+
 #ENDIF
 
 FD_MEDIA4:
@@ -778,7 +829,7 @@ FD_DETECT1:
 ;
 FD_INITUNIT:
 	LD	(IY+FD_STAT),0		; CLEAR STATUS
-	LD	(IY+FD_MEDTYP),FDMEDIA	; SET DEFAULT MEDIA TYPE
+	LD	(IY+FD_MEDTYP),$FF	; SET UNKNOWN MEDIA TYPE
 	LD	(IY+FD_CURTRK),$FE	; SPECIAL VALUE FOR CURTRK
 	RET
 ;
@@ -1285,7 +1336,8 @@ FC_SETUPIO:
 	LD	(DE),A
 	INC	DE
 
-	LD	A,(FCD_EOT)
+	;LD	A,(FCD_EOT)
+	LD	A,(FCD_R)		; READ ONLY ONE SECTOR
 	LD	(DE),A
 	INC	DE
 
@@ -1397,15 +1449,17 @@ FC_RESETFDC:
 ; PULSE TERMCT TO TERMINATE ANY ACTIVE EXECUTION PHASE
 ;
 FC_PULSETC:
-#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC))
-	IN	A,(FDC_TC)
-#ELSE
-	LD	A,(FST_DOR)
-	SET	0,A
-	OUT	(FDC_DOR),A
-	RES	0,A
-	OUT	(FDC_DOR),A
-#ENDIF
+; PULSING TC NO LONGER REQUIRED BECAUSE WE ONLY READ A SINGLE SECTOR
+;
+;#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO) | (FDMODE == FDMODE_EPFDC) | (FDMODE == FDMODE_MBC))
+;	IN	A,(FDC_TC)
+;#ELSE
+;	LD	A,(FST_DOR)
+;	SET	0,A
+;	OUT	(FDC_DOR),A
+;	RES	0,A
+;	OUT	(FDC_DOR),A
+;#ENDIF
 	RET
 ;
 ; SET FST_DOR FOR MOTOR CONTROL ON
@@ -1694,7 +1748,7 @@ FXR_TO:		; TIMEOUT
 ;
 FXR_ABORT:	; EXECUTION ABORTED
 	HB_EI				; INTERRUPTS OK AGAIN
-	JR	FOP_RES			; GET RSEULTS, NO NEED TO PULSE TC
+	JR	FOP_RES			; GET RESULTS, NO NEED TO PULSE TC
 ;
 FXR_END:	; EXECUTION COMPLETED NORMALLY
 	CALL	FC_PULSETC		; PULSE TC TO END EXECUTION
@@ -1828,7 +1882,9 @@ FOP_EVALST1:
 
 	LD	C,FRC_ENDCYL
 	BIT	7,A
-	JR	NZ,FOP_SETFST
+	; THI IS NORMAL BECAUSE WE NOW READ ONLY A SINGLE SECTOR
+	;JR	NZ,FOP_SETFST
+	JR	NZ,FOP_EXIT
 
 	LD	C,FRC_DATAERR
 	BIT	5,A

Source/HBIOS/hbios.asm

@@ -22,7 +22,7 @@
 ;   SYSTEM INITIALIZATION, THE IMAGE OF THE RUNNING ROM BANK IS COPIED TO A RAM BANK
 ;   CREATING A SHADOW COPY IN RAM.  EXECUTION IS THAN TRANSFERRED TO THE RAM SHADOW COPY.
 ;   THIS IS ESSENTIAL BECAUSE THE HBIOS CODE DOES NOT SUPPORT RUNNING IN READ ONLY MEMORY
-;   (EXCEPT FOR THE INITIAL LAUNCHING CODE).  IN THIS MODE, THE HBIOS INITIALIZATION WILL
+;   (EXCEPT FOR THE INITIAL LAUNCHING CODE).  IN THIS MODE, THE HBI OS INITIALIZATION WILL
 ;   ALSO COPY THE OS IMAGES BANK IN ROM TO THE USER RAM BANK AND LAUNCH IT AFTER HBIOS
 ;   IS INSTALLED.
 ;
@@ -1898,8 +1898,8 @@ HB_CPU1:
 ;
 ; INIT OSCILLATOR SPEED FROM CONFIG
 ;
-	LD	HL,CPUOSC / 1000
-	LD	(HB_CPUOSC),HL
+	LD	HL,CPUOSC / 1000	; OSC SPD IN KHZ
+	LD	(HB_CPUOSC),HL		; INIT HB_CPUOSC DEFAULT
 ;
 ; ATTEMPT DYNAMIC CPU SPEED DERIVATION
 ; NOTE THAT FOR PLATFORMS WITH SOFTWARE SELECTABLE CPU SPEED,
@@ -1907,8 +1907,8 @@ HB_CPU1:
 ; POSSIBLE SETTING.  THE FINAL CPU SPEED WILL BE ADJUSTED
 ; LATER.
 ;
-	CALL	HB_CPUSPD		; CPU SPEED DETECTION
-	JR	NZ,HB_CPUSPD2		; SKIP IF FAILED
+	CALL	HB_CPUSPD		; DYNAMIC CPU SPEED DETECTION
+	JR	NZ,HB_CPU2		; SKIP AHEAD IF FAILED
 ;
 ; RECORD THE UPDATED CPU OSCILLATOR SPEED
 ;
@@ -1917,10 +1917,11 @@ HB_CPU1:
 	; SO RECORD DOUBLE THE MEASURED VALUE
 	SLA	L
 	RL	H
-	LD	(HB_CPUOSC),HL
 #ENDIF
 ;
-HB_CPUSPD2:
+	LD	(HB_CPUOSC),HL		; RECORD MEASURED SPEED
+;
+HB_CPU2:
 ;
 ; INIT CPUKHZ BASED ON OSCILLATOR SPEED
 ;
@@ -2231,6 +2232,29 @@ NOT_REC_M0:
 	CALL	DSKY_SHOW
 #ENDIF
 ;
+#IF FPENABLE
+;
+; IF FRONT PANEL IS ENABLED IN CONFIG, WE NEED TO CHECK TO SEE IF THE
+; HARDWARE REALLY EXISTS.  THE ONLY WAY TO DO THAT IS TO SEE IF THE
+; FRONT PANEL PORT SEEMS TO BE VALID (NOT FLOATING).  HERE WE JUST
+; DO THE CHECKING AND RECORD WHETHER THE FP SWITCHES ARE USEABLE.
+;
+	; THE SWITCH HARDWARE MAY OR MAY NOT BE INSTALLED.  SO, HERE WE
+	; ATTEMPT TO CONFIRM WE HAVE A VALID PORT.  CREDIT TO STEPHEN
+	; COUSINS FOR THIS APPROACH.
+	LD	C,FPBASE		; ADR OF SWITCH PORT
+	IN	C,(C)			; READ IT USING IN (C)
+	IN	A,(FPBASE)		; READ IT USING IN (PORT)
+	CP	C			; PORT FLOATING ON MISMATCH
+	JR	NZ,HB_SWZ		; ABORT IF FLOATING
+	CP	$FF			; $FF ALSO MEANS PORT INACTIVE
+	JR	Z,HB_SWZ		; ABORT IF SO
+	OR	$FF			; SIGNAL FP EXISTS
+	LD	(HB_HASFP),A		; AND SAVE IT
+HB_SWZ:
+;
+#ENDIF
+;
 #IF FALSE
 ;
 ; TEST DEBUG ***************************************************************************************
@@ -2247,7 +2271,6 @@ NOT_REC_M0:
 ;
 ;
 ;
-;
 #IF (BOOT_DELAY > 100)
 	.ECHO	"*** ERROR: INVALID BOOT_DELAY (BOOT_DELAY > 100)!!!\n"
 	!!!	; FORCE AN ASSEMBLY ERROR
@@ -2273,6 +2296,29 @@ HB_BOOTDLY:
 	LD	A,BOOTCON		; GET REQUESTED CONSOLE DEV
 	LD	(CB_CONDEV),A		; SAVE IT
 HB_CONRDY:
+;
+; MOST SERIAL PORTS ARE CONFIGURED WITH HARDWARE FLOW CONTROL ENABLED.
+; IF THERE IS A PROBLEM WITH THE RTS SIGNAL, THEN OUTPUT TO THE CONSOLE
+; WILL BE STALLED WHICH CAN LEAD A USER TO THINK THE SYSTEM IS TOTALLY
+; DEAD WHEN, IN FACT, IT IS JUST WAITING FOR RTS TO BE ASSERTED.  ALSO,
+; IF THE USER IS BOOTING TO A CRT DEVICE AND DISCONNECTS THE CONSOLE
+; SERIAL PORT, THE SYSTEM WILL WAIT FOR RTS AND NEVER BOOT.  SO, HERE
+; WE SAVE THE ACTIVE CONSOLE CONFIGURATION, THEN TURN OFF HARDWARE
+; FLOW CONTROL.  THE ORIGINAL CONFIGURATION WILL BE RESTORED BELOW
+; PRIOR TO LAUNCING THE ROM LOADER.
+;
+	; RETRIEVE THE CONFIG FROM THE CONSOLE PORT
+	LD	B,BF_CIOQUERY		; HBIOS QUERY CIO CONFIG
+	LD	A,(CB_CONDEV)		; GET CONSOLE DEVICE
+	LD	(HB_BOOTCON),A		; SAVE IT FOR LATER
+	LD	C,A			; BOOT CONSOLE TO C
+	CALL	HB_DISPATCH		; INTERNAL HBIOS CALL
+	LD	(HB_BOOTCFG),DE		; SAVE CONFIG
+	RES	5,D			; CLEAR RTS BIT
+	LD	B,BF_CIOINIT		; HBIOS CIO INIT
+	LD	A,(CB_CONDEV)		; GET CONSOLE DEVICE
+	LD	C,A			; BOOT CONSOLE TO C
+	CALL	HB_DISPATCH		; INTERNAL HBIOS CALL
 
 #IF (WBWDEBUG == USEMIO)		; OUTPUT ANY CACHED DEBUG TEXT
 	LD	HL,MIOOUTPTR
@@ -2719,8 +2765,10 @@ HB_WDZ:
 	LD	HL,(CB_HEAPTOP)
 	LD	(HEAPCURB),HL
 ;
-; NOW SWITCH TO CRT CONSOLE IF CONFIGURED
+; NOW SWITCH CONSOLES IF CONFIGURED
 ;
+	LD	A,(CB_CONDEV)		; GET CURRENT CONSOLE
+	LD	(HB_NEWCON),A		; AND INIT NEW CONSOLE VAR
 #IF CRTACT
 ;
 ; BIOS IS CONFIGURED TO AUTO ACTIVATE CRT DEVICE.  FIRST,
@@ -2739,20 +2787,107 @@ HB_WDZ:
 	JR	Z,INITSYS3		; Z=SHORTED, BYPASS CONSOLE SWITCH
   #ENDIF
 ;
-	; NOTIFY USER OF CONSOLE SWITCH ON BOOT CONSOLE
-	CALL	NEWLINE2
-	PRTX(STR_SWITCH)
-	CALL	NEWLINE
-;
-	; SWITCH TO CRT CONSOLE
 	LD	A,(CB_CRTDEV)		; GET CRT DISPLAY DEVICE
-	LD	(CB_CONDEV),A		; SAVE IT AS ACTIVE CONSOLE DEVICE
+	LD	(HB_NEWCON),A		; AND QUEUE TO SWITCH
+;
+#ENDIF
+;
+#IF FPENABLE
+;
+; IF WE HAVE FRONT PANEL SWITCHES, THIS IS THE RIGHT PLACE TO HANDLE
+; ANY CONSOLE CHANGE REQUESTS.  THE FRONT PANEL HAS TWO SWITCHES
+; RELATED TO THIS: 1) CRT/SER, AND 2) SEC/PRI.  IF CRT/SER IS SET,
+; THEN WE SWITCH TO THE CRT DEVICE (IF THERE IS ONE).  IF THE SEC/PRI
+; SWITCH IS SET, THEN WE ATTEMPT TO USE THE SECOND SERIAL OR CRT
+; DEVICE.
+;
+	PRTS("\r\nFP: IO=0x$")
+	LD	A,FPBASE
+	CALL	PRTHEXBYTE
+;
+	; THE EXISTENCE OF THE FP WAS TESTED EARLIER.  IF IT DOESN'T
+	; EXIST, BAIL OUT.
+	LD	A,(HB_HASFP)		; GET FP EXISTENCE FLAG
+	OR	A			; SET FLAGS
+	JR	NZ,HB_FP1		; IF WE HAVE ONE, CONTINUE
+;
+	; HANDLE NO FP
+	PRTS(" NOT PRESENT$")
+	JR	HB_FPZ
+;
+HB_FP1:
+	; WE NOW BELIEVE WE HAVE A VALID SWITCH SETTINGS VALUE.
+	; CHECK FOR CRT SWITCH VALUE AND SWITCH TO CRT IF SET.
+	; NOTE THAT CB_CRTDEV WILL BE ZERO IF THERE IS NO CRT DEVICE
+	; IN THE SYSTEM, SO WE DON'T NEED TO CHECK FOR THE EXISTENCE
+	; OF A CRT DEVICE -- IT WILL JUST FAILBACK TO FIRST SERIAL
+	; PORT.
+	PRTS(" SWITCHES=0x$")		; TAG
+	IN	A,(FPBASE)		; GET SWITCH SETTINGS
+	CALL	PRTHEXBYTE		; DISPLAY VALUE
+	LD	B,A			; SAVE IN REG B
+	AND	SW_CRT			; TEST CRT BIT
+	JR	Z,HB_FP2		; SKIP AHEAD IF NOT SET
+	LD	A,(CB_CRTDEV)		; GET CRT DISPLAY DEVICE
+	CP	$FF			; $FF MEANS NO CRT PRESENT
+	JR	Z,HB_FP2		; BYPASS IF SO
+	LD	(HB_NEWCON),A		; QUEUE NEW CONSOLE UNIT
+;
+HB_FP2:
+	; IF SEC SWITCH IS SET, WE WANT TO BUMP TO SECONDARY
+	; CRT OR SERIAL DEVICE.  FOR NOW, WE ARE GOING TO CHEAT AND
+	; JUST INCREMENT THE CONSOLE DEVICE UNIT.  THIS SHOULD WORK
+	; ASSUMING NORMAL ORDERING OF THE CHARACTER DEVICE UNITS.
+	LD	A,B			; RECOVER SWITCH SETTINGS
+	AND	SW_SEC			; TEST SEC BIT
+	JR	Z,HB_FPZ		; IF NOT SET, THEN ALL DONE
+;
+	; INCREMENT CONSOLE UNIT, BUT MAKE SURE IT DOES NOT EXCEED
+	; THE HIGHEST CHAR UNIT IN SYSTEM.
+	LD	A,(CIO_CNT)		; GET CHAR UNIT COUNT
+	LD	B,A			; MOVE TO B
+	LD	A,(HB_NEWCON)		; GET NEW CONSOLE UNIT
+	INC	A			; BUMP TO SECONDARY
+	CP	B			; A (UNIT) >= B (CNT)?
+	JR	NC,HB_FPZ		; ABORT IF UNIT TOO HIGH
+	LD	(HB_NEWCON),A		; UPDATE NEW CONSOLE UNIT
+;
+HB_FPZ:
 ;
-	; DISPLAY HBIOS BANNER ON NEW CONSOLE
-	PRTX(STR_BANNER)
 #ENDIF
 ;
 INITSYS3:
+;
+; IF WE ARE GOING TO SWITCH CONSOLES, IT IS IMPLEMENTED HERE.  A
+; MESSAGE IS PRINTED ON THE OLD CONSOLE INDICATING WHERE THE NEW
+; CONSOLE IS AND THE NEW CONSOLE RECEIVES AN HBIOS BANNER.
+;
+	LD	A,(HB_BOOTCON)		; GET ORIGINAL BOOT CONSOLE DEV
+	LD	C,A			; PUT IN C
+	LD	A,(HB_NEWCON)		; GET NEW CONSOLE DEVICE
+	CP	C			; COMPARE
+	JR	Z,INITSYS3A		; NO CHANGE, BYPASS
+;
+	LD	DE,STR_CONSOLE		; CONSOLE CHANGE NOTIFY
+	CALL	WRITESTR		; PRINT IT
+	LD	A,(HB_NEWCON)		; GET NEW CONSOLE UNIT NUM
+	CALL	PRTDECB			; PRINT UNIT NUM
+	LD	(CB_CONDEV),A		; IMPLEMENT NEW CONSOLE!
+	CALL	NEWLINE2		; FORMATTING
+	LD	DE,STR_BANNER		; POINT TO BANNER
+	CALL	NZ,WRITESTR		; OUTPUT IF CONSOLE MOVED
+;
+INITSYS3A:
+;
+; RESTORE BOOT CONSOLE CONFIGURATION
+;
+	CALL	LDELAY			; ALLOW SERIAL PORT TO FLUSH
+	LD	B,BF_CIOINIT		; HBIOS CIO INIT
+	LD	A,(HB_BOOTCON)		; ORIGINAL BOOT CONSOLE DEVICE
+	LD	C,A			; BOOT CONSOLE TO C
+	LD	DE,(HB_BOOTCFG)		; SAVED ORIGINAL CONSOLE CFG
+	CALL	HB_DISPATCH		; INTERNAL HBIOS CALL
+;
 	CALL	PRTSUM			; PRINT UNIT/DEVICE SUMMARY TABLE
 ;
 #IF 0
@@ -4114,9 +4249,130 @@ SYS_GET:
 	JP	Z,SYS_GETBNKINFO
 	CP	BF_SYSGET_CPUSPD
 	JP	Z,SYS_GETCPUSPD
+	CP	BF_SYSGET_PANEL
+	JP	Z,SYS_GETPANEL
 	SYSCHKERR(ERR_NOFUNC)		; SIGNAL ERROR
 	RET
 ;
+; GET SERIAL UNIT COUNT
+;
+SYS_GETCIOCNT:
+	LD	A,(CIO_CNT)		; GET DEVICE COUNT (FIRST BYTE OF LIST)
+	LD	E,A			; PUT IT IN E
+	XOR	A			; SIGNALS SUCCESS
+	RET
+;
+; GET SERIAL UNIT API FN ADR AND DATA ADR
+;   ENTRY:
+;     D: FUNCTION
+;     E: UNIT
+;   RETURNS:
+;     HL: FUNCTION ADDRESS
+;     DE: DATA BLOB ADDRESS
+;
+SYS_GETCIOFN:
+	BIT	7,E			; CHECK FOR SPECIAL UNIT CODE
+	CALL	NZ,SYS_GETCIOFN1	; IF SO, HANDLE IT
+	LD	IY,CIO_TBL		; POINT TO UNIT TABLE
+	JP	SYS_GETFN		; GO TO COMMON CODE
+;
+SYS_GETCIOFN1:
+	LD	A,(CB_CONDEV)		; UNIT $80 -> CONSOLE UNIT
+	LD	E,A			; REPLACE UNIT VALUE IN C
+	RET				; AND BACK TO REGULAR FLOW
+;
+;
+; GET DISK UNIT COUNT
+;
+SYS_GETDIOCNT:
+	LD	A,(DIO_CNT)		; GET DEVICE COUNT (FIRST BYTE OF LIST)
+	LD	E,A			; PUT IT IN E
+	XOR	A			; SIGNALS SUCCESS
+	RET
+;
+; GET DISK UNIT API FN ADR AND DATA ADR
+;   ENTRY:
+;     D: FUNCTION
+;     E: UNIT
+;   RETURNS:
+;     HL: FUNCTION ADDRESS
+;     DE: DATA BLOB ADDRESS
+;
+SYS_GETDIOFN:
+	LD	IY,DIO_TBL		; POINT TO UNIT TABLE
+	JP	SYS_GETFN		; GO TO COMMON CODE
+;
+; GET RTC UNIT COUNT
+;
+SYS_GETRTCCNT:
+	LD	E,0			; ASSUME 0 RTC DEVICES
+	LD	A,(RTC_DISPACT)		; IS RTC ACTIVE?
+	OR	A			; SET FLAGS
+	JR	Z,SYS_GETRTCCNT1	; IF NONE, DONE
+	INC	E			; SET ONE DEVICE
+SYS_GETRTCCNT1:
+	XOR	A			; SIGNALS SUCCESS
+	RET
+;
+; GET VIDEO UNIT COUNT
+;
+SYS_GETVDACNT:
+	LD	A,(VDA_CNT)		; GET DEVICE COUNT (FIRST BYTE OF LIST)
+	LD	E,A			; PUT IT IN E
+	XOR	A			; SIGNALS SUCCESS
+	RET
+;
+; GET VIDEO UNIT API FN ADR AND DATA ADR
+;   ENTRY:
+;     D: FUNCTION
+;     E: UNIT
+;   RETURNS:
+;     HL: FUNCTION ADDRESS
+;     DE: DATA BLOB ADDRESS
+;
+SYS_GETVDAFN:
+	LD	IY,VDA_TBL		; POINT TO UNIT TABLE
+	JP	SYS_GETFN		; GO TO COMMON CODE
+;
+; GET SOUND UNIT COUNT
+;
+SYS_GETSNDCNT:
+	LD	A,(SND_CNT)		; GET DEVICE COUNT (FIRST BYTE OF LIST)
+	LD	E,A			; PUT IT IN E
+	XOR	A			; SIGNALS SUCCESS
+	RET
+;
+; GET SOUND UNIT API FN ADR AND DATA ADR
+;   ENTRY:
+;     D: FUNCTION
+;     E: UNIT
+;   RETURNS:
+;     HL: FUNCTION ADDRESS
+;     DE: DATA BLOB ADDRESS
+;
+SYS_GETSNDFN:
+	LD	IY,SND_TBL		; POINT TO UNIT TABLE
+	JP	SYS_GETFN		; GO TO COMMON CODE
+;
+; SHARED CODE TO COMPLETE A FUNCTION LOOKUP
+; ENTRY:
+;   IY: DISPATCH FUNCTION TABLE
+;   D: FUNCTION ID
+;   E: UNIT NUMBER
+; EXIT:
+;   HL: DRIVER FUNCTION ADDRESS
+;   DE: DRIVER UNIT DATA ADDRESS
+;
+SYS_GETFN:
+	LD	A,D			; GET FUNC NUM FROM D
+	LD	B,A			; AND PUT IN B
+	LD	A,E			; GET UNIT NUM FROM E
+	LD	C,A			; AND PUT IN C
+	CALL	HB_DISPCALC		; CALC FN ADR & BLOB ADR
+	PUSH	IY			; MOVE DATA ADR
+	POP	DE			; ... TO DE
+	RET				; AF STILL HAS RESULT OF CALC
+;
 ; GET TIMER
 ;   RETURNS:
 ;     DE:HL: TIMER VALUE (32 BIT)
@@ -4274,124 +4530,27 @@ SYS_GETCPUSPD1:
 	OR	$FF
 	RET
 ;
-; GET SERIAL UNIT COUNT
-;
-SYS_GETCIOCNT:
-	LD	A,(CIO_CNT)		; GET DEVICE COUNT (FIRST BYTE OF LIST)
-	LD	E,A			; PUT IT IN E
-	XOR	A			; SIGNALS SUCCESS
-	RET
-;
-; GET SERIAL UNIT API FN ADR AND DATA ADR
-;   ENTRY:
-;     D: FUNCTION
-;     E: UNIT
+; GET FRONT PANEL SWITCH VALUES BYTE
 ;   RETURNS:
-;     HL: FUNCTION ADDRESS
-;     DE: DATA BLOB ADDRESS
+;     L: SWITCH VALUES BYTE
 ;
-SYS_GETCIOFN:
-	BIT	7,E			; CHECK FOR SPECIAL UNIT CODE
-	CALL	NZ,SYS_GETCIOFN1	; IF SO, HANDLE IT
-	LD	IY,CIO_TBL		; POINT TO UNIT TABLE
-	JP	SYS_GETFN		; GO TO COMMON CODE
+SYS_GETPANEL:
 ;
-SYS_GETCIOFN1:
-	LD	A,(CB_CONDEV)		; UNIT $80 -> CONSOLE UNIT
-	LD	E,A			; REPLACE UNIT VALUE IN C
-	RET				; AND BACK TO REGULAR FLOW
-;
-;
-; GET DISK UNIT COUNT
-;
-SYS_GETDIOCNT:
-	LD	A,(DIO_CNT)		; GET DEVICE COUNT (FIRST BYTE OF LIST)
-	LD	E,A			; PUT IT IN E
-	XOR	A			; SIGNALS SUCCESS
-	RET
-;
-; GET DISK UNIT API FN ADR AND DATA ADR
-;   ENTRY:
-;     D: FUNCTION
-;     E: UNIT
-;   RETURNS:
-;     HL: FUNCTION ADDRESS
-;     DE: DATA BLOB ADDRESS
-;
-SYS_GETDIOFN:
-	LD	IY,DIO_TBL		; POINT TO UNIT TABLE
-	JP	SYS_GETFN		; GO TO COMMON CODE
-;
-; GET RTC UNIT COUNT
-;
-SYS_GETRTCCNT:
-	LD	E,0			; ASSUME 0 RTC DEVICES
-	LD	A,(RTC_DISPACT)		; IS RTC ACTIVE?
+#IF FPENABLE
+	LD	A,(HB_HASFP)		; GET FP EXISTS FLAG
 	OR	A			; SET FLAGS
-	JR	Z,SYS_GETRTCCNT1	; IF NONE, DONE
-	INC	E			; SET ONE DEVICE
-SYS_GETRTCCNT1:
-	XOR	A			; SIGNALS SUCCESS
-	RET
-;
-; GET VIDEO UNIT COUNT
-;
-SYS_GETVDACNT:
-	LD	A,(VDA_CNT)		; GET DEVICE COUNT (FIRST BYTE OF LIST)
-	LD	E,A			; PUT IT IN E
-	XOR	A			; SIGNALS SUCCESS
-	RET
-;
-; GET VIDEO UNIT API FN ADR AND DATA ADR
-;   ENTRY:
-;     D: FUNCTION
-;     E: UNIT
-;   RETURNS:
-;     HL: FUNCTION ADDRESS
-;     DE: DATA BLOB ADDRESS
-;
-SYS_GETVDAFN:
-	LD	IY,VDA_TBL		; POINT TO UNIT TABLE
-	JP	SYS_GETFN		; GO TO COMMON CODE
-;
-; GET SOUND UNIT COUNT
-;
-SYS_GETSNDCNT:
-	LD	A,(SND_CNT)		; GET DEVICE COUNT (FIRST BYTE OF LIST)
-	LD	E,A			; PUT IT IN E
-	XOR	A			; SIGNALS SUCCESS
-	RET
-;
-; GET SOUND UNIT API FN ADR AND DATA ADR
-;   ENTRY:
-;     D: FUNCTION
-;     E: UNIT
-;   RETURNS:
-;     HL: FUNCTION ADDRESS
-;     DE: DATA BLOB ADDRESS
-;
-SYS_GETSNDFN:
-	LD	IY,SND_TBL		; POINT TO UNIT TABLE
-	JP	SYS_GETFN		; GO TO COMMON CODE
-;
-; SHARED CODE TO COMPLETE A FUNCTION LOOKUP
-; ENTRY:
-;   IY: DISPATCH FUNCTION TABLE
-;   D: FUNCTION ID
-;   E: UNIT NUMBER
-; EXIT:
-;   HL: DRIVER FUNCTION ADDRESS
-;   DE: DRIVER UNIT DATA ADDRESS
-;
-SYS_GETFN:
-	LD	A,D			; GET FUNC NUM FROM D
-	LD	B,A			; AND PUT IN B
-	LD	A,E			; GET UNIT NUM FROM E
-	LD	C,A			; AND PUT IN C
-	CALL	HB_DISPCALC		; CALC FN ADR & BLOB ADR
-	PUSH	IY			; MOVE DATA ADR
-	POP	DE			; ... TO DE
-	RET				; AF STILL HAS RESULT OF CALC
+	JR	Z,SYS_GETPANEL1		; HANDLE NOT EXISTS
+	IN	A,(FPBASE)		; READ SWITCHES
+	LD	H,0			; FOR FUTURE
+	LD	L,A			; PUT SWITCHES VALUE IN L
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+#ENDIF
+SYS_GETPANEL1:	; HANDLE NON-EXISTENT FRONT PANEL
+	LD	HL,0			; ZERO RESULT VALUE
+	LD	A,ERR_NOHW		; NO HARDWARE ERR
+	OR	A			; SET FLAGS
+	RET				; DONE
 ;
 ; SET SYSTEM PARAMETERS
 ; PARAMETER(S) TO SET INDICATED IN C
@@ -4406,6 +4565,8 @@ SYS_SET:
 	JR	Z,SYS_SETBOOTINFO
 	CP	BF_SYSSET_CPUSPD
 	JR	Z,SYS_SETCPUSPD
+	CP	BF_SYSSET_PANEL
+	JP	Z,SYS_SETPANEL
 	SYSCHKERR(ERR_NOFUNC)		; SIGNAL ERROR
 	RET
 ;
@@ -4681,6 +4842,23 @@ SYS_SETCPUSPD_ERR:
 	OR	$FF			; NOT SUPPORTED
 	RET
 ;
+; SET FRONT PANEL LEDS
+;   ON ENTRY:
+;     L: LED VALUES BYTE
+;
+SYS_SETPANEL:
+;
+#IF DIAGENABLE
+	LD	A,L
+	OUT	(DIAGPORT),A
+	XOR	A
+	RET
+#ELSE
+	LD	A,ERR_NOHW		; NO HARDWARE ERR
+	OR	A			; SET FLAGS
+	RET
+#ENDIF
+;
 ; RETURN A BYTE OF MEMORY FROM SPECIFIED BANK
 ; ENTRY: D=BANK ID, HL=ADDRESS
 ; RETURN: E=BYTE VALUE
@@ -6285,27 +6463,33 @@ HB_CPUSPD1:
   #ENDIF
 
 	; WAIT FOR AN INITIAL TICK TO ALIGN, THEN WAIT
-	; FOR SECOND TICK AND TO GET A FULL ONE SECOND LOOP COUNT
+	; FOR A SECOND TICK TO GET A FULL ONE SECOND LOOP COUNT.
+	; WAITSEC WILL SET ZF IF AN OVERFLOW OCCURS (MEANING THAT THE
+	; CLOCK IS NOT TICKING).  THERE IS NO
+	; POINT IN CALLING HB_WAITSEC AGAIN IN THAT CASE, SO WE ONLY
+	; CALL HB_WAITSEC AGAIN IF ZF IS NOT SET.
 	CALL	DSRTC_START
 	CALL	HB_RDSEC		; GET SECONDS
 	LD	(HB_CURSEC),A		; AND INIT CURSEC
 	CALL	HB_WAITSEC		; WAIT FOR SECONDS TICK
 	LD	(HB_CURSEC),A		; SAVE NEW VALUE
-	CALL	HB_WAITSEC		; WAIT FOR SECONDS TICK
+	; CALL HB_WAITSEC AGAIN, BUT ONLY IF ZF IS NOT SET
+	CALL	NZ,HB_WAITSEC		; WAIT FOR SECONDS TICK
 ;
   #IF (CPUFAM == CPU_Z180)
 	; RESTORE W/S SETTINGS FROM BEFORE TEST
 	POP	AF
 	OUT0	(Z180_DCNTL),A
   #ENDIF
-;
-	LD	A,H
-	OR	L
-	RET	Z			; FAILURE, USE DEFAULT CPU SPEED
 ;
 	; MOVE LOOP COUNT TO HL
 	PUSH	DE
 	POP	HL
+;
+	; CHECK FOR OVERFLOW (NOT TICKING)
+	LD	A,H
+	OR	L
+	JR	Z,HB_CPUSPD2		; FAILURE, USE DEFAULT CPU SPEED
 ;
 	; TIMES 4 FOR CPU SPEED IN KHZ
 ;	RES	0,L			; GRANULARITY
@@ -6321,6 +6505,7 @@ HB_CPUSPD1:
 HB_WAITSEC:
 	; WAIT FOR SECONDS TICK
 	; RETURN SECS VALUE IN A, LOOP COUNT IN DE
+	; ZF IS SET ON OVERFLOW (CLOCK NOT TICKING)
 	LD	DE,0			; INIT LOOP COUNTER
 HB_WAITSEC1:
 ;
@@ -6365,14 +6550,14 @@ HB_RDSEC:
 	CALL	DSRTC_END		; FINISH IT
 	LD	A,E			; VALUE TO A
 	RET
-;
-  #ELSE
-;
-	OR	$FF			; SIGNAL ERROR
-	RET				; NO RTC, ABORT
 ;
 #ENDIF
 ;
+HB_CPUSPD2:
+	; HANDLE NO RTC OR NOT TICKING
+	OR	$FF			; SIGNAL ERROR
+	RET				; AND DONE
+;
 ; SYSTEM CHECK: DUMP MACHINE STATE AND CONTINUE?
 ;
 SYSCHKA:
@@ -7237,7 +7422,8 @@ HB_BOOT_REC	.DB	0		; BOOT MODE (0=NORMAL, 1=RECOVERY MODE)
 ;
 STR_BANNER	.DB	"RomWBW HBIOS v", BIOSVER, ", ", TIMESTAMP, "$"
 STR_PLATFORM	.DB	PLATFORM_NAME, "$"
-STR_SWITCH	.DB	"*** Activating CRT Console ***$"
+;STR_SWITCH	.DB	"*** Activating CRT Console ***$"
+STR_CONSOLE	.DB	"\r\n\r\n  Console on Unit #$"
 STR_BADINT	.DB	"\r\n*** BAD INT ***\r\n$"
 STR_LOWBAT	.DB	"\r\n\r\n+++ LOW BATTERY +++$"
 ;
@@ -7261,6 +7447,12 @@ HB_CURSEC	.DB	0		; CURRENT SECOND (TEMP)
 ;
 HB_BCDTMP	.FILL	5,0		; BCD NUMBER STORAGE (TEMP)
 ;
+HB_BOOTCON	.DB	0		; INITIAL BOOT CONSOLE SAVE AREA
+HB_BOOTCFG	.DW	0		; CONSOLE CONFIG SAVE AREA
+HB_NEWCON	.DB	0		; NEW CONSOLE TO SWITCH TO
+;
+HB_HASFP	.DB	0		; NON-ZERO MEANS FP EXISTS
+;
 HB_WRKBUF	.FILL	512,0		; INTERNAL DISK BUFFER
 ;
 HB_END		.EQU	$

Source/HBIOS/hbios.inc

@@ -109,11 +109,13 @@ BF_SYSGET_CPUINFO	.EQU	$F0	; GET CPU INFORMATION
 BF_SYSGET_MEMINFO	.EQU	$F1	; GET MEMORY CAPACTITY INFO
 BF_SYSGET_BNKINFO	.EQU	$F2	; GET BANK ASSIGNMENT INFO
 BF_SYSGET_CPUSPD	.EQU	$F3	; GET CLOCK SPEED & WAIT STATES
+BF_SYSGET_PANEL		.EQU	$F4	; GET FRONT PANEL SWITCHES VAL
 ;
 BF_SYSSET_TIMER		.EQU	$D0	; SET TIMER VALUE
 BF_SYSSET_SECS		.EQU	$D1	; SET SECONDS VALUE
 BF_SYSSET_BOOTINFO	.EQU	$E0	; SET BOOT INFORMATION
 BF_SYSSET_CPUSPD	.EQU	$F3	; SET CLOCK SPEED & WAIT STATES
+BF_SYSSET_PANEL		.EQU	$F4	; SET FRONT PANEL LEDS
 ;
 BF_SYSINT_INFO		.EQU	$00	; GET INTERRUPT SYSTEM INFO
 BF_SYSINT_GET		.EQU	$10	; GET INT VECTOR ADDRESS
@@ -137,6 +139,7 @@ PLT_DYNO	.EQU	11		; DYNO MICRO-ATX MOTHERBOARD
 PLT_RCZ280	.EQU	12		; RCBUS W/ Z280
 PLT_MBC		.EQU	13		; MULTI BOARD COMPUTER
 PLT_RPH		.EQU	14		; RHYOPHYRE GRAPHICS COMPUTER
+PLT_Z80RETRO	.EQU	15		; Z80 RETRO COMPUTER
 ;
 ; HBIOS GLOBAL ERROR RETURN VALUES
 ;
@@ -261,6 +264,15 @@ DIAG_08 .EQU 11111111B ; ON
 DIAG_09 .EQU 11111111B ; ON 
 #ENDIF
 ;
+; FRONT PANEL SWITCHES
+;
+SW_CRT		.EQU	%10000000	; CRT/SER CONSOLE
+SW_SEC		.EQU	%01000000	; SEC/PRI CONSOLE
+SW_AUTO		.EQU	%00100000	; AUTO/MENU BOOT
+SW_DISK		.EQU	%00010000	; DISK/ROM
+SW_FLOP		.EQU	%00001000	; FLOP/HD
+SW_OPT		.EQU	%00000111	; SLICE/ROM APP
+;
 ; MEDIA ID VALUES
 ;
 MID_NONE	.EQU	0

Source/HBIOS/ide.asm

@@ -1111,6 +1111,7 @@ IDE_PROBE:
 	PRTS(" PROBE$")			; LABEL FOR IO ADDRESS
 #ENDIF
 ;
+	; SELECT DEVICE (MASTER/SLAVE)
 	LD	A,(IDE_DRVHD)
 	;OUT	(IDE_IO_DRVHD),A
 	CALL	IDE_OUT
@@ -1119,21 +1120,44 @@ IDE_PROBE:
 	CALL	PC_SPACE
 	CALL	PRTHEXBYTE
 #ENDIF
-
+;
 	CALL	DELAY			; DELAY ~16US
 ;
-	;LD	C,IDE_IO_STAT
-	;IN	A,(C)
+; TEST FOR PRESENCE OF IDE REGISTERS.  USE LBA0/1 TO SEE
+; IF VALUE CAN BE PERSISTED.  THE USE OF BOTH LBA0 AND LBA1
+; IS TO MAINTAIN CONSISTENCY WITH TGHE THE PPIDE DRIVER BECAUSE
+; PPI ITSELF WILL PERSIST THE LAST VALUE WRITTEN, SO WE USE
+; MULTIPLE REGISTERS TO WORK AROUND THIS FALSE POSITIVE.
+;
+	; $AA -> LBA0
+	LD	A,$AA
+	CALL	IDE_OUT
+	.DB	IDE_REG_LBA0
+;	
+	; $55 => LBA1
+	LD	A,$55
+	CALL	IDE_OUT
+	.DB	IDE_REG_LBA1
+;
+	; TEST LBA0 == $AA
 	CALL	IDE_IN
-	.DB	IDE_REG_STAT
+	.DB	IDE_REG_LBA0
 #IF (IDETRACE >= 3)
 	CALL	PC_SPACE
 	CALL	PRTHEXBYTE
 #ENDIF
-	CP	$FF
-	JP	Z,IDE_NOMEDIA
-	CP	$78
-	JP	Z,IDE_NOMEDIA
+	CP	$AA
+	JP	NZ,IDE_NOMEDIA
+;
+	; TEST LBA1 == $55
+	CALL	IDE_IN
+	.DB	IDE_REG_LBA1
+#IF (IDETRACE >= 3)
+	CALL	PC_SPACE
+	CALL	PRTHEXBYTE
+#ENDIF
+	CP	$55
+	JP	NZ,IDE_NOMEDIA
 ;
 #IF (IDETRACE >= 3)
 	CALL	IDE_REGDUMP
@@ -1159,55 +1183,9 @@ IDE_PROBE0:
 #ENDIF
 	OR	A			; SET FLAGS TO TEST FOR ZERO
 	JP	Z,IDE_NOMEDIA
-;
-	; CHECK SIGNATURE
-#IF (IDETRACE >= 3)
-	CALL	PC_SPACE
-#ENDIF
-	;IN	A,(IDE_IO_COUNT)
-	CALL	IDE_IN
-	.DB	IDE_REG_COUNT
-#IF (IDETRACE >= 3)
-	CALL	PRTHEXBYTE
-#ENDIF
-	CP	$01
-	JP	NZ,IDE_NOMEDIA
-#IF (IDETRACE >= 3)
-	CALL	PC_SPACE
-#ENDIF
-	;IN	A,(IDE_IO_SECT)
-	CALL	IDE_IN
-	.DB	IDE_REG_SECT
-#IF (IDETRACE >= 3)
-	CALL	PRTHEXBYTE
-#ENDIF
-	CP	$01
-	JP	NZ,IDE_NOMEDIA
-#IF (IDETRACE >= 3)
-	CALL	PC_SPACE
-#ENDIF
-	;IN	A,(IDE_IO_CYLLO)
-	CALL	IDE_IN
-	.DB	IDE_REG_CYLLO
-#IF (IDETRACE >= 3)
-	CALL	PRTHEXBYTE
-#ENDIF
-	CP	$00
-	JP	NZ,IDE_NOMEDIA
-#IF (IDETRACE >= 3)
-	CALL	PC_SPACE
-#ENDIF
-	;IN	A,(IDE_IO_CYLHI)
-	CALL	IDE_IN
-	.DB	IDE_REG_CYLHI
-#IF (IDETRACE >= 3)
-	CALL	PRTHEXBYTE
-#ENDIF
-	CP	$00
-	JP	NZ,IDE_NOMEDIA
 ;
 IDE_PROBE1:
-	; SIGNATURE MATCHES ATA DEVICE, RECORD TYPE AND RETURN SUCCESS
+	; ASSUME ATA DEVICE FOR NOW, RECORD TYPE AND RETURN SUCCESS
 	LD	A,IDE_TYPEATA		; TYPE = ATA
 	LD	(IY+IDE_TYPE),A		; SET IT IN INSTANCE DATA
 	XOR	A			; SIGNAL SUCCESS

Source/HBIOS/pio.asm

@@ -1,6 +1,6 @@
 ;
 ;==================================================================================================
-; PIO DRIVER (SERIAL PORT)
+; PIO DRIVER (PARALLEL PORT)
 ;==================================================================================================
 ;
 ;  SETUP PARAMETER WORD:
@@ -12,7 +12,7 @@
 ;
 ; THIS DRIVER IS JUST A STUB TO DETECT AND INITIALIZE PIO HARDWARE
 ; IF IT EXISTS.  FOR NOW, IT DOES NOT REGISTER ANY OF THE PIO CHANNELS
-; AS CHARCTER DEVICE UNITS.
+; AS CHARACTER DEVICE UNITS.
 ;
 PIO_NONE	.EQU	0
 PIO_PIO		.EQU	1
@@ -34,7 +34,7 @@ PIO1B_DAT	.EQU	PIO1BASE + $01
 PIO_PREINIT:
 ;
 ; SETUP THE DISPATCH TABLE ENTRIES
-; NOTE: INTS WILL BE DISABLED WHEN PREINIT IS CALLED AND THEY MUST REMIAIN
+; NOTE: INTS WILL BE DISABLED WHEN PREINIT IS CALLED AND THEY MUST REMAIN
 ; DISABLED.
 ;
 	CALL	PIO_PROBE		; PROBE FOR CHIPS

Source/HBIOS/ppide.asm

@@ -1127,6 +1127,7 @@ PPIDE_PROBE:
 	PRTS(" PROBE$")			; LABEL FOR IO ADDRESS
 #ENDIF
 ;
+	; SELECT DEVICE (MASTER/SLAVE)
 	LD	A,(PPIDE_DRVHD)
 	;OUT	(IDE_IO_DRVHD),A
 	CALL	PPIDE_OUT
@@ -1135,30 +1136,44 @@ PPIDE_PROBE:
 	CALL	PC_SPACE
 	CALL	PRTHEXBYTE
 #ENDIF
-
+;
 	CALL	DELAY			; DELAY ~16US
 ;
-	; BELOW TESTS FOR EXISTENCE OF AN IDE CONTROLLER ON THE
-	; PPIDE INTERFACE.  WE WRITE A VALUE OF ZERO FIRST SO THAT
-	; THE PPI BUS HOLD WILL RETURN A VALUE OF ZERO IF THERE IS
-	; NOTHING CONNECTED TO PPI PORT A.  THEN WE READ THE STATUS
-	; REGISTER.  IF AN IDE CONTROLLER IS THERE, IT SHOULD ALWAYS
-	; RETURN SOMETHING OTHER THAN ZERO.  IF AN IDE CONTROLLER IS
-	; THERE, THEN THE VALUE WRITTEN TO PPI PORT A IS IGNORED
-	; BECAUSE THE WRITE SIGNAL IS NEVER PULSED.
-	XOR	A
-	;OUT	(PPIDE_IO_DATALO),A
-	LD	C,(IY+PPIDE_DATALO)	; PPI PORT A, DATALO
-	OUT	(C),A
-;	IN	A,(PPIDE_REG_STAT)	; GET STATUS
+; TEST FOR PRESENCE OF IDE REGISTERS.  USE LBA0/1 TO SEE
+; IF VALUE CAN BE PERSISTED.  THE USE OF BOTH LBA0 AND LBA1
+; IS TO MAINTAIN CONSISTENCY WITH TGHE THE PPIDE DRIVER BECAUSE
+; PPI ITSELF WILL PERSIST THE LAST VALUE WRITTEN, SO WE USE
+; MULTIPLE REGISTERS TO WORK AROUND THIS FALSE POSITIVE.
+;
+	; $AA -> LBA0
+	LD	A,$AA
+	CALL	PPIDE_OUT
+	.DB	PPIDE_REG_LBA0
+;	
+	; $55 => LBA1
+	LD	A,$55
+	CALL	PPIDE_OUT
+	.DB	PPIDE_REG_LBA1
+;
+	; TEST LBA0 == $AA
 	CALL	PPIDE_IN
-	.DB	PPIDE_REG_STAT
+	.DB	PPIDE_REG_LBA0
 #IF (PPIDETRACE >= 3)
 	CALL	PC_SPACE
 	CALL	PRTHEXBYTE
 #ENDIF
-	OR	A
-	JP	Z,PPIDE_NOMEDIA
+	CP	$AA
+	JP	NZ,PPIDE_NOMEDIA
+;
+	; TEST LBA1 == $55
+	CALL	PPIDE_IN
+	.DB	PPIDE_REG_LBA1
+#IF (PPIDETRACE >= 3)
+	CALL	PC_SPACE
+	CALL	PRTHEXBYTE
+#ENDIF
+	CP	$55
+	JP	NZ,PPIDE_NOMEDIA
 ;
 #IF (PPIDETRACE >= 3)
 	CALL	PPIDE_REGDUMP
@@ -1184,55 +1199,9 @@ PPIDE_PROBE0:
 #ENDIF
 	OR	A			; SET FLAGS TO TEST FOR ZERO
 	JP	Z,PPIDE_NOMEDIA		; CONTINUE IF NON-ZERO
-;
-	; CHECK SIGNATURE
-#IF (PPIDETRACE >= 3)
-	CALL	PC_SPACE
-#ENDIF
-	;IN	A,(PPIDE_REG_COUNT)
-	CALL	PPIDE_IN
-	.DB	PPIDE_REG_COUNT
-#IF (PPIDETRACE >= 3)
-	CALL	PRTHEXBYTE
-#ENDIF
-	CP	$01
-	JP	NZ,PPIDE_NOMEDIA
-#IF (PPIDETRACE >= 3)
-	CALL	PC_SPACE
-#ENDIF
-	;IN	A,(PPIDE_REG_SECT)
-	CALL	PPIDE_IN
-	.DB	PPIDE_REG_SECT
-#IF (PPIDETRACE >= 3)
-	CALL	PRTHEXBYTE
-#ENDIF
-	CP	$01
-	JP	NZ,PPIDE_NOMEDIA
-#IF (PPIDETRACE >= 3)
-	CALL	PC_SPACE
-#ENDIF
-	;IN	A,(PPIDE_REG_CYLLO)
-	CALL	PPIDE_IN
-	.DB	PPIDE_REG_CYLLO
-#IF (PPIDETRACE >= 3)
-	CALL	PRTHEXBYTE
-#ENDIF
-	CP	$00
-	JP	NZ,PPIDE_NOMEDIA
-#IF (PPIDETRACE >= 3)
-	CALL	PC_SPACE
-#ENDIF
-	;IN	A,(PPIDE_REG_CYLHI)
-	CALL	PPIDE_IN
-	.DB	PPIDE_REG_CYLHI
-#IF (PPIDETRACE >= 3)
-	CALL	PRTHEXBYTE
-#ENDIF
-	CP	$00
-	JP	NZ,PPIDE_NOMEDIA
 ;
 PPIDE_PROBE1:
-	; SIGNATURE MATCHES ATA DEVICE, RECORD TYPE AND RETURN SUCCESS
+	; ASSUME ATA DEVICE FOR NOW, RECORD TYPE AND RETURN SUCCESS
 	LD	A,PPIDE_TYPEATA		; TYPE = ATA
 	LD	(IY+PPIDE_TYPE),A	; SET IT IN INSTANCE DATA
 	XOR	A			; SIGNAL SUCCESS

Source/HBIOS/romldr.asm

@@ -41,6 +41,7 @@ bel	.equ	7	; ASCII bell
 bs	.equ	8	; ASCII backspace
 lf	.equ	10	; ASCII linefeed
 cr	.equ	13	; ASCII carriage return
+del	.equ	127	; ASCII del/rubout
 ;
 cmdbuf	.equ	$80	; cmd buf is in second half of page zero
 cmdmax	.equ	60	; max cmd len (arbitrary), must be < bufsiz
@@ -179,6 +180,30 @@ start1:
 	call	pstr			; do it
 	call	clrbuf			; zero fill the cmd buffer
 ;
+#if (BIOS == BIOS_WBW)
+;
+	ld	b,BF_SYSGET		; HBIOS SysGet
+	ld	c,BF_SYSGET_PANEL	; ... Panel swiches value
+	rst	08			; do it
+	jr	nz,nofp			; no switches, skip over
+	ld	a,l			; put value in A
+	ld	(switches),a		; save it
+;
+	call	nl			; formatting
+	ld	hl,str_switches		; tag
+	call	pstr			; display
+	ld	a,(switches)		; get switches value
+	call	prthexbyte		; display
+;
+	ld	a,(switches)		; get switches value
+	and	SW_AUTO			; auto boot?
+	call	nz,runfp		; process front panel
+;
+nofp:
+	; fall thru
+;
+#endif
+;
 #if (BOOT_TIMEOUT != -1)
 	; Initialize auto command timeout downcounter
 	or	$FF			; auto cmd active value
@@ -211,12 +236,12 @@ prompt:
 	ld	hl,msg_sel		; boot select msg
 	call	DSKY_SHOW		; show on DSKY
 
- #IF (DSKYMODE == DSKYMODE_NG)
+ #if (DSKYMODE == DSKYMODE_NG)
 	call 	DSKY_PUTLED
 	.db 	$3f,$3f,$3f,$3f,$00,$00,$00,$00
 	call 	DSKY_BEEP
 	call 	DSKY_L2ON
- #ENDIF
+ #endif
 
 #endif
 ;
@@ -365,6 +390,125 @@ runcmd2:
 	ld	(bootslice),a		; save boot slice
 	jp	diskboot		; boot the disk unit/slice
 ;
+#if (BIOS == BIOS_WBW)
+;
+;=======================================================================
+; Process Front Panel switches
+;=======================================================================
+;
+runfp:
+	ld	a,(switches)		; get switches value
+	and	SW_DISK			; disk boot?
+	jr	nz,fp_diskboot		; handle disk boot
+;
+fp_romboot:
+	; Handle FP ROM boot
+	ld	a,(switches)		; get switches value
+	and	SW_OPT			; isolate options bits
+	ld	hl,fpapps		; rom apps cmd char list
+	call	addhla			; point to the right one
+	ld	a,(hl)			; get it
+;
+	; Attempt ROM application launch
+	ld	ix,(ra_tbl_loc)		; point to start of ROM app tbl
+	ld	c,a			; save command in C
+fp_romboot1:
+	ld	a,(ix+ra_conkey)	; get match char
+	and	~$80			; clear "hidden entry" bit
+	cp	c			; compare
+	jp	z,romload		; if match, load it
+	ld	de,ra_entsiz		; table entry size
+	add	ix,de			; bump IX to next entry
+	ld	a,(ix)			; check for end
+	or	(ix+1)			; ... of table
+	jr	nz,fp_romboot1		; loop till done
+	ret				; no match, return
+;
+fpapps	.db	"MBFPCZNU"
+;
+fp_diskboot:
+	; get count of disk units
+	ld	b,BF_SYSGET		; HBIOS Get function
+	ld	c,BF_SYSGET_DIOCNT	; HBIOS DIO Count sub fn
+	rst	08			; call HBIOS
+	ld	a,e			; count to A
+	ld	(diskcnt),a		; save it
+	or	a			; set flags
+	ret	z			; bort if no disk units
+	ld	a,(switches)		; get switches value
+	and	SW_FLOP			; floppy switch bit
+	jr	nz,fp_flopboot		; handle auto flop boot
+	; fall thru for auto hd boot
+;
+fp_hdboot:
+	; Find the first hd with media and boot to that unit using
+	; the slice specified by the FP switches.
+	ld	a,(diskcnt)		; get disk count
+	ld	b,a			; init loop counter
+	ld	c,0			; init disk index
+fp_hdboot1:
+	push	bc			; save loop control
+	ld	b,BF_DIODEVICE		; HBIOS Disk Device func
+	rst	08			; unit in C, do it
+	pop	bc			; restore loop control
+	ld	a,d			; device type to A
+	cp	DIODEV_IDE		; type IDE or greater is HD
+	jr	c,fp_hdboot2		; if not, continue loop
+	push	bc			; save loop control
+	ld	b,BF_DIOMEDIA		; HBIOS Sense Media
+	ld	e,1			; perform media discovery
+	rst	08			; do it
+	pop	bc			; restore loop control
+	jr	z,fp_hdboot3		; if has media, go boot it
+fp_hdboot2:
+	inc	c			; else next disk
+	djnz	fp_hdboot1		; loop thru all disks
+	ret				; nothing works, abort
+;
+fp_hdboot3:
+	ld	a,c			; disk unit to A
+	ld	(bootunit),a		; save it
+	ld	a,(switches)		; get switches value
+	and	SW_OPT			; isolate slice value
+	ld	(bootslice),a		; save it
+	jp	diskboot		; do it
+;
+fp_flopboot:
+	; Find the nth floppy drive and boot to that unit.  The
+	; floppy number is based on the option switches.
+	ld	a,(diskcnt)		; get disk count
+	ld	b,a			; init loop counter
+	ld	c,0			; init disk index
+	ld	a,(switches)		; get switches value
+	and	SW_OPT			; isolate option bits
+	ld	e,a			; floppy unit down counter
+	inc	e			; pre-increment for ZF check
+fp_flopboot1:
+	push	bc			; save loop control
+	push	de			; save floppy down ctr
+	ld	b,BF_DIODEVICE		; HBIOS Disk Device func
+	rst	08			; unit in C, do it
+	ld	a,d			; device type to A
+	pop	de			; restore loop control
+	pop	bc			; restore floppy down ctr
+	cp	DIODEV_FD		; type FD?
+	jr	nz,fp_flopboot3		; if not floppy, skip
+	dec	e			; decrement down ctr
+	jr	z,fp_flopboot2		; if ctr expired, boot this unit
+fp_flopboot3:
+	inc	c			; else next disk
+	djnz	fp_flopboot1		; loop thru all disks
+	ret				; nothing works, abort
+;
+fp_flopboot2:
+	ld	a,c			; disk unit to A
+	ld	(bootunit),a		; save it
+	xor	a		;	; zero accum
+	ld	(bootslice),a		; floppy boot slice is always 0
+	jp	diskboot		; do it
+;
+#endif
+;
 ;=======================================================================
 ; Process a DSKY command from key in A
 ;=======================================================================
@@ -1281,6 +1425,8 @@ rdln_nxt:
 	call	cin			; get a character
 	cp	bs			; backspace?
 	jr	z,rdln_bs		; handle it if so
+	cp	del			; del/rubout?
+	jr	z,rdln_bs		; handle as backspace
 	cp	cr			; return?
 	jr	z,rdln_cr		; handle it if so
 ;
@@ -2165,6 +2311,7 @@ str_upd		.db	"XModem Flash Updater",0
 str_user	.db	"User App",0
 str_egg		.db	"",0
 str_net		.db	"Network Boot",0
+str_switches	.db	"FP Switches = 0x",0
 newcon		.db	0
 newspeed	.db	0
 ;
@@ -2191,6 +2338,8 @@ ra_tbl_loc	.dw	0		; points to active ra_tbl
 bootunit	.db	0		; boot disk unit
 bootslice	.db	0		; boot disk slice
 loadcnt		.db	0		; num disk sectors to load
+switches	.db	0		; front panel switches
+diskcnt		.db	0		; disk unit count value
 ;
 ;=======================================================================
 ; Pad remainder of ROM Loader

Source/HBIOS/sd.asm

@@ -282,6 +282,35 @@ SD_INVCS	.EQU	FALSE		; INVERT CS
 #ENDIF
 ;
 ;
+#IF (SDMODE == SDMODE_PIO)		; Z80 PIO
+;
+;	These mappings work for the RCbus Gluino card with an Arduino
+;	shield attached and are the ones also used in other bitbang setups
+;	directly attached to a PIO. It also works on a straight digital I/O
+;	port as the config writes will disappear into oblivion harmlessly
+;	
+;	The Gluino mapping (ie Arduino pin mapping equivalent) is thus
+;	D10 SS, D11 CIPO, D12 COPI, D13 SCL.
+;
+;	For speed reasons MISO/MOSI are mapped to the top and bottom bits.
+;	RomWBW doesn't yet use this fact but the optimized Fuzix routines do.
+;
+SD_DEVMAX	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
+SD_IOBASE	.EQU	$69		; IO BASE ADDRESS FOR SD INTERFACE
+SD_OPRREG	.EQU	SD_IOBASE	; OUTPUT PORT (OUTPUT: CS, CLK, DIN)
+SD_OPRDEF	.EQU	%11111111	; OUTPUT PORT DEFAULT STATE
+SD_INPREG	.EQU	SD_IOBASE	; INPUT REGISTER
+SD_CS0		.EQU	%00001000	; SELECT
+SD_CLK		.EQU	%00010000	; CLOCK
+SD_DI		.EQU	%00000001	; DATA IN (CARD <- CPU) MOSI
+SD_DO		.EQU	%10000000	; DATA OUT (CARD -> CPU) MISO
+SD_CINIT	.EQU	TRUE		; INITIALIZE OUTPUT PORT
+SD_DDR		.EQU	$6B		; DATA DIRECTION REGISTER
+SD_DDRVAL	.EQU	%11100110	; DATA DIRECTION REGISTER VALUE
+SD_INVCS	.EQU	TRUE		; INVERT CS
+#ENDIF
+;
+;
 #IF (SDMODE == SDMODE_USR)		; USER DEFINED HARDWARE CONFIGURATION
 ;
 ; THIS MODE IS INTENDED TO ALLOW A USER TO EASILY CONFIGURE A CUSTOM
@@ -304,6 +333,27 @@ SD_DDRVAL	.EQU	%00001101	; DATA DIRECTION REGISTER VALUE
 SD_INVCS	.EQU	FALSE		; INVERT CS
 #ENDIF
 ;
+#IF (SDMODE == SDMODE_Z80R)		; Z80 Retro
+;
+;	SPLIT OVER TWO REGISTERS TO DRIVE CLK. THE CS LINE IS ON THE GPIO
+;	WHICH IS THE SAME LATCHES THAT CONTROL MMU ON/OFF, SO DON;T GLITCH
+;	THEM WHEN UPDATING!
+;
+SD_DEVMAX	.EQU	1		; NUMBER OF PHYSICAL UNITS (SOCKETS)
+SD_OPRDEF	.EQU	%00000001	; OUTPUT PORT DEFAULT STATE
+SD_OPRMSK	.EQU	%00000101	; OUTPUT PORT MASK
+SD_OPRREG	.EQU	$64		; CS VIA GPIO
+SD_IOBASE	.EQU	$68		; 68/69 FOR OUTPUT
+SD_IOREG	.EQU	SD_IOBASE	; INPUT REGISTER
+SD_IOCLK	.EQU	SD_IOBASE+1	; CLOCK IS OFF A0
+SD_GPIO		.EQU	$64		; MISO IS ON THE GPIO
+SD_CS0		.EQU	%00000100	; SELECT
+SD_DI		.EQU	%00000001	; DATA IN (CARD <- CPU) MOSI
+SD_DO		.EQU	%00000001	; DATA OUT (CARD -> CPU) MISO
+SD_CINIT	.EQU	FALSE		; INITIALIZE OUTPUT PORT
+SD_INVCS	.EQU	FALSE		; INVERT CS
+#ENDIF
+;
 #IF (SD_DEVCNT > SD_DEVMAX)
 	.ECHO	"*** ERROR: SDCNT EXCEEDS MAXIMUM SUPPORTED BY INTERFACE!!!\n"
 	!!!	; FORCE AN ASSEMBLY ERROR
@@ -510,6 +560,22 @@ SD_INIT:
 	CALL	PRTHEXBYTE
 #ENDIF
 ;
+#IF (SDMODE == SDMODE_PIO)
+	PRTS(" MODE=PIO$")
+	PRTS(" IO=0x$")
+	LD	A,SD_IOBASE
+	CALL	PRTHEXBYTE
+#ENDIF
+;
+#IF (SDMODE == SDMODE_Z80R)
+	PRTS(" MODE=Z80R$")
+	PRTS(" IO=0x$")
+	LD	A,SD_IOBASE
+	CALL	PRTHEXBYTE
+	LD	A,SD_OPRDEF
+	LD	(SD_OPRVAL),A
+#ENDIF
+;
 #IF (SDMODE == SDMODE_USR)
 	PRTS(" MODE=USER$")
 	PRTS(" IO=0x$")
@@ -1736,6 +1802,17 @@ SD_SETUP:
 	OUT	(SD_OPRREG),A		; OPRREG == SIO_MCR
 #ENDIF
 ;
+#IF (SDMODE == SDMODE_PIO)
+	LD	A,SD_OPRDEF		; All output bits high
+	OUT	(SD_OPRREG),A
+	LD	A,$CF			; Port B mode 3
+	OUT	(SD_DDR),A
+	LD	A,SD_DDRVAL		; Set the direction bits
+	OUT	(SD_DDR),A
+	LD	A,$07			; No interrupts
+	OUT	(SD_DDR),A
+#ENDIF
+;
 #IF (SDMODE == SDMODE_USR)
   #IF (SD_CINIT == TRUE)
 	LD	A,(SD_OPRMSK)		; GET OUTPUT PORT MASK
@@ -1863,7 +1940,7 @@ SD_DESELECT:
 	AND	~SD_CS0
 #ENDIF
 ; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS
-#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC))
+#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_PIO) | (SDMODE == SDMODE_Z80R))
   #IF ((SDMODE == SDMODE_SC) & (SD_DEVCNT > 1))
 	XOR	SD_CS0 | SD_CS1
   #ELSE
@@ -1910,9 +1987,48 @@ SD_PUT:
 	SET	4,A			; SET TRANSMIT ENABLE
 	OUT0	(SD_CNTR),A
   #ELSE
-    #IF (SDMODE == SDMODE_UART)
+
+    #IF (SDMODE == SDMODE_Z80R)
+	; USE C - THE CALLING CODE FOR COMMAND SEND FAILS TO SAVE HL/DE
+	; WHILST THE OTHER PATHS DO ?
+        LD	C,A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	RL	C
+	RLA
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+    #ELSE
+
+      #IF (SDMODE == SDMODE_UART)
 	XOR	$FF			; DI IS INVERTED ON UART
-    #ENDIF
+      #ENDIF
 	LD	C,A			; C=BYTE TO SEND
 	LD	B,8			; SEND 8 BITS (LOOP 8 TIMES)
 	LD	A,(SD_OPRVAL)		; LOAD CURRENT OPR VALUE
@@ -1928,6 +2044,7 @@ SD_PUT1:
 	DJNZ	SD_PUT1			; REPEAT FOR ALL 8 BITS
 	LD	A,(SD_OPRVAL)		; LOAD CURRENT OPR VALUE
 	OUT	(SD_OPRREG),A		; LEAVE WITH CLOCK LOW
+    #ENDIF
   #ENDIF
 #ENDIF
 	RET				; DONE
@@ -1950,34 +2067,83 @@ SD_GET:
 	CALL	MIRROR			; MSB<-->LSB MIRROR BITS
 	LD	A,C			; KEEP RESULT
   #ELSE
+    #IF (SDMODE == SDMODE_Z80R)
+	; MUST PRESERVE HL,DE
+	PUSH	DE
+	LD	A,1
+	LD	C,SD_GPIO
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	OUT	(SD_IOREG),A
+	OUT	(SD_IOCLK),A
+	IN	B,(C)
+	RR	B
+	RL	E
+	LD	A,E
+	POP	DE
+    #ELSE
 	LD	B,8			; RECEIVE 8 BITS (LOOP 8 TIMES)
 	LD	A,(SD_OPRVAL)		; LOAD CURRENT OPR VALUE
 SD_GET1:
 	XOR	SD_CLK			; TOGGLE CLOCK
 	OUT	(SD_OPRREG),A		; UPDATE CLOCK
 	IN	A,(SD_INPREG)		; READ THE DATA WHILE CLOCK IS ACTIVE
-    #IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_PPI))
+      #IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_PIO))
 	RLA				; ROTATE INP:7 INTO CF
-    #ENDIF
-    #IF (SDMODE == SDMODE_N8)
+      #ENDIF
+      #IF (SDMODE == SDMODE_N8)
 	RLA				; ROTATE INP:6 INTO CF
 	RLA				; "
-    #ENDIF
-    #IF (SDMODE == SDMODE_UART)
+      #ENDIF
+      #IF (SDMODE == SDMODE_UART)
 	RLA				; ROTATE INP:5 INTO CF
 	RLA				; "
 	RLA				; "
-    #ENDIF
-    #IF (SDMODE == SDMODE_DSD)
+      #ENDIF
+      #IF (SDMODE == SDMODE_DSD)
 	RRA				; ROTATE INP:0 INTO CF
-    #ENDIF
+      #ENDIF
 	RL	C			; ROTATE CF INTO C:0
 	LD	A,(SD_OPRVAL)		; BACK TO INITIAL VALUES (TOGGLE CLOCK)
 	OUT	(SD_OPRREG),A		; DO IT
 	DJNZ	SD_GET1			; REPEAT FOR ALL 8 BITS
 	LD	A,C			; GET BYTE RECEIVED INTO A
-    #IF (SDMODE == SDMODE_UART)
+      #IF (SDMODE == SDMODE_UART)
 	XOR	$FF			; DO IS INVERTED ON UART
+      #ENDIF
     #ENDIF
   #ENDIF
 #ENDIF

Source/HBIOS/sio.asm

@@ -60,13 +60,20 @@ SIO0B_CMD	.EQU	SIO0BASE + $03
 SIO0B_DAT	.EQU	SIO0BASE + $01
 #ENDIF
 ;
-#IF (SIO0MODE == SIOMODE_ZP)		
+#IF (SIO0MODE == SIOMODE_ZP)
 SIO0A_CMD	.EQU	SIO0BASE + $06
 SIO0A_DAT	.EQU	SIO0BASE + $04 
 SIO0B_CMD	.EQU	SIO0BASE + $07
 SIO0B_DAT	.EQU	SIO0BASE + $05
 #ENDIF
 ;
+#IF (SIO0MODE == SIOMODE_Z80R)
+SIO0A_CMD	.EQU	SIO0BASE + $03
+SIO0A_DAT	.EQU	SIO0BASE + $01
+SIO0B_CMD	.EQU	SIO0BASE + $02
+SIO0B_DAT	.EQU	SIO0BASE + $00
+#ENDIF
+;
 #IF (SIOCNT >= 2)
 ;
   #IF (SIO1MODE == SIOMODE_STD)
@@ -97,6 +104,13 @@ SIO1B_CMD	.EQU	SIO1BASE + $07
 SIO1B_DAT	.EQU	SIO1BASE + $05
   #ENDIF
 ;
+#IF (SIO1MODE == SIOMODE_Z80R)
+SIO1A_CMD	.EQU	SIO0BASE + $03
+SIO1A_DAT	.EQU	SIO0BASE + $01 
+SIO1B_CMD	.EQU	SIO0BASE + $02
+SIO1B_DAT	.EQU	SIO0BASE + $00
+#ENDIF
+;
 #ENDIF
 ;
 SIO_PREINIT:
@@ -785,10 +799,14 @@ SIO_INITBROK:
 ;
 ; SET RECEIVE DATA BITS WR3 
 ;	
+	LD	A,D			; HI WORD OF CONFIG
+	AND	%00100000		; BIT 5 IS AUTO-CTS
+	LD	H,A			; SAVE IN H
 	LD	A,L			; DATA BITS
 	AND	$C0			; CLEAR OTHER BITS
-	OR	$21			; CTS/DCD AUTO, RX ENABLE
-;	
+	OR	$01			; RX ENABLE
+	OR	H			; COMBINE WITH AUTO-CTS
+;
 	LD	(SIO_WR3),A
 ;
 ; SAVE CONFIG PERMANENTLY NOW

Source/HBIOS/std.asm

@@ -1,5 +1,5 @@
 ; The purpose of this file is to define generic symbols and to include
-; the requested build configuraton file to bring in platform specifics.
+; the requested build configuration file to bring in platform specifics.
 
 ; There are several hardware platforms supported by SBC.
 ; 1.  SBC	Z80 SBC (v1 or v2) w/ ECB interface
@@ -16,6 +16,7 @@
 ; 12. RCZ280	Z280 CPU on RCBUS or ZZ80MB
 ; 13. MBC	Andrew Lynch's Multi Board Computer
 ; 14. RPH	Andrew Lynch's RHYOPHYRE Graphics Computer
+; 15. Z80RETRO	Peter Wilson's Z80-Retro Computer
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;
@@ -91,6 +92,15 @@ FDM360		.EQU	2		; 5.25" FLOPPY, 360KB, 2 SIDES, 40 TRKS, 9 SECTORS
 FDM120		.EQU	3		; 5.25" FLOPPY, 1.2MB, 2 SIDES, 80 TRKS, 15 SECTORS
 FDM111		.EQU	4		; 8" FLOPPY, 1.11MB, 2 SIDES, 74 TRKS, 15 SECTORS
 ;
+; FLOPPY DISK TYPE
+;
+FDT_NONE	.EQU	0		; NONE
+FDT_3DD		.EQU	1		; 3.5" FLOPPY, DOUBLE DENSITY
+FDT_3HD		.EQU	2		; 3.5" FLOPPY, HIGH DENSITY
+FDT_5DD		.EQU	3		; 5.25" FLOPPY, DOUBLE DENSITY
+FDT_5HD		.EQU	4		; 5.25" FLOPPY, HIGH DNSITY
+FDT_8		.EQU	5		; 8" FLOPPY, DOUBLE DENSITY
+;
 ; ZILOG CTC MODE SELECTIONS
 ;
 CTCMODE_NONE	.EQU	0		; NO CTC
@@ -116,6 +126,7 @@ SIOMODE_STD	.EQU	1		; STD SIO REG CFG (EZZ80, KIO)
 SIOMODE_RC	.EQU	2		; RCBUS SIO MODULE (SPENCER OWEN)
 SIOMODE_SMB	.EQU	3		; RCBUS SIO MODULE (SCOTT BAKER)
 SIOMODE_ZP	.EQU	4		; ECB-ZILOG PERIPHERALS BOARD
+SIOMODE_Z80R	.EQU	5		; SIO A/B SWAPPED
 ;
 ; TYPE OF CONSOLE BELL TO USE
 ;
@@ -182,6 +193,8 @@ SDMODE_MK4	.EQU	7		; MARK IV
 SDMODE_SC	.EQU	8		; SC (Steve Cousins)
 SDMODE_MT	.EQU	9		; MT (Shift register SPI WIZNET for RCBUS)
 SDMODE_USR	.EQU	10		; USER DEFINED (in sd.asm) (NOT COMPLETE)
+SDMODE_PIO	.EQU	11		; Z80 PIO bitbang
+SDMODE_Z80R	.EQU	12		; Z80 Retro
 ;
 ; AY SOUND CHIP MODE SELECTIONS
 ;

Source/HBIOS/uart.asm

@@ -78,11 +78,13 @@ UART1_IVT	.EQU	IVT(INT_UART1)
 ;
 ;
 UART_PREINIT:
+#IF (UART4)
 ;
 ; INIT UART4 BOARD CONFIG REGISTER (NO HARM IF IT IS NOT THERE)
 ;
 	LD	A,$80			; SELECT 7.3728MHZ OSC & LOCK CONFIG REGISTER
 	OUT	(UART4BASE+$0F),A	; DO IT
+#ENDIF
 ;
 ; SETUP THE DISPATCH TABLE ENTRIES
 ;
@@ -737,7 +739,7 @@ UART_DETECT2:
 	LD	A,C			; RETURN RESULT IN A
 	RET
 ;
-; DETERMINE TEH UART CHIP VARIANT AND RETURN IN A
+; DETERMINE THE UART CHIP VARIANT AND RETURN IN A
 ;
 UART_CHIP:
 ;

Source/Images/ReadMe.txt

@@ -105,7 +105,7 @@ where:
     <disk> specifies the disk contents (e.g., "cpm22")
     <type> specifies disk type ("fd" for floppy, or "hd" for hard disk)
     <format> specifies the disk format which must be one of:
-        - "fd144": 1.44M floppy disk
+      - "fd144": 1.44M floppy disk
 	- "hd512": hard disk with 512 directory entries
 	- "hd1k": hard disk with 1024 directory entries
     <system> optionally specifies a boot system image to place in the
@@ -203,10 +203,11 @@ command prompt:
   | C:\RomWBW\Binary>copy /b hd1k_prefix.dat + hd1k_zsdos.img + hd1k_ws4.img hd_multi.img
 
 Since the hd512 format does not utilize a partition, you do not
-prefix the hd512_xxx.img files with anything.  They are ready to write
-to your media as is.
+prefix the hd512_xxx.img files with anything.  You can simply
+concatenate the desired hd512_xxx.img files together and write the
+resulting file to the start of your hard disk media.
 
-In general, the hd1k format is considered the better format to use. 
+In general, the hd1k format is considered the preferred format to use. 
 It provides double the directory space and places all slices inside 
 of a hard disk partition that DOS/Windows should respect as "used" 
 space.

Source/Images/d_cpm22/ReadMe.txt

@@ -8,7 +8,7 @@ RomWBW Loader prompt.
 
 The remainder of this document describes the usage and contents of
 this disk.  It is highly recommended that you review the "RomWBW
-Getting Started.pdf" document found in the Doc directory of the
+User Guide.pdf" document found in the Doc directory of the
 RomWBW Distribution.
 
 == Usage ==

Source/Images/d_dos65/ReadMe.txt

@@ -0,0 +1,34 @@
+===== DOS/65 Disk for RomWBW =====
+
+This disk is one of several ready-to-run disks provided with RomWBW.  
+It contains the files to start and run DOS/65 on an MBC system that
+contains Dan Werner's 6502 processor.
+
+WARNING: This is a work in progress.  Use of this disk image requires
+specific hardware and configuration.  You should contact Dan Werner
+before attempting to use this disk image.
+
+The remainder of this document describes the usage and contents of
+this disk.  It is highly recommended that you review the "RomWBW
+User Guide.pdf" document found in the Doc directory of the
+RomWBW Distribution.
+
+== Usage ==
+
+  - The disk is configured to boot under ZSDOS 1.1 (via primary Z80
+    CPU).  Once booted, you can launch DOS/65 on a secondary 6502
+    CPU using the "DOS65" command.
+    
+== Notes ==
+
+  - DOS/65 is generally compatible with the CP/M 2.2 filesystem.  Once
+    launched, you will have access to the fielsystem of the boot disk.
+
+  - DOS/65 does not utilize any of the RomWBW framework or drivers, so
+    it will only support devices built into DOS/65 itself.  Once
+    launched DOS/65 takes over the hardware completely.
+    
+  - The contents of this disk are purely a redistribution of the work
+    of Dan Werner.
+
+-- WBW 2:47 PM 3/16/2023

Source/Images/d_dos65/u0/alloc.s19

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